CN220552935U - Test system - Google Patents

Abstract

The application relates to a test system comprising: at least two output data source modules; the multiplexing selection module is connected with each output data source module and is used for switching and outputting test patterns corresponding to the output data source modules; the waveform synthesis module is connected with the multiplexing selection module, receives the test pattern output by the multiplexing selection module and outputs a synthesized waveform; the time sequence generating module is connected with the waveform synthesizing module and used for receiving the synthesized waveform output by the waveform synthesizing module and generating an output waveform; the pin circuit module is connected with the time sequence generating module and the device to be tested, receives the output waveform generated by the time sequence generating module and outputs an excitation signal to the device to be tested. The advanced wave form synthesis is adopted, and then the processing mode of time sequence generation is carried out to obtain the output wave form, so that the delay compensation error is reduced, the wave form output function can be realized by adopting a general chip, and the design cost is reduced.

Description

Test system

Technical Field

The present application relates to the field of signal processing technologies, and in particular, to a test system.

Background

The automatic semiconductor test refers to the detection of various parameter indexes of a tested device (Device Under Test, DUT) by using a tester, and the rejection of defective products to control the factory quality of the semiconductor device. In the traditional testing machine, the time sequence generation and waveform synthesis depend on a special IC (Integrated Circuit ) chip, the implementation structure is complex, and the defect of high design complexity exists.

Disclosure of Invention

Based on this, it is necessary to provide a test system capable of reducing design complexity in order to solve the above-mentioned problems.

A test system, comprising:

at least two output data source modules;

the multiplexing selection module is connected with each output data source module and is used for switching and outputting test patterns corresponding to the output data source modules;

a waveform synthesis module (Format Controller, FC module) connected to the multiplexing selection module, for receiving the test pattern output by the multiplexing selection module, and outputting a synthesized waveform;

a Timing Generator (TG module) connected to the waveform synthesis module, for receiving the synthesized waveform output by the waveform synthesis module and generating an output waveform;

and the pin circuit module (Pin Electronics Driver/calculator, PE module) is connected with the time sequence generating module and the device to be tested, receives the output waveform generated by the time sequence generating module and outputs an excitation signal to the device to be tested.

In one embodiment, the output data source module includes an algorithmic pattern generating module (Algorithmic Pattern Generator, ALPG module) and a pattern generating module (Pattern Generator, PG module).

In one embodiment, the test system further includes a comparison processing module, which connects the timing generation module and the waveform synthesis module;

the pin circuit module receives an input signal fed back by the device to be tested and outputs a comparison signal to the time sequence generation module;

the time sequence generating module receives the comparison signal output by the pin circuit module and outputs a sampling signal to the comparison processing module;

and the comparison processing module receives the sampling signal output by the time sequence generating module and outputs a comparison result.

In one embodiment, the test system further comprises a timing control module (Timing Controller, TC module) for setting a delay time of the timing generation module, and the timing generation module is connected to the waveform synthesis module through the timing control module.

In one embodiment, the test system further comprises an error address memory module (Address Fail Memory, AFM module) coupled to the comparison processing module.

In one embodiment, the test system further includes a memory error repair analysis module (Memory Repair Analysis, MRA module) coupled to the error address memory module.

In one embodiment, the test system further includes a debug module, which connects the comparison processing module and the waveform synthesis module.

In one embodiment, the test system further comprises a test unit processor (Test Unit Processor, TUP module) connected to the debug module.

In one embodiment, the timing generation module includes at least one of a CARRY module, an IDELAY, and an ODELAY.

In one embodiment, the timing generation module is a digital control delay chain chip.

According to the test system, the multiplexing selection module selects the corresponding output data source module to output the test waveform, the waveform synthesis module receives the test pattern to carry out waveform synthesis to obtain a synthesized waveform, and the time sequence generation module generates the output waveform. And finally, the pin circuit module generates an excitation signal according to the received output waveform and sends the excitation signal to the device to be tested. The advanced wave form synthesis is adopted, and then the processing mode of time sequence generation is carried out to obtain the output wave form, so that the delay compensation error is reduced, the wave form output function can be realized by adopting a general chip, and the design cost is reduced.

Drawings

FIG. 1 is a schematic diagram of a test system in one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and the like, specify the presence of stated features, integers, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, or groups thereof.

The current testing machine has the function architecture that the time delay of the data is adjusted firstly, and then the adjusted signals are converted and output according to the required waveform format, which requires that the waveform format conversion circuit delay of each channel is as consistent as possible, or the circuit delay difference between the channels is compensated into the data delay. The time sequence generation and waveform synthesis in the current testing machine depend on a special chip, cannot be realized by using a general FPGA (Filed Programmable Gate Array, field programmable logic array), and the special chip has a complex realization structure.

Based on the above, in order to solve the problem that the delay requirements of the inter-channel waveform format conversion circuit introduced by firstly delaying data and then converting waveform formats are equal, or additional circuit delay difference compensation is introduced, the application provides a test system, a multiplexing selection module selects a corresponding output data source module to output test waveforms, a waveform synthesis module receives test patterns to synthesize waveform formats to obtain synthesized waveforms, and a time sequence generation module delays the synthesized waveforms to obtain output waveforms. And finally, the pin circuit module generates an excitation signal according to the received output waveform and sends the excitation signal to the device to be tested. The output waveform is obtained by adopting advanced waveform synthesis and then a processing mode of time sequence generation, is insensitive to the delay of the waveform format conversion part, can perform the delay compensation among channels, can reduce the delay compensation error without calculating the format conversion part, can realize the waveform output function by adopting a universal FPGA chip, and reduces the design cost.

In one embodiment, as shown in fig. 1, a test system is provided, which includes an output data source module, a multiplexing selection module MUX, a waveform synthesis module FC, a timing generation module TG and a pin circuit module PE, where the number of output data source modules is at least two, the multiplexing selection module MUX is connected to each output data source module, the waveform synthesis module FC is connected to the multiplexing selection module MUX, the timing generation module TG is connected to the waveform synthesis module FC, and the pin circuit module PE is connected to the timing generation module TG and the DUT to be tested.

The multiplexing selection module MUX switches and outputs the test pattern corresponding to the output data source module, and the waveform synthesis module FC receives the test pattern output by the multiplexing selection module MUX and outputs the synthesized waveform; the time sequence generating module TG receives the synthesized waveform output by the waveform synthesizing module FC and generates an output waveform; the pin circuit module PE receives the output waveform generated by the time sequence generating module TG, outputs an excitation signal to the DUT to be tested, and tests the DUT to be tested. The DUT may be a chip to be tested or other devices.

The types of the output data source modules can be the same or different. When the types of the output data source modules are the same, switching to other standby output data source modules when one of the output data source modules fails, so as to ensure the normal operation of the test system; when the types of the output data source modules are different, the multiplexing selection module MUX can be used for switching the output data source modules of the corresponding types to output the test patterns according to actual needs, and the application scene is expanded. In this embodiment, the output data source module includes an algorithm graphic generation module ALPG and a graphic generation module PG, which are both connected to the multiplexing selection module MUX.

Specifically, the algorithm pattern generating module ALPG automatically generates an original data stream according to a written program, the pattern generating module PG generates an original data stream according to a specified test vector, and the multiplexing selecting module MUX is used for selecting to use the algorithm pattern generating module ALPG or the pattern generating module PG to generate a test pattern. And the waveform synthesis module FC synthesizes the waveform format of the test pattern according to the configured waveform format to obtain a synthesized waveform. The type of waveform format is not unique and may include, for example, NRZ, RZ, XORBC, etc. The timing generation module TG delays the input synthesized waveform to obtain an output waveform. The specific structure of the timing generation block TG is also not unique, and may be a combination of one or more of an IDELAY (input delay unit), an ODELAY (output delay unit), and a CARRY block. Specifically, the delay width of the timing generation module TG covers the clock period, and the signal delay can be realized by a dedicated resource such as IDELAY, ODELAY, CARRY inside the FPGA. In other embodiments, the timing generation module TG may also implement signal delay using a digitally controlled delay chain chip. The pin circuit module PE is responsible for level control of excitation signals, comparison threshold control of input signals and the like. The pin circuit module PE receives the output waveform generated by the timing generation module TG, converts the output waveform into an excitation signal according to a set level threshold value (VIH\VIL), and sends the excitation signal to the DUT, and the level amplitude of the excitation signal is suitable for the DUT through level conversion. The pin circuit module PE also compares and judges the input signals fed back by the DUT to be tested according to a preset level threshold value and outputs comparison signals. Further, the timing generation module TG also samples the comparison signal output by the pin circuit module PE based on the main sampling clock frequency of the system operation.

In one embodiment, the test system further includes a comparison processing module CP, which connects the timing generation module TG and the waveform synthesis module FC. The pin circuit module PE receives an input signal fed back by a device DUT to be tested and outputs a comparison signal to the time sequence generation module TG; the timing sequence generation module TG receives the comparison signal output by the pin circuit module PE and outputs a sampling signal to the comparison processing module CP; the comparison processing module CP receives the sampling signal output from the timing generation module TG, and outputs a comparison result.

Specifically, the pin circuit module PE compares and judges the input signals in combination with the threshold value voh\threshold value VOL, and outputs the corresponding output signal ca\output signal CB. When the input signal is smaller than the threshold value VOL, the output signal CA is at a low level, and the output signal CB is at a low level; when the input signal is between the threshold value VOL and the threshold value VOH, the output signal CA is low level, and the output signal CB is high level; when the input signal is greater than the threshold value VOH, the output signal CA is at a high level and the output signal CB is at a high level. The timing sequence generating module TG samples the output signal ca\output signal CB, and the obtained sampling signal is sent to the comparing and processing module CP. The comparison processing module CP may analyze the two paths of sampling signals according to a set comparison truth table to determine an actual sampling value, and further determine whether the sampling signal is consistent with the expected value according to the actual sampling value and a preset expected value, so as to obtain a comparison result.

In addition, the test system further comprises a time sequence control module TC for performing time delay time setting on the time sequence generation module TG, and the time sequence generation module TG is connected with the waveform synthesis module FC through the time sequence control module TC. The time sequence control module TC is used for calculating according to the set position and sampling position of the sending signal edge, analyzing the delay time of the time sequence generation module TG, and further realizing the control of the signal edge position and the sampling position through the time sequence generation module TG, and realizing the signal sending and the sampling of the input signal meeting the time sequence. The timing control module TC determines the output beat of the signal edge and the delay time in a single clock according to the output signal edge timing information fed by the waveform synthesis module FC. The timing control module TC also determines the sampling clock beat of the signal and the signal delay time information in the single clock according to the input signal sampling position information fed by the waveform synthesis module FC, and feeds the output beat of the signal edge, the delay time in the single clock, the sampling clock beat and the signal delay time information in the single clock to the timing generation module TG. The time sequence generating module TG delays and outputs the output signal according to the beat information and the delay information fed in by the time sequence control module TC, and delays and samples the input signal, so that the synthesis of the time sequence relation of the output signal edge and the fine control of the sampling position of the input signal are realized.

In the test system, the multiplexing selection module MUX selects the corresponding output data source module to output the test waveform, the waveform synthesis module FC receives the test pattern to perform waveform synthesis to obtain a synthesized waveform, and the timing sequence generation module TG generates the output waveform. Finally, the pin circuit module PE generates an excitation signal according to the received output waveform and sends the excitation signal to the DUT to be tested. The advanced wave form synthesis is adopted, and then the processing mode of time sequence generation is carried out to obtain the output wave form, so that the delay compensation error is reduced, the wave form output function can be realized by adopting a general chip, and the design cost is reduced.

In one embodiment, with continued reference to FIG. 1, the test system further includes an error address memory module AFM coupled to the comparison processing module CP. The error address memory module AFM is used for judging address information corresponding to the dislocation bit of the device to be tested in the process of recording and testing the device to be tested DUT so as to retest and repair the dislocation address after the test is finished.

In one embodiment, the test system further includes a memory error repair analysis module MRA, which is coupled to the error address memory module AFM. The memory error repair analysis module MRA is used for analyzing the error address information recorded by the error address memory module AFM, optimizing to obtain a repair strategy, and controlling the repair treatment of the DUT memory to be tested.

In one embodiment, the test system further comprises a Debug module Debug, which connects the comparison processing module CP and the waveform synthesis module FC. The Debug module is used in cooperation with a software tool and is used for grabbing theoretical waveforms and actual waveforms excited to the DUT to be tested by the test system, expected waveforms and sampling waveforms fed back to the test system after the DUT to be tested responds, and the like, so that the debugging module is convenient for debugging, analyzing and debugging the running state of codes and the working state of the DUT to be tested.

In one embodiment, the test system further comprises a test unit processor TUP connected to the Debug module Debug. The test unit processor TUP is used to run a software tool by which the test person can analyze the stimulus waveform and the response waveform.

Specifically, the execution flow of the test system is as follows:

1. the algorithm pattern generating module ALPG\pattern generating module PG generates a test pattern data stream, and carries out flow control according to the signals fed back by the waveform synthesis module FC, so as to ensure that the waveform synthesis module FC has continuous data stream supply.

2. The multiplexing selection module MUX selects whether to use the algorithmic pattern generating module ALPG or the test pattern generated by the pattern generating module PG according to the setting.

3. The waveform synthesis module FC synthesizes waveform format according to the test pattern, determines each output signal edge time sequence information and input signal sampling position information according to the pattern time sequence index, controls waveform synthesis processing speed according to the feedback signal of the time sequence control module TC, and further controls the fed-in data flow by the feedback algorithm pattern generation module ALPG\pattern generation module PG.

4. The timing control module TC determines the clock of the edge output of the signal and the delay time in a single clock for the decomposition of the output synthesized waveform signal, determines the sampling clock of the signal and the signal delay time information in a single clock for the sampling position of the input sampled signal, and feeds the above information to the timing generation module TG.

5. The time sequence generating module TG delays and outputs the output signal according to the beat information and the delay information fed in by the time sequence control module TC, and delays and samples the input signal, so that the synthesis of the time sequence relation of the output signal edge and the fine control of the sampling position of the input signal are realized.

6. The waveform synthesized by the time sequence generating module TG is fed into the pin circuit module PE, and the pin circuit module PE synthesizes signals in a high-low level state according to the set VIH/VIL level information and feeds the signals into the device DUT to be tested as excitation signals.

7. The DUT responds to the fed stimulus signal and outputs a signal to the pin circuit module PE.

8. The pin circuit module PE compares signals fed in by the DUT to be tested according to the set VOH\VOL level to obtain an output signal CA\and transmits the output signal CB to the time sequence generating module TG.

9. The timing generation module TG finely samples the output signal ca\output signal CB fed in by the pin circuit module PE according to the sampling time information transmitted from the timing control module TC, and outputs the sampled signal to the comparison processing module CP.

10. The algorithm pattern generating module ALPG and the test pattern generated by the pattern generating module PG are converted into expected values sampled by each row of time sequence generating module TG in the waveform synthesizing module FC, and the expected values are fed into the comparison processing module CP so that the comparison processing module CP can compare and analyze the sampled signals; the waveform synthesis module FC also feeds the expected values and the original output theoretical waveforms for each row into the Debug module Debug.

11. The comparison processing module CP performs table lookup matching comparison on the sampling signal output by the timing sequence generating module TG to obtain whether the signal output by the device DUT to be tested is High level (High), low level (Low) or High resistance (highZ), and uses the matching comparison result to compare with the expected value fed in by the waveform synthesis module FC to judge whether the sampling value is consistent with the expected value, if so, true is output, otherwise False is output, and the comparison result is fed into the error address memory module AFM.

12. The error address memory module AFM records corresponding address information according to the error information fed in by the comparison processing module CP, and feeds the error address information into the memory error repair analysis module MRA.

13. The memory error repair analysis module MRA analyzes the distribution rule of error bits according to the error address information fed in by the error address memory module AFM, and optimizes to obtain an optimal repair strategy to repair the DUT memory to be tested.

14. The Debug module debugs records the synthesized theoretical waveform of the transmitted waveform and the synthesized excitation waveform actually transmitted to the DUT according to the configuration, records the expected waveform and the actual waveform of the DUT response to be tested, and uploads the related waveform information to a software analysis tool of the test unit processor TUP.

15. The test unit processor TUP runs a software analysis tool, collects relevant waveform information captured by the Debug module Debug, and presents the relevant waveform information to a tester in a GUI (Graphical User Interface ) mode, so that the tester can Debug and analyze whether the running state of the test program is normal, whether the working state of the device DUT to be tested is normal, and the like.

According to the testing system, in the flow of waveform format synthesis and waveform time sequence synthesis, the waveform format is synthesized firstly, then the edges of the waveform format are moved in time sequence, and finally the output waveform is synthesized, so that the testing system can be realized in an FPGA device more easily, phase switching of a clock is not needed, and the design complexity is reduced. In the time sequence synthesis technology of the synthesized waveform, the time sequence synthesis technology is divided into two parts, namely time sequence calculation control and time sequence generation, and the functions of decomposing time sequence parameters and generating time sequence delay of requirements are respectively realized. In the realization technology of synthesizing waveform time sequence synthesis and dynamically adjusting sampling positions of input signal signals, the flexibility of time sequence synthesis is improved by moving the signals instead of adjusting the frequency and the phase of a main frequency clock.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the utility model. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (10)

1. A test system, comprising:

at least two output data source modules;

the multiplexing selection module is connected with each output data source module and is used for switching and outputting test patterns corresponding to the output data source modules;

the waveform synthesis module is connected with the multiplexing selection module, receives the test pattern output by the multiplexing selection module and outputs a synthesized waveform;

the time sequence generation module is connected with the waveform synthesis module, receives the synthesized waveform output by the waveform synthesis module and generates an output waveform;

the pin circuit module is connected with the time sequence generating module and the device to be tested, receives the output waveform generated by the time sequence generating module and outputs an excitation signal to the device to be tested.

2. The test system of claim 1, wherein the output data source module comprises an algorithmic pattern generation module and a pattern generation module.

3. The test system of claim 1, further comprising a comparison processing module connecting the timing generation module and the waveform synthesis module;

the pin circuit module receives an input signal fed back by the device to be tested and outputs a comparison signal to the time sequence generation module;

the time sequence generating module receives the comparison signal output by the pin circuit module and outputs a sampling signal to the comparison processing module;

and the comparison processing module receives the sampling signal output by the time sequence generating module and outputs a comparison result.

4. The test system of claim 3, further comprising a timing control module for delaying the timing generation module, the timing generation module being coupled to the waveform synthesis module via the timing control module.

5. The test system of claim 3, further comprising an error address memory module coupled to the comparison processing module.

6. The test system of claim 5, further comprising a memory error repair analysis module coupled to the error address memory module.

7. The test system of claim 3, further comprising a debug module, the debug module connecting the comparison processing module and the waveform synthesis module.

8. The test system of claim 7, further comprising a test unit processor, the test unit processor coupled to the debug module.

9. The test system of any of claims 1-8, wherein the timing generation module comprises at least one of a carrier module, an IDELAY, and an ODELAY.

10. The test system of any one of claims 1-8, wherein the timing generation module is a digitally controlled delay chain chip.