CN220543689U

CN220543689U - Chip thermistor

Info

Publication number: CN220543689U
Application number: CN202321953456.0U
Authority: CN
Inventors: 雷小冬; 苏雨波; 易新龙
Original assignee: Shenzhen Shunluo Layered Electronics Co ltd
Current assignee: Shenzhen Shunluo Layered Electronics Co ltd
Priority date: 2023-07-24
Filing date: 2023-07-24
Publication date: 2024-02-27
Anticipated expiration: 2033-07-24

Abstract

The utility model discloses a chip thermistor, which comprises a ceramic body, two end electrodes respectively arranged at two ends of the ceramic body and a plurality of layers of inner electrodes arranged in the ceramic body, wherein each layer of inner electrodes comprises a middle inner electrode and a connecting end inner electrode connected with the end electrode; the middle inner electrode is provided with two overlapping areas and a non-overlapping area connected between the two overlapping areas, and the width of the overlapping area is larger than that of the non-overlapping area; the overlapping area of the middle inner electrode overlaps with the corresponding overlapping area of the connecting end inner electrode. The overlapping region of the intermediate inner electrode extends beyond the range of the overlapping region of the terminal inner electrode in the width direction, or vice versa. The utility model can reduce the use amount of the internal paste under the condition of not influencing the overlapping area and the resistance accuracy of the electrodes by reducing the electrode width of the non-overlapping area, thereby reducing the manufacturing cost while ensuring that the resistance accuracy of the product is not influenced.

Description

Chip thermistor

Technical Field

The utility model relates to the technical field of electronic components, in particular to a chip thermistor.

Background

A thermistor is a sensor resistor whose resistance value changes with a change in temperature. Positive temperature coefficient thermistors (PTC thermistors) and negative temperature coefficient thermistors (NTC thermistors) are classified according to temperature coefficients. The resistance value of the positive temperature coefficient thermistor increases with an increase in temperature, and the resistance value of the negative temperature coefficient thermistor decreases with an increase in temperature.

In recent years, with the continuous expansion of the demands of industries such as electronic products, automobiles and the like for chip thermistor products, competition is also increasingly intense, and reduction of manufacturing cost is an effective way for improving competitiveness. At present, the chip thermistor design controls the product resistance by controlling the electrode spacing and the overlapping area, but the printing area is larger, the internal paste use amount is high, and the manufacturing cost is not reduced. Moreover, the electrode deviation in the preparation process of the product has influence on the product resistance, so that the high-precision qualification rate of the product is lower.

It should be noted that the information disclosed in the above background section is only for understanding the background of the present application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

The utility model aims to solve the problems in the background art and provides a chip thermistor.

In order to achieve the above purpose, the present utility model adopts the following technical scheme:

in a first aspect, the present utility model provides a chip thermistor, including a ceramic body, two end electrodes respectively disposed at both ends of the ceramic body, and a multilayer internal electrode disposed in the ceramic body, the multilayer internal electrode including a middle internal electrode and a connecting end internal electrode connected to the end electrodes;

the middle inner electrode is provided with two overlapping areas and a non-overlapping area connected between the two overlapping areas, and the width of the overlapping area is larger than that of the non-overlapping area;

the overlapping area of the middle inner electrode overlaps with the corresponding overlapping area of the connecting end inner electrode;

the overlapping region of the middle inner electrode extends beyond the range of the corresponding overlapping region of the connecting end inner electrode in the width direction, or the corresponding overlapping region of the connecting end inner electrode extends beyond the range of the overlapping region of the middle inner electrode in the width direction;

wherein the width direction exceeds a range of 5 μm to 100 μm.

In some embodiments, the overlapping region of the intermediate inner electrode is rectangular.

In some embodiments, the non-overlapping region of the intermediate inner electrode is the same width as the non-overlapping region of the terminal inner electrode.

In some embodiments, the two overlapping regions of the intermediate inner electrode are equally wide.

In some embodiments, the width of the intermediate inner electrode is 1/5 to 4/5 of the width of the ceramic body.

In a second aspect, the present utility model also provides another chip thermistor, including a ceramic body, two terminal electrodes respectively disposed at both ends of the ceramic body, and a multilayer internal electrode disposed in the ceramic body;

at least one internal electrode has an overlapping region and a non-overlapping region, and the width of the overlapping region is greater than that of the non-overlapping region;

the overlapping region of the at least one internal electrode overlaps with a corresponding overlapping region of an internal electrode of an adjacent layer, and the corresponding overlapping region extends beyond the range of the overlapping region in the width direction;

wherein the width direction exceeds a range of 5 μm to 100 μm.

In some embodiments, the overlapping region of the inner electrode concentrically overlaps a corresponding overlapping region of an inner electrode of an adjacent layer.

In some embodiments, the multi-layered inner electrode includes three layers of inner electrodes, a first connected inner electrode connected to the end electrode, a second connected inner electrode, and an intermediate inner electrode, the intermediate inner electrode having a first overlapping region, a second overlapping region, and a non-overlapping region connected between the first overlapping region and the second overlapping region, the first overlapping region having a width smaller than a width of the second overlapping region, the overlapping region of the first connected inner electrode overlapping the first overlapping region of the intermediate inner electrode, the overlapping region of the second connected inner electrode overlapping the second overlapping region of the intermediate inner electrode; the overlapping region of the first connecting end inner electrode extends beyond the range of the first overlapping region in the width direction; the second overlap region extends beyond the range of the overlap region of the second terminal inner electrode in the width direction.

In some embodiments, the multi-layered inner electrode includes two-layered inner electrodes, a first terminal inner electrode and a second terminal inner electrode connected to the terminal electrode, respectively, and an overlapping region of the first terminal inner electrode overlaps an overlapping region of the second terminal inner electrode.

In some embodiments, the multi-layered inner electrode comprises five layers of inner electrodes, namely a first connected inner electrode and a second connected inner electrode which are respectively distributed in a first layer, a third layer and a fifth layer and are connected with the end electrodes, and an intermediate inner electrode which is distributed in a second layer and a fourth layer, wherein the overlapping area of the first connected inner electrode overlaps with the first overlapping area of the intermediate inner electrode, and the overlapping area of the second connected inner electrode overlaps with the second overlapping area of the intermediate inner electrode; wherein the relationship of the width and the size of each overlapping area which are overlapped is alternately changed along the direction perpendicular to the layers.

The utility model has the following beneficial effects:

in the first aspect of the utility model, the middle inner electrode of the chip thermistor is provided with two overlapping areas and a non-overlapping area connected between the two overlapping areas, and the width of the overlapping area is larger than that of the non-overlapping area.

In the second aspect of the utility model, at least one inner electrode of the chip thermistor has an overlapping region and a non-overlapping region, the width of the overlapping region is larger than that of the non-overlapping region, the overlapping region of the at least one inner electrode overlaps with the corresponding overlapping region of the inner electrode of the adjacent layer, and the corresponding overlapping region extends beyond the range of the overlapping region in the width direction. Therefore, the utility model not only can effectively reduce the influence of electrode deviation on the product resistance, thereby improving the high-precision qualification rate of the product, but also can save the use amount of internal slurry and reduce the production cost.

Other advantages of embodiments of the present utility model are further described below.

Drawings

Fig. 1 is a schematic diagram showing a front view of a chip thermistor according to an embodiment of the present utility model.

Fig. 2 is a schematic top view of a chip thermistor according to an embodiment of the present utility model.

Fig. 3 is a schematic side view of a chip thermistor according to an embodiment of the present utility model.

Fig. 4 is a schematic illustration of an electrode according to an embodiment of the utility model.

Fig. 5 is a flowchart of a method for manufacturing a chip thermistor according to an embodiment of the present utility model.

Fig. 6 is a schematic view of an electrode in a comparative example.

Fig. 7 is a schematic diagram showing a front view of a chip thermistor according to an embodiment of the present utility model.

Fig. 8 is a schematic top view of a chip thermistor according to an embodiment of the present utility model.

Fig. 9 is a schematic side view of a chip thermistor according to an embodiment of the present utility model.

Fig. 10 is a schematic view of a large square electrode according to an embodiment of the utility model.

FIG. 11 is a schematic view of a large and small rectangular electrode according to one embodiment of the utility model.

Fig. 12a to 12d are schematic views of electrode misalignment according to an embodiment of the present utility model.

Fig. 13 is a schematic view of a large and small circular electrode according to another embodiment of the present utility model.

Fig. 14 is a schematic diagram showing a front view of a chip thermistor according to another embodiment of the present utility model.

Fig. 15 is a schematic structural diagram of a 2-layer electrode according to an embodiment of the present utility model.

Fig. 16 is a schematic diagram of a structure using 5 layers of electrodes according to an embodiment of the present utility model.

Fig. 17 is a schematic structural view of an electrode with elliptical overlapping regions according to an embodiment of the present utility model.

Detailed Description

The utility model will be further described with reference to the following drawings in conjunction with the preferred embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.

It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element. In addition, the connection may be for both a fixing action and a coupling or communication action.

It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing embodiments of the utility model and to simplify the description by referring to the figures, rather than to indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the utility model.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present utility model, the meaning of "plurality" is two or more, unless explicitly defined otherwise.

Referring to fig. 1 to 6, an embodiment of the present utility model provides a chip thermistor, which includes a ceramic body 1, two terminal electrodes 4 respectively disposed at two ends of the ceramic body 1, and a multi-layer internal electrode disposed in the ceramic body 1, wherein the multi-layer internal electrode includes a middle internal electrode 5 and connecting terminal internal electrodes 8 and 9 connected with the terminal electrodes 4; the middle inner electrode 5 has two overlapping regions 2 and a non-overlapping region 3 connected between the two overlapping regions 2, and the width of the overlapping region 2 is greater than the width of the non-overlapping region 3; the overlapping region 2 of the intermediate inner electrode 5 overlaps the corresponding overlapping region of the terminal inner electrode, and the overlapping region 2 of the intermediate inner electrode extends beyond the extent of the corresponding overlapping region of the terminal inner electrodes 8, 9 in the width direction. In another embodiment, the corresponding overlap region of the terminal inner electrode may extend beyond the overlap region 2 of the intermediate inner electrode in the width direction (not shown). Wherein the width direction exceeds a range of 5 μm to 100 μm.

In the present utility model, the overlap region means that one internal electrode is disposed to form a major portion of an overlap area with a corresponding internal electrode of an adjacent layer, which has a larger width than a non-overlap region, and the non-overlap region may also form an overlap with a corresponding internal electrode of an adjacent layer, but the non-overlap region has a smaller width than the overlap region, which is not a major portion of an overlap area with an internal electrode of an adjacent layer. The utility model effectively eliminates the adverse effect of deviation between the inner electrodes on the precision of the resistance value of the thermistor when the thermistor is manufactured by utilizing the difference of the overlapping area and the non-overlapping area in width, and improves the high-precision qualification rate of the product.

In some embodiments, the overlap region 2 of the intermediate inner electrode 5 is rectangular, but the specific shape of the overlap region 2 is not limited to rectangular.

In some embodiments, the non-overlapping region 3 of the intermediate inner electrode 5 is the same width as the non-overlapping region of the terminal inner electrode. In other embodiments, the two may also be unequal in width.

In some embodiments, the two overlapping areas 2 of the intermediate inner electrode 5 are equally wide. In other embodiments, the two may also be unequal in width.

In some embodiments, the width of the intermediate inner electrode 5 is 1/5 to 4/5 of the width of the ceramic body 1.

According to the embodiments of the utility model, the middle inner electrode of the chip thermistor is provided with two overlapping areas and a non-overlapping area connected between the two overlapping areas, and the width of the overlapping area is larger than that of the non-overlapping area.

Referring to fig. 7 to 17, another chip thermistor according to an embodiment of the present utility model is also provided, which includes a ceramic body 1, two terminal electrodes 4 respectively disposed at two ends of the ceramic body 1, and a multi-layer internal electrode disposed in the ceramic body 1; at least one of the inner electrodes has an overlap region 2 and a non-overlap region 3, and the width of the overlap region 2 is greater than the width of the non-overlap region 3; the overlapping region 2 of the at least one inner electrode overlaps a corresponding overlapping region of an inner electrode of an adjacent layer, and the corresponding overlapping region extends beyond the range of the overlapping region 2 in the width direction. Wherein the width direction exceeds a range of 5 μm to 100 μm.

In some embodiments, the overlap region 2 of the inner electrode concentrically overlaps a corresponding overlap region of an inner electrode of an adjacent layer.

In different embodiments, the overlapping area 2 of the inner electrode and the corresponding overlapping area of the inner electrode of the adjacent layer may be configured in shapes of rectangles, circles, ovals, etc. of concentric shapes and different sizes, and the present utility model is not limited to the specific shape.

As shown in fig. 7 and 8, in some embodiments, the multi-layered inner electrode includes three layers of inner electrodes, a first terminal inner electrode 9, a second terminal inner electrode 8, and an intermediate inner electrode 5, which are connected to the terminal electrode 4, respectively, the intermediate inner electrode 5 having a first overlap region 7, a second overlap region 6, and a non-overlap region 3 connected between the first overlap region 7 and the second overlap region 6, the first overlap region 7 having a width smaller than that of the second overlap region 6. As shown in fig. 8, the overlapping region of the first connecting end internal electrode 9 overlaps the first overlapping region 7 of the intermediate internal electrode 5, and the overlapping region of the first connecting end internal electrode 9 extends beyond the extent of the first overlapping region 7 in the width direction; the overlapping region of the second terminal inner electrode 8 overlaps the second overlapping region 6 of the intermediate inner electrode 5, and the second overlapping region 6 of the intermediate inner electrode 5 extends beyond the extent of the overlapping region of the second terminal inner electrode 8 in the width direction.

As shown in fig. 8, in some embodiments, one of the two overlapping regions that overlap extends beyond the extent of the other overlapping region in both the width and length directions.

Referring to fig. 15, in some embodiments, the multi-layered inner electrode includes two inner electrodes, a first terminal inner electrode and a second terminal inner electrode connected to the terminal electrode, respectively, and an overlapping region of the first terminal inner electrode overlaps an overlapping region of the second terminal inner electrode.

Referring to fig. 16, in some embodiments, the multi-layered inner electrode includes five layers of inner electrodes, a first connected inner electrode and a second connected inner electrode respectively distributed on the first, third, and fifth layers connected to the end electrodes, and an intermediate inner electrode distributed on the second and fourth layers, the overlapping region of the first connected inner electrode overlaps the first overlapping region of the intermediate inner electrode, and the overlapping region of the second connected inner electrode overlaps the second overlapping region of the intermediate inner electrode; wherein the relationship of the width and the size of each overlapping area which are overlapped is alternately changed along the direction perpendicular to the layers.

According to the embodiments of the utility model, at least one inner electrode of the chip thermistor is provided with an overlapping area and a non-overlapping area, the width of the overlapping area is larger than that of the non-overlapping area, the overlapping area of the at least one inner electrode overlaps with the corresponding overlapping area of the inner electrode of the adjacent layer, and the corresponding overlapping area extends beyond the range of the overlapping area in the width direction. Therefore, the utility model not only can effectively reduce the influence of electrode deviation on the product resistance, thereby improving the high-precision qualification rate of the product, but also can save the use amount of internal slurry and reduce the production cost.

Specific embodiments of chip thermistors are described further below.

As shown in fig. 1 to 5, a chip thermistor of the present embodiment includes a ceramic body 1, two terminal electrodes 4 respectively provided at both ends of the ceramic body 1, and a multilayer internal electrode provided in the ceramic body 1, the multilayer internal electrode including a middle internal electrode 5 and connecting terminal internal electrodes 8, 9 connected to the terminal electrodes 4; the middle inner electrode 5 has two overlapping regions 2 and a non-overlapping region 3 connected between the two overlapping regions 2, and the width of the overlapping region 2 is greater than the width of the non-overlapping region 3; the overlapping region 2 of the intermediate inner electrode 5 overlaps the corresponding overlapping region of the terminal inner electrodes 8, 9, and the overlapping region of the intermediate inner electrode extends beyond the extent of the overlapping region of the terminal inner electrodes 8, 9 in the width direction. Wherein, the two overlapping areas 2 of the middle inner electrode 5 are rectangular and have the same width, the non-overlapping areas 3 and the non-overlapping areas of the connecting end inner electrodes 8 and 9 have the same width, and the width of the middle inner electrode 5 is 1/5 to 4/5 of the width of the ceramic body 1. Referring to fig. 4, the length of the electrode in this embodiment is L1, the length of the overlap region 2 is L3, and the length of the non-overlap region 3 (the length of the conductive connection region) is L2, where l1=2l3+l2 (theoretically 1/2 ceramic body length < L1 < ceramic body length, L2 > 0). The electrode width of the overlapping region 2 is W1, the electrode width of the non-overlapping region 3 (electrode width of the conductive connection region) is W2, wherein W2 is less than W1, preferably, the width of W1 and W2 ranges from 1/5 to 4/5 of the width of the ceramic body 1, and the width of W1 and W2 ranges from 100 mu m to 400 mu m by taking metric 1005 products as an example, but W2 is always less than W1.

According to the embodiment, the product resistance is controlled by controlling the overlapping area of the multi-layer inner electrode, the electrode width of the non-overlapping area for conducting connection of the middle inner electrode is reduced under the condition that the overlapping area of the middle inner electrode and the inner electrode of the adjacent layer is not influenced, the printing area of the middle inner electrode is effectively reduced, and the use amount of inner paste is reduced.

As shown in fig. 5, the chip thermistor of the embodiment is manufactured by adopting the processes of batching, casting, printing, laminating, wen Shuiya, cutting, chamfering, sintering, end electrode, electroplating, sorting and taping, and finally, the consistency and high-precision qualification rate of the product resistance value are improved under the condition that the product resistance value is not changed. The manufacturing method comprises the following steps:

step one, casting the thermosensitive sizing agent on a PET film to form a raw belt roll, and cutting to form a single raw belt piece.

And step two, forming a large electrode pattern and a small electrode pattern on the green tape by using the inner paste through a screen printing mode.

And thirdly, stacking the common green tape and the green tape with the electrodes into a BAR block by adopting the design of layer number, displacement and the like.

Step four, then step three, namely, the finished product is manufactured through the procedures of warm water pressure, cutting, chamfering, sintering, electrode terminating, electroplating, sorting and braiding.

Further, taking 1005 size structure as an example, the length and width and the print area of the electrode designs (see fig. 4) of the comparative example and the embodiment of the present utility model are shown in table 1, wherein the electrode structure of the comparative example is schematically shown in fig. 6, the electrode length is L1, the electrode width is W1, the electrode width of the conductive connection region is W2, and the electrode length of the conductive connection region is L2. Compared with the comparative example, the area of the intermediate inner electrode of the chip thermistor of this embodiment can be reduced by 35.06%.

TABLE 1

According to the embodiment, the electrode width of the non-overlapping area is reduced, the printing area can be reduced under the conditions that the electrode overlapping area is not affected and the high precision of the resistance value is ensured, and the using amount of inner paste is reduced, so that the manufacturing cost is reduced while the influence on the resistance value of a product is avoided.

As shown in fig. 7 to 17, another chip thermistor of the present embodiment is exemplified by a large and small square electrode design, comprising a ceramic body 1, two terminal electrodes 4 respectively provided at both ends of the ceramic body 1, and a plurality of layers of internal electrodes provided in the ceramic body 1, at least one of the internal electrodes having an overlap region 2 and a non-overlap region 3, and the width of the overlap region 2 being larger than the width of the non-overlap region 3 thereof. The overlap region 2 of the at least one inner electrode concentrically overlaps a corresponding overlap region of an inner electrode of an adjacent layer, and the corresponding overlap region extends beyond the extent of the overlap region 2 in the width direction. The multi-layered inner electrode comprises connected end inner electrodes 8, 9 connected to the end electrode 4 and an intermediate inner electrode 5, the intermediate inner electrode 5 having a first overlap region 7, a second overlap region 6 and a non-overlap region 3 connected between the first overlap region 7 and the second overlap region 6, the width of the first overlap region 7 being smaller than the width of the second overlap region 6. Referring to fig. 10, W1 is the width of the first overlap region 7 (small square electrode side length), W2 is the width of the non-overlap region 3 (conductive connection region electrode width), L2 is the length of the non-overlap region 3 (conductive connection region electrode length), W3 is the width of the second overlap region 6 (large square electrode side length), where W2 < W1 < W3, preferably, the widths of W1, W2, W3 are in the range of 1/5 to 4/5 of the ceramic body width, taking metric 1005 product as an example, the width ranges of 100 μm to 400 μm, where the difference between W1 and W3 is primarily dependent on the manufacturing process offset, and the center-to-center spacing of the square is equal to the electrode shift amount to ensure concentric overlapping of the electrodes.

According to the embodiment, the product resistance is controlled by controlling the overlapping area of the electrodes in the multiple layers, so that the influence of electrode deviation on the product resistance can be effectively reduced, the high-precision qualification rate of the product is improved, the use amount of inner paste can be saved, and the production cost is reduced.

In the present embodiment, the influence of the offset on the overlapping area can be reduced in the preparation process to reduce the influence of the offset on the product resistance, and the electrode offset schematic diagrams in the present embodiment are shown in fig. 12a to 12d, wherein fig. 12a and 12b are two non-offset schematic diagrams, and fig. 12c and 12d are two offset schematic diagrams.

Further, taking 1005 size square electrode design (as shown in fig. 10) as an example, table 2 is comparative data of the present example and comparative example, wherein the electrode structure of the comparative example is shown in fig. 6, the electrode length is L1, the electrode width is W1, the electrode width of the conductive connection region is W2 (theoretically 1/2 ceramic body length < L1 < ceramic body length, the width of W1 ranges from 1/5 to 4/5 of the ceramic body width of the product, taking metric 1005 product as an example, the width ranges of W1 and W2 are 100 μm to 400 μm), and the electrode length of the conductive connection region is L2. Compared with the comparative example, the electrode design of the chip thermistor of the embodiment can be reduced by 18.80% in cost, and the high-precision qualification rate of the final product can be improved from 54% to 60%.

TABLE 2

In some embodiments, a 1005-size circular electrode chip thermistor manufactured according to the above method is shown in fig. 13 and 14. Referring to fig. 13, R1 is the radius of the second overlap region (large circular electrode radius), W2 is the width of the non-overlap region 3 (conductive connection region electrode width), L2 is the length of the non-overlap region 3 (conductive connection region electrode length), and R2 is the radius of the first overlap region (small circular electrode radius). Table 3 shows comparative data and the like between the present example and the comparative example, in which the structure of the electrode in the comparative example is schematically shown in FIG. 6. Compared with the comparative example, the electrode design of the chip thermistor of the embodiment can be reduced by 19.97% in cost, and the high-precision qualification rate of the final product can be improved from 54% to 59%.

TABLE 3 Table 3

The chip thermistor provided by the embodiment of the utility model effectively reduces the influence of electrode deviation on the product resistance, thereby improving the consistency and high-precision qualification rate of the product resistance, reducing the use amount of internal paste and reducing the cost.

In addition, the foregoing embodiment has mainly been described by taking the overlapping of 3 layers of electrodes as an example, but the number of electrode layers in the chip thermistor of the present utility model is not limited to 3, and may have 2 layers, 5 layers, 7 layers, and so on. Fig. 15 is a schematic view illustrating a structure of a 2-layer electrode according to an embodiment of the present utility model. Fig. 16 is a schematic diagram of a structure using 5 layers of electrodes according to an embodiment of the present utility model. In addition, the shape of the overlapping region of the electrode is not limited, and fig. 17 is a schematic view of the structure of the electrode having an elliptical overlapping region according to the embodiment of the present utility model, in addition to the rectangular shape and the circular shape according to the foregoing embodiment of the present utility model.

The background section of the present utility model may contain background information about the problems or environments of the present utility model and is not necessarily descriptive of the prior art. Accordingly, inclusion in the background section is not an admission of prior art by the applicant.

The foregoing is a further detailed description of the utility model in connection with specific/preferred embodiments, and it is not intended that the utility model be limited to such description. It will be apparent to those skilled in the art that several alternatives or modifications can be made to the described embodiments without departing from the spirit of the utility model, and these alternatives or modifications should be considered to be within the scope of the utility model. In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "preferred embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Those skilled in the art may combine and combine the features of the different embodiments or examples described in this specification and of the different embodiments or examples without contradiction. Although embodiments of the present utility model and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope of the utility model as defined by the appended claims.

Claims

1. The chip thermistor is characterized by comprising a ceramic body, two end electrodes respectively arranged at two ends of the ceramic body and a plurality of layers of inner electrodes arranged in the ceramic body, wherein each layer of inner electrodes comprises a middle inner electrode and a connecting end inner electrode connected with each end electrode;

wherein the width direction exceeds a range of 5 μm to 100 μm.

2. A chip thermistor according to claim 1, characterized in that the overlapping area of the intermediate inner electrode is rectangular.

3. A chip thermistor according to any of claims 1 to 2, characterized in that the non-overlapping area of the intermediate inner electrode is the same width as the non-overlapping area of the terminal inner electrode.

4. A chip thermistor according to any of claims 1 to 2, characterized in that the two overlapping areas of the intermediate inner electrode are equally wide.

5. A chip thermistor according to any of claims 1 to 2, characterized in that the width of the intermediate inner electrode is 1/5 to 4/5 of the width of the ceramic body.

6. The chip thermistor is characterized by comprising a ceramic body, two end electrodes respectively arranged at two ends of the ceramic body and a plurality of layers of inner electrodes arranged in the ceramic body;

wherein the width direction exceeds a range of 5 μm to 100 μm.

7. A chip thermistor according to claim 6, wherein the overlap region of the inner electrodes overlaps concentrically with the corresponding overlap region of the inner electrodes of the adjacent layers.

8. A chip thermistor according to any of claims 6 to 7, wherein the multilayered inner electrode comprises three layers of inner electrodes, which are a first connecting inner electrode connected to the end electrode, a second connecting inner electrode, and an intermediate inner electrode, respectively, the intermediate inner electrode having a first overlapping region, a second overlapping region, and a non-overlapping region connected between the first overlapping region and the second overlapping region, the first overlapping region having a width smaller than that of the second overlapping region, the overlapping region of the first connecting inner electrode overlapping the first overlapping region of the intermediate inner electrode, the overlapping region of the second connecting inner electrode overlapping the second overlapping region of the intermediate inner electrode; the overlapping region of the first connecting end inner electrode extends beyond the range of the first overlapping region in the width direction; the second overlap region extends beyond the range of the overlap region of the second terminal inner electrode in the width direction.

9. A chip thermistor according to any of claims 6 to 7, wherein the multilayer internal electrode comprises two internal electrodes, a first terminal internal electrode and a second terminal internal electrode connected to the terminal electrode, respectively, and an overlapping region of the first terminal internal electrode overlaps an overlapping region of the second terminal internal electrode.

10. A chip thermistor according to any of claims 6 to 7, wherein the multilayered inner electrode comprises five layers of inner electrodes, which are respectively a first terminal inner electrode and a second terminal inner electrode distributed in first, third and fifth layers connected to the terminal electrodes, and an intermediate inner electrode distributed in second and fourth layers, an overlapping region of the first terminal inner electrode overlapping a first overlapping region of the intermediate inner electrode, and an overlapping region of the second terminal inner electrode overlapping a second overlapping region of the intermediate inner electrode; wherein the relationship of the width and the size of each overlapping area which are overlapped is alternately changed along the direction perpendicular to the layers.