CN220543595U - Memory chip testing device and testing system - Google Patents
Memory chip testing device and testing system Download PDFInfo
- Publication number
- CN220543595U CN220543595U CN202321488715.7U CN202321488715U CN220543595U CN 220543595 U CN220543595 U CN 220543595U CN 202321488715 U CN202321488715 U CN 202321488715U CN 220543595 U CN220543595 U CN 220543595U
- Authority
- CN
- China
- Prior art keywords
- control module
- memory chip
- board
- main board
- power control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 105
- 230000002159 abnormal effect Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 4
- 239000011324 bead Substances 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 5
- 230000002950 deficient Effects 0.000 description 5
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Abstract
The application discloses a memory chip testing device and a testing system, which are used for testing a memory chip, wherein the memory chip testing device comprises a main board, a control module and at least one auxiliary board, wherein the auxiliary board is arranged on the main board, the auxiliary board is detachably connected with the main board, the control module is connected with the auxiliary board through the main board, a chip mounting seat is further arranged on the auxiliary board, and the memory chip is arranged in the chip mounting seat; the memory chip testing device further comprises circuit protection modules, the circuit protection modules correspond to the auxiliary boards one by one, the circuit protection modules are connected to the input ends of the chip mounting seats, and in the testing process, the control module detects that the voltage of the memory chip is abnormal, and then controls the circuit protection modules to disconnect the connection between the main board and the chip mounting seats. Through the design, the safety of the storage chip testing device is protected, the reliability and the applicability are improved, and the testing cost is reduced.
Description
Technical Field
The present disclosure relates to the field of testing memory chips, and in particular, to a testing device and a testing system for a memory chip.
Background
Because the memory chip needs to be subjected to high-temperature aging sorting grade, a large amount of high-temperature stable tests are required, and card opening tests are required before and after the tests. For testing of memory chips, the prior art uses a single test board, manually installs the memory chips, loads RDT (Reliability Demonstration Testing) programs, and then places the memory chips into a high-temperature furnace for testing, and simulates erasing under high temperature conditions to accelerate faults of weak NAND flash memory blocks so as to improve reliability and durability to the greatest extent.
The existing memory chip has defective products, and the problem that the whole circuit board cannot be normally used due to short circuit of the circuit board of the testing device during testing is caused, so that the cost of testing is possibly increased.
Disclosure of Invention
The purpose of the application is to provide a memory chip testing device and a testing system, which can improve the reliability and applicability of the chip testing device and reduce the testing cost.
The application discloses a memory chip testing device for testing a memory chip, the memory chip testing device comprises a main board, a control module and at least one auxiliary board, wherein the auxiliary board is arranged on the main board, the auxiliary board is detachably connected with the main board, the control module is connected with the auxiliary board through the main board, a chip mounting seat is further arranged on the auxiliary board, and the memory chip is arranged in the chip mounting seat;
the memory chip testing device further comprises circuit protection modules, the circuit protection modules correspond to the auxiliary boards one by one, the circuit protection modules are connected to the input ends of the chip mounting seats, and in the testing process, the control module detects that the voltage of the memory chip is abnormal, and then controls the circuit protection modules to disconnect the connection between the main board and the chip mounting seats.
Optionally, a first power control module is arranged on the main board, a second power control module is arranged on the auxiliary board, the first power control module is connected with the second power control module, the control module is connected with the first power control module, and the circuit protection module is arranged on the main board and is arranged at the output end of the first power control module.
Optionally, the storage chip testing device further includes at least one LED light bead, where the LED light bead is connected between the first power control module and the second power control module, and the LED light bead is disposed on the main board and corresponds to the auxiliary board one to one.
Optionally, the memory chip testing device further includes a display module, and the display module is connected with the control module.
Optionally, the circuit protection module includes a first switch, and the first switch is disposed at an output end of the first power control module and an input end of the second power control module.
Optionally, the memory chip testing device further includes a control module circuit board, the control module is disposed on the control module circuit board, a first connection port is further disposed on the control module circuit board, a second connection port is disposed on the main board, and the first connection port is connected with the second connection port through a connection line.
Optionally, the memory chip testing device includes a plurality of the sub-boards, and the plurality of sub-boards correspond to different types of memory chips.
Optionally, at least one male connector is provided on the main board, the male connector is connected to the output end of the first power control module, a female connector is provided on the auxiliary board, the female connector is connected to the input end of the second power control module, and the male connector is detachably connected to the female connector.
Optionally, the orthographic projection of the auxiliary board on the main board covers the male connector corresponding to the auxiliary board.
The application also discloses a test system, the test system includes a host end and a memory chip test device, the host end is connected with the memory chip test device.
Compared with the scheme that the memory chip testing device only has one circuit board, the control module detects the voltage value of the memory chip in the testing state, and when abnormal voltage appears in the voltage, the circuit protection module cuts off the power supply to the memory chip, so that the safety of the memory chip testing device is protected in time, and the reliability of the memory chip testing device is improved; the chip mounting seat in the storage chip testing device is arranged on the auxiliary board, the auxiliary board is detachably connected with the main board, the storage chip is in short circuit during testing, the main board is not burnt out even if the auxiliary board is damaged, and the test can be directly continued by replacing the auxiliary board; and because the main board and the auxiliary board are detachably connected, only the corresponding auxiliary board is required to be replaced when different chips are tested, and the applicability of the product is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive faculty for a person skilled in the art. In the drawings:
FIG. 1 is a schematic diagram of a test system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a memory chip testing apparatus according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another memory chip testing apparatus according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a circuit protection module according to an embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a memory chip testing apparatus according to an embodiment of the present application.
10, testing a system; 20. a host end; 30. a memory chip testing device; 40. a memory chip; 100. a control module; 110. a control module circuit board; 120. a first connection port; 200. a main board; 210. a first power control module; 220. LED lamp beads; 230. a second connection port; 240. a male interface; 300 subplates; 310. a second power control module; 320. a chip mounting base; 330. a female interface; 400. a display module; 500. a circuit protection module; 510. a first switch.
Detailed Description
It should be understood that the terminology, specific structural and functional details disclosed herein are merely representative for purposes of describing particular embodiments, but that the application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or implicitly indicating the number of technical features indicated. Thus, unless otherwise indicated, features defining "first", "second" may include one or more such features either explicitly or implicitly; the meaning of "plurality" is two or more. The terms "comprises," "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or groups thereof may be present or added.
In addition, terms of the azimuth or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., are described based on the azimuth or relative positional relationship shown in the drawings, are merely for convenience of description of the present application, and do not indicate that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application.
Furthermore, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with each other. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
The present application is described in detail below with reference to the attached drawings and alternative embodiments.
Fig. 1 is a schematic diagram of a test system according to an embodiment of the present application, and as shown in fig. 1, the present application discloses a test system 10, where the test system 10 includes a host end 20 and a memory chip test device 30, and the host end 20 is connected to the memory chip test device 30.
The host 20 is a device such as a computer used for testing, and is mainly used for erasing data to the memory chip 40 in the memory chip testing device 30.
The application also discloses a memory chip testing device 30, which can be used in the testing system 10, and for the memory chip testing device 30, the application provides the following design.
Fig. 2 is a schematic diagram of a memory chip testing apparatus according to an embodiment of the present application, and as shown in fig. 2, the present application discloses a memory chip testing apparatus 30 for testing a memory chip 40, where the memory chip testing apparatus 30 includes a main board 200, a control module 100, a chip mount 320, and at least one sub-board 300. The auxiliary board 300 is disposed on the main board 200, the auxiliary board 300 is detachably connected with the main board 200, the control module 100 is connected with the auxiliary board 300 through the main board 200, the chip mount 320 is disposed on the auxiliary board 300, and the memory chip 40 is disposed in the chip mount 320.
The memory chip testing device 30 further includes a circuit protection module 500, the circuit protection module 500 corresponds to the sub-board 300 one by one, the circuit protection module 500 is connected to the input end of the chip mount 320, and in the testing process, the control module 100 detects that the voltage of the memory chip 40 is abnormal, and then controls the circuit protection module 500 to disconnect the connection between the motherboard 200 and the chip mount 320. Wherein the control module 100 is an MCU control module 100.
The voltage value of the memory chip 40 in the test state is detected by the control module 100, when abnormal voltage appears in the voltage, the power supply to the memory chip 40 is disconnected by the circuit protection module 500, so that the safety of the memory chip test device 30 is timely protected, and the reliability of the chip test device is improved; and the chip mount pad 320 in the memory chip testing device 30 is arranged on the auxiliary board 300, the auxiliary board 300 is detachably connected with the main board 200, firstly, the memory chip 40 is short-circuited during testing, even if the auxiliary board 300 is damaged, the main board 200 can not be burnt out, and the test can be directly continued by replacing the auxiliary board 300, secondly, because the main board 200 and the auxiliary board 300 are detachably connected, only the corresponding auxiliary board 300 is required to be replaced during testing different chips, and the applicability of products is improved.
The test voltage of the memory chip 40 is 1.8V, and when the control module 100 detects that the voltage of the memory chip 40 exceeds the voltage by ±5%, the control module 500 is controlled to be turned off, and the control module 100 further has the functions of automatically identifying the type of the memory chip 40 and automatically configuring GPIOs for the memory chip 40.
And a first power control module 210 is disposed on the main board 200, a second power control module 310 is disposed on the sub-board 300, the first power control module 210 is connected with the second power control module 310, the control module 100 is connected with the first power control module 210, and the circuit protection module 500 is disposed on the main board 200 and is disposed at an output end of the first power control module 210.
The control module 100 detects the output voltage of the first power control module 210, that is, the voltage value of the memory chip 40, when the memory chip 40 is shorted, the output voltage of the first power control module 210 will be suddenly changed, and when the suddenly changed voltage exceeds the threshold range, the control module 100 controls the circuit protection module 500 to be disconnected, and the first power module 210 and the memory chip 40 are electrically connected, that is, the first power module 210 no longer supplies power to the memory chip 40.
Since one sub-board 300 needs to correspond to one circuit protection module 500, the circuit protection module 500 is disposed on the motherboard 200, so that the circuit protection module 500 does not need to be disposed on each sub-board 300, and the cost of the sub-board 300 is reduced.
Of course, the circuit protection module 500 may be disposed on the sub-board 300, and the circuit protection module 500 is disposed at the output end of the second power control module 310, so as to protect the sub-board 300 from being damaged due to short circuit of the defective memory chip 40.
To further improve the applicability of the product, a plurality of sub-boards 300 of different types may be simultaneously disposed on the main board 200, specifically: the memory chip testing apparatus 30 includes a plurality of the sub-boards 300, and the plurality of the sub-boards 300 correspond to different types of memory chips 40. A variety of different memory chips 40 may be tested.
The control module 100 may be directly disposed on the motherboard 200, or may be connected to the motherboard 200 by an external connection, which is illustrated by using the control module 100 being connected to the motherboard 200 by an external connection as an example:
the memory chip testing device 30 further includes a control module circuit board 110, the control module 100 is disposed on the control module circuit board 110, a first connection port 120 is further disposed on the control module circuit board 110, a second connection port 230 is disposed on the motherboard 200, and the first connection port 120 and the second connection port 230 are connected by a connection line.
Corresponding to the modularized design, even if the main board 200 is damaged, only the main board 200 needs to be replaced, and when the high-low temperature test is performed, the control module 100 and the main board 200 are connected through wires, so that the control module 100 can be arranged outside the high-low temperature box, and the influence of temperature change in the high-low temperature box on the control module 100 is avoided.
Of course, the control module 100 may also be connected to the main board 200 through a wireless connection, specifically, only a wireless transmission module needs to be set on the main board 200 and is connected to the control module 100 in a pairing manner, where the wireless transmission manner includes bluetooth transmission and WIFI transmission.
Further, in order to timely understand that the memory chip 40 is a defective product, the test efficiency is improved, and the application further sets up the LED lamp bead 220 on the main board 200 for prompting, and is specific:
the memory chip testing device 30 further includes at least one LED light bead 220, where the LED light bead 220 is connected between the first power control module 210 and the second power control module, and the LED light bead 220 is disposed on the main board 200 and corresponds to the sub-board 300 one by one.
When the circuit protection module 500 cuts off the power supply to the auxiliary board 300, the control module 100 controls the corresponding LED lamp beads 220 of the auxiliary board 300 to be turned on, and the LED lamp beads 220 are directly arranged on one side of the auxiliary board 300, so that the worker can conveniently identify the auxiliary board through the LED lamp beads 220, and the worker can intuitively obtain which auxiliary board 300 has the defective memory chip 40.
For the mode of setting up the LED lamp pearl 220 at the output of circuit protection module 500, go out through the LED lamp pearl 220 that observes the subplate 300 correspondence, judge which storage chip 40 on the subplate 300 is the scheme of defective products, the LED lamp pearl 220 of the mode of this application need not keep the state of always bright, and is more energy-conserving.
Of course, it is also possible to directly display the position of the sub-board 300, which is disconnected from power, on the display module 400 by adding a display module 400, specifically:
fig. 3 is a schematic diagram of another memory chip testing device according to an embodiment of the present application, as shown in fig. 3, the memory chip testing device 30 further includes a display module 400, where the display module 400 is connected to the control module 100.
Since the GPIOs of each chip mount 320 are different, the control module 100 can determine the position of the sub-board 300 corresponding to the chip mount 320 that is powered off by identifying the GPIOs of the chip mount 320, and display the position in the display module 400, where the display module 400 is a display screen.
As shown in fig. 4, the circuit protection module 500 includes a first switch 510, and the first switch 510 is disposed at an output terminal of the first power control module 210 and an input terminal of the second power control module 310. The control module 100 tests the voltage value of the memory chip 40, and when an abnormal voltage occurs, the first power control module 210 cuts off the power supply to the second power control module 310 by turning off the first switch 510.
Fig. 5 is a schematic cross-sectional view of a memory chip testing apparatus according to an embodiment of the present application, as shown in fig. 5, the main board 200 and the sub-board 300 are detachably connected together by plugging, specifically:
the main board 200 is provided with at least one male connector 240, the male connector 240 is connected to an output end of the first power control module 210, the auxiliary board 300 is provided with a female connector 330, the female connector 330 is connected to an input end of the second power control module 310, and the male connector 240 is detachably connected to the female connector 330.
For the mode through the connecting wire is connected, the utility model discloses a connect through public first interface 240 and female first interface 330, first transmission distance has been reduced, has improved signal transmission's reliability, and the connected mode of pegging graft can fix subplate 300 on mainboard 200 moreover, avoids subplate 300 not hard up droing.
And, the front projection of the auxiliary board 300 on the main board 200 covers the male interface 240 corresponding to the auxiliary board 300. Thereby saving the occupied area of the auxiliary board 300 on the main board 200, improving the number of the auxiliary boards 300 arranged on the main board 200 and improving the detection efficiency.
It should be noted that the inventive concept of the present application may form a very large number of embodiments, but the application documents are limited in size and cannot be listed one by one, so that the above-described embodiments or technical features may be arbitrarily combined to form new embodiments without conflict, and the original technical effects will be enhanced after the embodiments or technical features are combined
The foregoing is a further detailed description of the present application in connection with specific alternative embodiments, and it is not intended that the practice of the present application be limited to such descriptions. It should be understood that those skilled in the art to which the present application pertains may make several simple deductions or substitutions without departing from the spirit of the present application, and all such deductions or substitutions should be considered to be within the scope of the present application.
Claims (10)
1. The storage chip testing device is used for testing a storage chip and is characterized by comprising a main board, a control module and at least one auxiliary board, wherein the auxiliary board is arranged on the main board, the auxiliary board is detachably connected with the main board, the control module is connected with the auxiliary board through the main board, a chip mounting seat is further arranged on the auxiliary board, and the storage chip is arranged in the chip mounting seat;
the memory chip testing device further comprises circuit protection modules, the circuit protection modules correspond to the auxiliary boards one by one, the circuit protection modules are connected to the input ends of the chip mounting seats, and in the testing process, the control module detects that the voltage of the memory chip is abnormal, and then controls the circuit protection modules to disconnect the connection between the main board and the chip mounting seats.
2. The memory chip testing device according to claim 1, wherein a first power control module is disposed on the main board, a second power control module is disposed on the sub-board, the first power control module is connected with the second power control module, the control module is connected with the first power control module, and the circuit protection module is disposed on the main board and is disposed at an output end of the first power control module.
3. The test device of claim 2, wherein the memory chip test device further comprises at least one LED light bead connected between the first power control module and the second power control module, and the LED light beads are disposed on the main board and in one-to-one correspondence with the sub-boards.
4. The memory chip testing apparatus of claim 2, further comprising a display module coupled to the control module.
5. The memory chip testing device of claim 2, wherein the circuit protection module comprises a first switch disposed at an output of the first power control module and an input of the second power control module.
6. The memory chip testing device according to claim 1, further comprising a control module circuit board, wherein the control module is disposed on the control module circuit board, a first connection port is further disposed on the control module circuit board, a second connection port is disposed on the main board, and the first connection port and the second connection port are connected through a connection line.
7. The memory chip testing apparatus of claim 1, wherein the memory chip testing apparatus comprises a plurality of the sub-boards, and the plurality of sub-boards correspond to different types of memory chips.
8. The memory chip testing device according to claim 2, wherein at least one male connector is provided on the main board, the male connector is connected to the output end of the first power control module, a female connector is provided on the auxiliary board, the female connector is connected to the input end of the second power control module, and the male connector is detachably connected to the female connector.
9. The memory chip testing device of claim 8, wherein an orthographic projection of the sub-board on the main board covers the male interface corresponding to the sub-board.
10. A test system comprising a host side and a memory chip test device according to any one of claims 1-9, wherein the host side is connected to the memory chip test device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321488715.7U CN220543595U (en) | 2023-06-12 | 2023-06-12 | Memory chip testing device and testing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321488715.7U CN220543595U (en) | 2023-06-12 | 2023-06-12 | Memory chip testing device and testing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220543595U true CN220543595U (en) | 2024-02-27 |
Family
ID=89968940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321488715.7U Active CN220543595U (en) | 2023-06-12 | 2023-06-12 | Memory chip testing device and testing system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220543595U (en) |
-
2023
- 2023-06-12 CN CN202321488715.7U patent/CN220543595U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101751316B (en) | Universal serial bus (USB) interface module testing device | |
| US8832344B2 (en) | Baseboard, extension module, and structure for connecting baseboard and extension module | |
| US8395393B2 (en) | Cable test method | |
| CN102479137A (en) | Detection device and detection method for detecting universal serial bus port of test equipment | |
| CN101769986B (en) | Test device and test method thereof | |
| US20100185880A1 (en) | Test apparatus | |
| CN220543595U (en) | Memory chip testing device and testing system | |
| CN106124904B (en) | A kind of electric connector electric property detecting system | |
| US10840624B2 (en) | NGSFF and M.2 differentiation and mutual protection circuit | |
| US20230305937A1 (en) | Test apparatus for usb-pd device | |
| CN113985321B (en) | Cable connection performance testing device and method with intelligent self-learning capability | |
| CN105717438A (en) | Current signal testing device and method | |
| CN213482386U (en) | USB adapter plate test circuit and test fixture | |
| US11675021B2 (en) | Test apparatus for USB-PD device | |
| CN209764982U (en) | connector plugging detection device and hardware-in-the-loop test equipment | |
| CN211627787U (en) | FPC circuit open/short circuit detection circuit, device and system | |
| CN108459232A (en) | touch screen test device and method | |
| CN210745405U (en) | Port detector | |
| CN220543599U (en) | Test circuit board and test device | |
| KR101091115B1 (en) | A defect-inspecting apparatus of usb | |
| CN218331852U (en) | Fool-proof device for integrated circuit test | |
| CN110568341A (en) | System for automatically testing welding state of IO (input/output) interface function of PCBA (printed circuit board assembly) mainboard | |
| CN220820205U (en) | Detection system for preventing FPC resistance cold joint | |
| CN218298400U (en) | Charging test system | |
| CN210427717U (en) | Small-size integral type circuit board automatic test box |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 518000 floor 1, floor 2 and floor 3, No. 7, Xinfa East Road, Xiangshan community, Xinqiao street, Bao'an District, Shenzhen, Guangdong Province; No.5 1st, 2nd and 3rd floors Patentee after: Shenzhen Shi Creative Electronics Co.,Ltd. Country or region after: China Address before: Shenzhen Shishi Creative Electronics Co., Ltd., No. 5, Xinfa East Road, Xinqiao Street, Bao'an District, Shenzhen City, Guangdong Province, 518000 Patentee before: SHENZHEN SHICHUANGYI ELECTRONIC CO.,LTD. Country or region before: China |
|
| CP03 | Change of name, title or address |