CN220526924U - SiC MOSFET channel type device - Google Patents
SiC MOSFET channel type device Download PDFInfo
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- CN220526924U CN220526924U CN202322191397.4U CN202322191397U CN220526924U CN 220526924 U CN220526924 U CN 220526924U CN 202322191397 U CN202322191397 U CN 202322191397U CN 220526924 U CN220526924 U CN 220526924U
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- 239000011159 matrix material Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims description 105
- 238000005468 ion implantation Methods 0.000 claims description 67
- 239000000758 substrate Substances 0.000 claims description 57
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
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- 230000015556 catabolic process Effects 0.000 abstract description 7
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- 238000000034 method Methods 0.000 description 23
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- 238000000151 deposition Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
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- 230000005669 field effect Effects 0.000 description 2
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- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
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- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
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- 238000005224 laser annealing Methods 0.000 description 1
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- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The utility model discloses a channel type device of a SiC MOSFET, which belongs to the technical field of semiconductors and comprises a plurality of MOSFET tubes connected in parallel, wherein the channel area of the SiC MOSFET device is of a three-dimensional vertical structure. According to the utility model, the channel region of the SiC MOSFET device is redesigned into a vertical structure from the arrangement structure of the existing horizontal plane, and the region of the JFET is etched by the channel, so that the resistance contribution of the JFET is reduced, the on-resistance of the whole device is reduced, and the power consumption of the device is also reduced. Meanwhile, the grid electrode of the MOSFET tube is a rectangular matrix array, the area of the grid electrode of the MOSFET device is reduced, the controllable channel area of the grid electrode switch of the device is increased, a plurality of MOSFETs are connected in parallel, the breakdown voltage of the equivalent transistor after the whole parallel connection is further improved, the equivalent transistor is different from a common plane channel SiC MOSFET, the power density of the unit area of the vertical channel SiC MOSFET device is higher, and the equivalent transistor is suitable for being used for being higher than a 1500V high-voltage device switch.
Description
Technical Field
The utility model relates to the technical field of semiconductors, in particular to a channel type device of a SiC MOSFET.
Background
The known SiC MOSFET in the market at present is relatively mature in technology, and the chip breakdown voltage can reach 950V to 1500V. The breakdown voltage of the whole high-voltage direct-current converter module needs to be greatly increased to more than 1800V, and the breakdown voltage of the whole module needs to be improved and increased from the design of the most basic unit transistor device in the SiC MOSFET chip.
The structural design of the conventional SiC MOSFET device is shown in fig. 1, and the conventional SiC MOSFET device comprises a substrate, wherein a drain metal layer 9 is arranged below the substrate, a drift region 11 is arranged above the substrate, protection rings 15 are arranged at two ends of the drift region 11, a plurality of P+ type regions 12 are arranged above the drift region 11, an N type ion implantation layer 3 is arranged in the P+ type regions 12, and a P type ion implantation layer 4 is arranged between the N type ion implantation layers 3; a gate 13 is arranged above the p+ type region 12, the gate 13 is arranged on two adjacent N-type ion implantation layers 3 in a building manner, a first source metal layer 61 is arranged on the gate 13, the gate 13 is contacted with the first source metal layer 61 through a gate side wall layer 5, and the first source metal layer 61 is connected with the source metal contact layer 7 through a source contact 14. The grid electrodes of the SiC MOSFET devices are arranged in a plane square array, the grid electrode arrays of the MOSFET devices are connected in parallel, the areas of the source electrodes of the MOSFET devices are connected with the two sides of the grid electrodes of the devices in a bridging mode through source electrode contacts, and then the grid electrodes are connected and connected at the same time, and the drain electrodes of the MOSFET devices are arranged at the bottom of the devices. When the structural SiC MOSFET device is electrified and an operating voltage is applied, the surface of the P+ type region contacted with the grid electrode 13 is a channel region 8, namely the channel region is in a horizontal plane arrangement structure. The area of the planar device, which is designed in the middle of the areas of the channels at two sides, is a JFET (Junction Field Effect Transistor) junction field effect transistor, and the resistance of the JFET can increase the on-resistance of the device under the condition that the device is conducted.
Disclosure of Invention
The utility model aims to overcome the problems in the prior art and provides a channel type device of a SiC MOSFET.
The aim of the utility model is realized by the following technical scheme: the channel type device of the SiC MOSFET comprises a substrate, wherein a drain electrode metal layer is arranged on the bottom surface of the substrate, a P+ type region and a protection ring are formed in the substrate, the P+ type region is arranged in the middle region, and the protection ring is arranged at the periphery; the P+ type region is sequentially provided with a P type ion implantation layer and an N type ion implantation layer which are positioned in the substrate;
the substrate is also provided with a grid penetrating through the P-type ion implantation layer and extending to the bottom of the N-type ion implantation layer, a grid oxide layer is arranged between the grid and the P-type ion implantation layer and between the grid and the N-type ion implantation layer, the surface of the substrate above the grid is provided with a first grid top metal, the surface of the substrate is also provided with a second grid top metal, and the side surfaces of the first grid top metal and the second grid top metal are provided with grid side wall layers; the first grid electrode top layer metal is provided with a second source electrode metal layer, the surface of the substrate is also provided with a third source electrode metal layer, the second source electrode metal layer penetrates through the P-type ion implantation layer and the N-type ion implantation layer at intervals and extends to the P+ type region, and the grid electrode is arranged at intervals in a crossing manner with the second source electrode metal layer region penetrating through the P-type ion implantation layer and the N-type ion implantation layer and extending to the P+ type region;
a dielectric layer is arranged on the surface of the substrate, the second source electrode metal layer, the grid electrode side wall layer and the third source electrode metal layer; a grid metal contact layer is arranged on the top metal of the second grid, a source metal contact layer is arranged on the third source metal layer, and a top protection layer is arranged on the grid metal contact layer and the source metal contact layer; when the device is loaded with working voltage, a channel region with a vertical structure is formed by a gate oxide layer between the gate and the P-type ion implantation layer.
In one example, the gate is a rectangular matrix array.
In one example, the guard rings are symmetrically distributed.
In one example, the guard ring spacing gradually expands toward the outer ring.
In one example, the gate sidewall layer is a silicon dioxide or silicon nitride film.
In one example, the dielectric layer is a silicon dioxide or silicon nitride film.
In one example, an alignment layer is disposed between the substrate surface and the dielectric layer.
It should be further noted that the technical features corresponding to the examples above may be combined with each other or replaced to form a new technical solution.
Compared with the prior art, the utility model has the beneficial effects that:
1. in an example, the channel region of the SiC MOSFET device is redesigned to be of a vertical structure from the existing horizontal arrangement structure, and the region of the JFET is etched away by the channel, so that the resistance contribution of the JFET is reduced, the on-resistance of the whole device is reduced, and the device power consumption is reduced. Meanwhile, the grid electrode of the MOSFET tube is a rectangular matrix array, the area of the grid electrode of the MOSFET device is reduced, the controllable channel area of the grid electrode switch of the device is increased, a plurality of MOSFETs are connected in parallel, the breakdown voltage of the equivalent transistor after the whole parallel connection is further improved, the equivalent transistor is different from a common plane channel SiC MOSFET, the power density of the unit area of the vertical channel SiC MOSFET device is higher, and the equivalent transistor is suitable for being used for being higher than a 1500V high-voltage device switch.
2. In an example, the design of the protection ring changes the traditional equidistant design, the concentric circle interval increases the design structure progressively, lengthen the propagation path of the leakage current, reduce the horizontal leakage risk of the diode device greatly.
Drawings
The following detailed description of the present utility model is further detailed in conjunction with the accompanying drawings, which are provided to provide a further understanding of the present application, and in which like reference numerals are used to designate like or similar parts throughout the several views, and in which the illustrative examples and descriptions thereof are used to explain the present application and are not meant to be unduly limiting.
Fig. 1 is a schematic cross-sectional structure of a conventional planar SiC MOSFET device;
fig. 2 is a top view of a channel SiC MOSFET device in an example of the utility model;
fig. 3 is a cross-sectional view of a channel SiC MOSFET device in an example of the utility model;
fig. 4 is a cross-sectional view of a channel type SiC MOSFET device in a preferred example of the present utility model;
fig. 5 is a schematic view of a device structure obtained in step S1 of the method for manufacturing a SiC MOSFET device;
fig. 6 is a schematic diagram of a device structure obtained in step S2 of the method for manufacturing a SiC MOSFET device;
fig. 7 is a schematic view of a device structure obtained in step S3 of the method for manufacturing a SiC MOSFET device;
fig. 8 is a schematic diagram of a device structure obtained in step S4 of the method for manufacturing a SiC MOSFET device;
fig. 9 is a schematic view of a device structure obtained in step S5 of the method for manufacturing a SiC MOSFET device;
fig. 10 is a schematic view of a device structure obtained in step S6 of the method for manufacturing a SiC MOSFET device;
fig. 11 is a schematic view of a device structure obtained in step S7 of the SiC MOSFET device manufacturing method;
fig. 12 is a schematic view of a device structure obtained in step S8 of the method for manufacturing a SiC MOSFET device;
fig. 13 is a schematic view of a device structure obtained in step S9 of the SiC MOSFET device manufacturing method;
fig. 14 is a schematic view of a device structure obtained in step S10 of the method for manufacturing a SiC MOSFET device;
fig. 15 is a schematic view of a device structure obtained in step S11 of the method for manufacturing a SiC MOSFET device;
fig. 16 is a schematic view of a device structure obtained in step S12 of the SiC MOSFET device manufacturing method;
fig. 17 is a schematic view of a device structure obtained in step S13 of the SiC MOSFET device manufacturing method;
fig. 18 is a top view of the device structure obtained in step S3 of the SiC MOSFET device manufacturing method;
fig. 19 is a top view of a device structure obtained in step S4 of the SiC MOSFET device manufacturing method;
fig. 20 is a top view of a device structure obtained in step S5 of the SiC MOSFET device manufacturing method;
fig. 21 is a top view of a device structure obtained in step S6 of the SiC MOSFET device manufacturing method;
fig. 22 is a top view of the device structure obtained in step S7 of the SiC MOSFET device manufacturing method;
fig. 23 is a top view of the device structure obtained in step S8 of the SiC MOSFET device manufacturing method;
fig. 24 is a top view of the device structure obtained in step S10 of the method for manufacturing a SiC MOSFET device.
In the figure: the drift region 11, the p+ type region 12, the gate 13, the source contact 14, the guard ring 15, the gate oxide 16, the alignment layer 20, the source metal opening 22, the first gate top metal 23, the gate metal contact layer 24, the top protection layer 25, the second gate top metal 26, the dielectric layer 27, the N-type ion implantation layer 3, the P-type ion implantation layer 4, the gate sidewall layer 5, the first source metal layer 61, the second source metal layer 62, the third source metal layer 63, the source metal contact layer 7, the channel region 8, the drain metal layer 9.
Detailed Description
The following description of the embodiments of the present utility model will be made apparent and fully understood from the accompanying drawings, in which some, but not all embodiments of the utility model are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
In the description of the present utility model, it should be noted that directions or positional relationships indicated as being "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are directions or positional relationships described based on the drawings are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Further, ordinal words (e.g., "first and second," "first through fourth," etc.) are used to distinguish between objects, and are not limited to this order, but rather are not to be construed to indicate or imply relative importance.
In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present utility model described below may be combined with each other as long as they do not collide with each other.
In one example, a SiC MOSFET channel device includes a substrate, a drift region 11 (epitaxial region) above the substrate, preferably an N-drift region 11, a P-type annular region above the drift region 11, and a square array of the periphery and the interior of the P-type annular region device; an N-type ion shallow layer injection layer and a P-type middle layer ion injection layer which are horizontally arranged in a square P+ type region 12 in the device; square P + type region 12 within the device is the source region; the "well" shape in fig. 2 is the gate region.
Specifically, as shown in fig. 1-2, the device comprises an n+ type substrate, preferably a SiC substrate, and an ohmic metal layer is disposed on the bottom surface of the substrate, namely: a drain metal layer 9. The substrate region is formed with a p+ -type region 12 and a guard ring 15. The p+ region 12 is disposed in the middle region, extends from the surface of the substrate to the lower portion of the substrate, and has a height equal to that of the guard ring 15, and has a connection hole for providing the source contact 14; the protection rings 15 are arranged on the periphery, and the protection rings 15 at the two ends can be distributed at equal intervals; the p+ type region 12 is sequentially provided with a P type ion implantation layer 4 and an N type ion implantation layer 3 which are positioned in the substrate, wherein the P type ion implantation layer 4 is p+ type, and the N type ion implantation layer 3 is n+ type.
Further, a plurality of grid electrodes 13 penetrating through the P-type ion implantation layer 4 and extending to the bottom of the N-type ion implantation layer 3 are further arranged in the substrate to form a rectangular matrix array; a gate oxide layer 16 is arranged between the gate 13 and the P-type ion implantation layer 4 and between the gate 13 and the N-type ion implantation layer 3, a first gate top metal 23 is arranged on the surface of the substrate above the gate 13, a second gate top metal 26 is also arranged on the surface of the substrate, a gate side wall layer 5 is arranged on the surface of the first gate 13 top layer and on the side surface of the second gate top metal 26, and a source region is connected with the source contact 14 through the side wall of the gate 13. Preferably, the gate sidewall layer 5 is a silicon dioxide or silicon nitride film, preferably a silicon nitride film. Further, the first gate top metal 23 is provided with a second source metal layer 62, the substrate surface is further provided with a third source metal layer 63, the second source metal layer 62 penetrates through the P-type ion implantation layer 4 and the N-type ion implantation layer 3 at intervals and extends to the p+ type region 12, and the gate 13 is arranged at intervals intersecting with the second source metal layer 62 penetrating through the P-type ion implantation layer 4 and the N-type ion implantation layer 3 and extending to the p+ type region 12, namely: the second source metal layer 62 extending to the p+ region 12 through the P-type ion implantation layer 4 and the N-type ion implantation layer 3 is separated from the adjacent gate 13 by the P-type ion implantation layer 4 and the N-type ion implantation layer 3.
Further, the dielectric layer 27, preferably a silicon nitride film, is disposed on the substrate surface, the third source metal layer 63, the gate sidewall layer 5, and the third source metal layer 63; the second gate top metal 26 is provided with a gate metal contact layer 24, the third source metal layer 63 is provided with a source metal contact layer 7, and the gate metal contact layer 24 and the source metal contact layer 7 are provided with a top protection layer 25. Further, the N-type ion implantation layer 3 in the contact region of the gate 13 is n+ type, and the P-type ion implantation layer 4 in the contact region of the source 14 is p+ type.
When the device is loaded with working voltage, a channel region 8 with a three-dimensional vertical structure is formed by a gate oxide layer 16 between a gate 13 and a P-type ion implantation layer 4, and the region of the JFET is etched by the channel, so that the resistance contribution of the JFET is reduced, the on-resistance of the whole device is reduced, and the power consumption of the device is reduced. The device comprises a plurality of MOSFET tubes connected in parallel, a channel region 8 of the SiC MOSFET device is designed to be a vertical structure from the arrangement structure of the existing horizontal plane, a grid electrode 13 of the MOSFET tube is in a square matrix column shape, the area of the grid electrode 13 of the MOSFET device is reduced, the controllable channel area of the grid electrode 13 of the device is increased, the plurality of MOSFETs are connected in parallel again, the breakdown voltage of an equivalent transistor after the whole parallel connection is further improved, the device is different from a common plane-type channel SiC MOSFET, the power density of the unit area of the vertical channel SiC MOSFET device is higher, and the device is suitable for being used for switching high-voltage devices higher than 1500V.
In an example, the guard rings 15 are symmetrically distributed, and preferably, the distance between the guard rings 15 is gradually enlarged towards the outer ring, so that the propagation path of the leakage current can be prolonged, and the horizontal leakage risk of the diode device is greatly reduced.
In an example, an alignment layer 20 is disposed between the substrate surface and the dielectric layer 27, so that the subsequent process can perform alignment based on the alignment layer 20, thereby ensuring the device manufacturing quality.
Combining the above examples, a preferred embodiment of the present utility model is shown in fig. 4, where the device includes a substrate, a drain metal layer 9 is disposed on the bottom surface of the substrate, a p+ type region 12 and a guard ring 15 are formed in the substrate, the p+ type region 12 is disposed in the middle region, and the guard ring 15 is located at the periphery; the guard rings 15 are symmetrically distributed with the space therebetween gradually expanding toward the outer ring. The P+ type region 12 is sequentially provided with a P type ion implantation layer 4 and an N type ion implantation layer 3 which are positioned in the substrate;
the substrate is also provided with a grid 13 which penetrates through the P-type ion implantation layer 4 and extends to the bottom of the N-type ion implantation layer 3, a grid oxide layer 16 is arranged between the grid 13 and the P-type ion implantation layer 4 and between the grid 13 and the N-type ion implantation layer 3, a first grid top metal 23 is arranged on the surface of the substrate above the grid 13, a second grid top metal 26 is also arranged on the surface of the substrate, and a grid side wall layer 5 is arranged on the surface of the top layer of the first grid 13 and on the side surface of the second grid top metal 26; the first grid top metal layer 23 is provided with a second source metal layer 62, the surface of the substrate is also provided with a third source metal layer 63, the second source metal layer 62 penetrates through the P-type ion implantation layer 4 and the N-type ion implantation layer 3 at intervals and extends to the P+ type region 12, and the grid 13 is arranged at intervals intersecting with the second source metal layer 62 which penetrates through the P-type ion implantation layer 4 and the N-type ion implantation layer 3 and extends to the P+ type region 12;
the dielectric layer 27 is arranged on the substrate surface, the third source electrode metal layer 63, the gate side wall layer 5 and the third source electrode metal layer 63, the alignment layer 20 is arranged between the substrate surface and the dielectric layer 27, and the alignment layer 20 is preferably arranged at the end part of the substrate; a gate metal contact layer 24 is arranged on the second gate top metal 26, a source metal contact layer 7 is arranged on the third source metal layer 63, and a top protection layer 25 is arranged on the gate metal contact layer 24 and the source metal contact layer 7; when the device is loaded with an operating voltage, a channel region 8 with a vertical structure is formed between the gate 13 and the P-type ion implantation layer 4 by the gate oxide layer 16. The vertical channel region design reduces the length of the grid electrode, reduces the area of the device, and increases the available area of the device channel; meanwhile, compared with a planar device, the channel MOSFET has the advantages of reducing the parasitic of 35 percent, reducing the on-resistance (Ron), and reducing the power consumed by the lower on-resistance device under the normal use condition of the device, and increasing the bearable power of the unit area of the device and increasing the bearable breakdown voltage of the device.
Based on the above preferred examples, the present utility model will be described with respect to a method for manufacturing a SiC MOSFET device, the method comprising the steps of:
s1: sputtering metal on the N-type substrate of SiC as a first alignment layer 20 to obtain a structure shown in FIG. 5;
s2: p-type ion implantation is carried out on the N-type substrate of SiC, the ion implantation energy is about 250KeV, the implantation dosage is about 1E12/cm < 2 >, the implantation depth is deep, the protection ring 15 and the P+ type region 12 at the periphery of the device are formed, and the structure shown in figure 6 is obtained;
s3: after defining a photoresist pattern by a photoetching process, carrying out P-type ion implantation, using the energy of about 150KeV and high-dose implantation of about 1E12/cm < 2 >, as a source contact 14 area of a device, and removing the photoresist to obtain a P-type ion implantation layer 4, wherein the P-type ion implantation layer is shown in figures 7 and 18;
s4: after defining a photoresist pattern by a photoetching process, carrying out N-type ion implantation, wherein the ion implantation energy is about 50KeV, the implantation depth is shallow, the high-dose implantation is about 1E12/cm < 2 >, the ion implantation is a source contact 14 area of a device, and then removing the photoresist to obtain an N-type ion implantation layer 3, so as to obtain a structure shown in fig. 8 and 19;
s5: defining a photoresist pattern of the source metal opening 22 by a photoetching process, etching the SiC substrate, and removing the photoresist after etching to obtain a structure shown in fig. 9 and 20;
s6: defining a grid region of a channel by a photoetching process, etching the SiC substrate, and removing photoresist after etching to obtain a structure shown in fig. 10 and 21;
s7: depositing a silicon dioxide film as a gate oxide layer 16, redefining a gate polysilicon region by a photoetching process, depositing polysilicon material as a gate 13, and removing photoresist to obtain a structure shown in fig. 11 and 22;
s8: the photoetching process defines the photoresist pattern of the grid region of the channel, and after depositing the first grid top metal 23 and the second grid top metal 26, photoresist is removed to obtain the structure shown in fig. 12 and 23;
s9: the top metal of the gate 13 is used as a dry etch stop to etch the silicon dioxide in the source hole, and then silicon dioxide or silicon nitride is deposited again as the gate sidewall layer 5. After redefining the photoresist pattern, dry etching the silicon dioxide or silicon nitride in the source hole, and removing the photoresist to obtain the structure shown in figure 13;
s10: defining a source metal region by a photoetching process, depositing source metal to obtain a first source metal layer 61 and a second source metal layer 62, and removing photoresist to obtain a junction shown in fig. 14 and 24;
s11: depositing a silicon nitride film layer to obtain a dielectric layer 27, and obtaining the structure shown in fig. 15;
s12: defining a photoresist pattern of a first layer of connecting metal and a through hole for connecting the grid electrode 13 and the source electrode by a photoetching process, depositing the first layer of metal after etching a silicon nitride film layer in the through hole to form a grid electrode metal contact layer 24 and a source electrode metal contact layer 7, and removing the photoresist to obtain a structure shown in fig. 16 and 2;
s13: using PBO material, the photolithographic process defines open areas for the first metal layer, forming a top protective layer 25, resulting in the structure shown in fig. 17;
s14: and (3) spin coating wax or glue on the front surface of the crystal source, heating the substrate to enable the substrate to be built on the wafer, and grinding the back of the crystal to the specified thickness.
S15: after metal is deposited on the back of the wafer and the region to be etched is defined by the photoetching process, metal etching is performed, and after photoresist is removed, laser annealing is performed on the metal to enable the collector metal to form ohmic contact, so that a drain metal layer 9 is formed, as shown in fig. 4.
S16: heating the substrate to Jie Jiange, placing the separation substrate and the wafer sheet on the telescopic film, cutting by laser or grinding wheel, and expanding the film after cutting to separate crystal grains to obtain the SiC MOSFET device with the three-dimensional vertical channel structure.
The foregoing detailed description of the utility model is provided for illustration, and it is not to be construed that the detailed description of the utility model is limited to only those illustration, but that several simple deductions and substitutions can be made by those skilled in the art without departing from the spirit of the utility model, and are to be considered as falling within the scope of the utility model.
Claims (7)
1. A SiC MOSFET channel type device characterized in that: the semiconductor device comprises a substrate, wherein a drain electrode metal layer is arranged on the bottom surface of the substrate, a P+ type region and a protection ring are formed in the substrate, the P+ type region is arranged in the middle region, and the protection ring is arranged on the periphery; the P+ type region is sequentially provided with a P type ion implantation layer and an N type ion implantation layer which are positioned in the substrate;
the substrate is also provided with a grid penetrating through the P-type ion implantation layer and extending to the bottom of the N-type ion implantation layer, a grid oxide layer is arranged between the grid and the P-type ion implantation layer and between the grid and the N-type ion implantation layer, the surface of the substrate above the grid is provided with a first grid top metal, the surface of the substrate is also provided with a second grid top metal, and the side surfaces of the first grid top metal and the second grid top metal are provided with grid side wall layers; the first grid electrode top layer metal is provided with a second source electrode metal layer, the surface of the substrate is also provided with a third source electrode metal layer, the second source electrode metal layer penetrates through the P-type ion implantation layer and the N-type ion implantation layer at intervals and extends to the P+ type region, and the grid electrode is arranged at intervals in a crossing manner with the second source electrode metal layer region penetrating through the P-type ion implantation layer and the N-type ion implantation layer and extending to the P+ type region;
a dielectric layer is arranged on the surface of the substrate, the second source electrode metal layer, the grid electrode side wall layer and the third source electrode metal layer; a grid metal contact layer is arranged on the top metal of the second grid, a source metal contact layer is arranged on the third source metal layer, and a top protection layer is arranged on the grid metal contact layer and the source metal contact layer; when the device is loaded with working voltage, a channel region with a vertical structure is formed by a gate oxide layer between the gate and the P-type ion implantation layer.
2. A SiC MOSFET channel type device according to claim 1, characterized in that: the grid electrode is a rectangular matrix array.
3. A SiC MOSFET channel type device according to claim 1, characterized in that: the protection rings are symmetrically distributed.
4. A SiC MOSFET channel device according to claim 1 or 3, characterized in that: the distance between the guard rings gradually expands towards the outer ring.
5. A SiC MOSFET channel type device according to claim 1, characterized in that: the grid side wall layer is a silicon dioxide or silicon nitride film.
6. A SiC MOSFET channel type device according to claim 1, characterized in that: the dielectric layer is a silicon dioxide or silicon nitride film.
7. A SiC MOSFET channel type device according to claim 1, characterized in that: an alignment layer is arranged between the surface of the substrate and the dielectric layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202322191397.4U CN220526924U (en) | 2023-08-15 | 2023-08-15 | SiC MOSFET channel type device |
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| CN202322191397.4U CN220526924U (en) | 2023-08-15 | 2023-08-15 | SiC MOSFET channel type device |
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| CN202322191397.4U Active CN220526924U (en) | 2023-08-15 | 2023-08-15 | SiC MOSFET channel type device |
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