CN220526913U - Packaging piece - Google Patents

Abstract

The application provides a package, comprising: a first redistribution layer including a first pad; a second redistribution layer stacked on the first redistribution layer and including a second pad, wherein the second pad at least partially overlaps the first pad; and a plurality of first through holes disposed spaced apart from each other, wherein one end of the first through hole is connected to the first pad, and the other end of the first through hole is connected to the second pad, wherein a surface of the second pad remote from the first through hole has a plurality of recesses. The problem that the recess is serious because the electroplating area of through-hole is too big has been solved through forming a plurality of first through-holes to this application.

Description

Packaging piece

Technical Field

Embodiments of the present application relate to packages.

Background

In the prior art, referring to fig. 1A, a Wafer Level Chip Scale Package (WLCSP) 11 grows a redistribution layer (RDL) 13 on a chip 12 and forms an Under Bump Metal (UBM) 13P to form a chip package 10, after which the chip package 10 is mounted on a Substrate (SBT) 20'. However, referring to fig. 1B to 1F, in which fig. 1B illustrates a cross-sectional view of a wafer level chip scale package 1 in which a substrate 20 'is replaced with a redistribution layer 20, fig. 1C illustrates a cross-sectional view of the redistribution layer 20 disposed on a carrier 30 through an adhesive layer 40, fig. 1D illustrates a top view along line A-A of fig. 1C, and fig. 1E and 1F illustrate scanning electron microscopy of region R of fig. 1C, in particular, as can be seen from fig. 1B, the redistribution layer chip package 1 having an ultra-thin package profile is produced on a mobile product for the purpose of achieving a slim and slim structure by replacing the substrate 20' with the redistribution layer 20. Referring further to fig. 1B to 1F, when the chip 12 (see fig. 1B) is a PMIC (power management integrated circuit), in order to provide a power transmission path, it may be necessary to form a via hole 20V (aperture 100 μm or more, such as 210 μm or more) having a larger aperture on the dielectric material 20A of the redistribution layer 20 to connect the pads 20P1 and 20P2 (width about 180 μm in the cross-sectional views shown in fig. 1C to 1D). As can be seen from the top view shown in fig. 1D, the respective pads 20P1 and 20P2 are connected by a respective one of the through holes 20V. While larger pore size vias are limited by the ability to fill with metal, such as copper, making them less design limiting. It can be seen that the metal (such as copper) plating in current redistribution layers still has poor via filling capability and will limit its applications, such as PMIC, due to the thinner metal plating thickness. In addition, since the through-holes 20V are formed in a plating manner, the through-holes 20V having a larger aperture may form concave depressions D on the surface, thereby being disadvantageous in terms of stacking the holes E (see fig. 1E and 1F) and controlling the heights of solder balls formed later.

Disclosure of Invention

In order to solve the above-mentioned related technical problems, the present application solves the limitation of the copper filling capability of the through holes by designing the redistribution layer interconnection of the plurality of small through holes, that is, solves the problem of serious recess caused by low current density of electroplating due to too large electroplating area of the through holes by reducing the electroplating area of the through holes.

The application provides a package, comprising: a first redistribution layer including a first pad; a second redistribution layer stacked on the first redistribution layer and including a second pad, wherein the second pad at least partially overlaps the first pad; and a plurality of first through holes arranged at intervals from each other, wherein one end of the first through hole is connected with the first bonding pad, and the other end of the first through hole is connected with the second bonding pad, and the surface of the second bonding pad far away from the first through hole is provided with a plurality of depressions.

In some embodiments, the plurality of recesses corresponds to the respective plurality of first vias.

In some embodiments, each of the plurality of recesses overlaps with a position of the corresponding first through hole in a vertical direction.

In some embodiments, the depths of the plurality of recesses are different from each other.

In some embodiments, a lowest point of each of the plurality of depressions is higher than the first redistribution layer.

In some embodiments, the spacing between adjacent ones of the plurality of first vias is the same or different.

In some embodiments, the first via is connected at a portion where the first pad overlaps the second pad.

In some embodiments, the maximum diameter of the first through holes is substantially the same.

In some embodiments, the width of the first pad in the lateral direction is 10-15 times the maximum diameter of the first via.

In some embodiments, the first via has a maximum diameter of 15-20 μm.

In some embodiments, the first via is tapered in a direction toward the first pad.

In some embodiments, the plurality of first through holes are configured for power delivery.

In some embodiments, the first redistribution layer further comprises a third pad, the second redistribution layer further comprises a fourth pad, the third pad and the fourth pad at least partially overlap, wherein the package further comprises: and a plurality of second through holes, one ends of which are connected to the third pads, and the other ends of which are connected to the fourth pads, wherein the plurality of second through holes are configured for signal transmission.

In some embodiments, the second via is tapered in a direction toward the third pad.

In some embodiments, a ratio of an area of the first via to a surface area of the first pad is less than a ratio of an area of the second via to a surface area of the third pad.

In some embodiments, an area of each of the first vias is less than 1/9 of a surface area of the first pad.

In some embodiments, the area of the first pad is greater than the area of the third pad, and the area of the second pad is greater than the area of the fourth pad.

In some embodiments, the plurality of first vias are entirely covered by the second pads in a top view.

In some embodiments, the package further comprises: a die disposed over the second redistribution layer.

In some embodiments, the maximum diameter of the first through holes is substantially the same.

In summary, the package provided by the present application solves the problem of serious recess caused by low current density of electroplating due to too large electroplating area of the through hole by reducing the electroplating area of the through hole, and solves the limitation of the filling capability of the through hole. And a plurality of through holes are formed on the same bonding pad so as to reduce through hole recessing after copper plating, thereby forming a flat under-bump metal bonding pad with better flip chip assembly window and better welding spot quality.

Drawings

The various aspects of the utility model are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A to 1F show a package of the related art.

Fig. 2 illustrates a package according to some embodiments of the present application.

Fig. 2A-2D illustrate detailed views of packages according to some embodiments of the present application.

Fig. 3A-3C illustrate the electrical performance of a package of the prior art and of some embodiments of the present application.

Fig. 4 illustrates an application of a package according to some embodiments of the present application.

Fig. 4A, 4B-1, and 4C-4D illustrate respective top views of the illustrated package of fig. 4.

Fig. 5 illustrates a cross-sectional view of a package according to some other embodiments.

Fig. 6-15 illustrate a process flow of a package according to some embodiments of the present application.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the utility model. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the utility model.

The problem that the recess is serious due to the fact that the electroplating current density of electroplating is low because the electroplating area of the through hole is too large is solved by reducing the electroplating area of the through hole. Further, forming a plurality of through holes of smaller apertures (such as apertures of about 15 to 20 μm) by electroplating instead of forming a single large-area through hole by electroplating solves the problem of surface dishing of the through holes of a single large aperture (such as apertures of 100 μm or more) formed on the pad.

Referring to fig. 2-2B, the present application provides an encapsulation 1000, specifically, fig. 2B shows a cross-sectional view of the redistribution layers 200-1 to 200-2 in the encapsulation 1000 of fig. 2A disposed on the carrier 300, and fig. 2B shows a cross-sectional view of the redistribution layer 200-1 disposed on the carrier 300. It will be appreciated by those skilled in the art that more redistribution layers may be formed, here exemplified by redistribution layers 200-1 through 200-2, and that a greater number of redistribution layers are within the scope of the present application. As can be seen from fig. 2A to 2B, the package 1000 includes: a first redistribution layer 200-1 including a first pad 200P1; a second redistribution layer 200-2 stacked on the first redistribution layer 200-1 and including a second pad 200P2, wherein the second pad 200P1 at least partially overlaps the first pad 200P 2; and a plurality of first through holes 200V1 disposed spaced apart from each other, wherein one end of the first through hole 200V1 is connected to the first pad 200P1, and the other end of the first through hole 200V1 is connected to the second pad 200P2. Importantly, referring to fig. 2C, fig. 2C shows an enlarged view of the region R ' of fig. 2A and 2B, and as can be seen from fig. 2C, the surface of the second pad 200P2 remote from the first via hole 200V1 has a plurality of recesses D1' -D3'. Further, the plurality of depressions D1'-D3' correspond to the corresponding plurality of first through holes 200V 1. Each of the plurality of recesses D1'-D3' overlaps with the position of the corresponding first via hole 200V1 in the vertical direction, which is the stacking direction of the first pad 200P1, the first via hole 200V1, and the second pad 200P2 in the cross-sectional view as shown in fig. 2C in the present embodiment. In some other embodiments, the depths of the plurality of recesses D1'-D3' are different from each other. In some embodiments, the lowest point P of each of the plurality of depressions D1'-D3' is higher than the first redistribution layer 200-1.

Further, in some embodiments, the spacing S1 or S2 between adjacent first through holes 200V1 among the plurality of first through holes 200V1 is the same or different, and in this embodiment, as shown in the cross-sectional view of fig. 2C, the spacing S1 or S2 between adjacent first through holes 200V1 is measured from between the center lines of the respective first through holes 200V 1. In some embodiments, the spacing S1 or S2 is in the range of between about 20-40 μm.

Further, as can be seen from fig. 2C, the first via hole 200V1 is connected at a portion where the first pad 200P1 overlaps the second pad 200P2. In some embodiments, the first via 200V1 is tapered in a direction toward the first pad 200P1. In some embodiments, the maximum diameter M1 of the first via 200V1 is substantially the same, and in this embodiment, in the cross section shown in fig. 2C, since the first via 200V1 is tapered in a direction toward the first pad 200P1, the maximum diameter M1 of the first via 200V1 is the diameter of the first via 200V1 at the top near the second pad 200P2. Specifically, the maximum diameter M1 of the first via 200V1 is located near the top of the second pad 200P2 and away from the top of the first pad 200P1, and further, the maximum diameter M1 of the first via 200V1 is located on the same horizontal plane (or coplanar) with the bottom surface 200P2d (as shown by the dotted line in fig. 2C) of the second pad 200P2. In some embodiments, the width W of the first pad 200P1 in the lateral direction is 10-15 times the maximum diameter M1 of the first via hole 200V1, and in the cross-sectional view shown in fig. 2C, the lateral direction refers to a direction in which the first pad 200P1 extends laterally, and the width W of the first pad 200P1 in the lateral direction is in a range between about 50-90 μm. In still other embodiments, the maximum diameter M1 of the first via 200V1 is 15-20 μm. In some embodiments, the plurality of first vias 200V1 are configured for power delivery to address dishing of the via surface where the aperture of the via for power delivery is large such that the electroplating process is plating the large aperture via. In some embodiments, the plurality of first via holes 200V1 are entirely covered by the second pad 200P1 in a top view. In some embodiments, the package further comprises: the die 120 is disposed over the second redistribution layer 200-2 as shown in fig. 2. Specifically, as can be seen in fig. 2, die 120 is connected to second redistribution layer 200-2 by solder balls 150 and encapsulated by encapsulant 160. In addition, the package 1000 further includes solder balls 170 disposed on a side of the first redistribution layer 200-1 corresponding to the second redistribution layer 200-2 for power transmission with other components.

In addition, in the package 1000, as shown in fig. 2 to 2D, the first redistribution layer 200-1 further includes a third pad 200P3, the second redistribution layer 200-2 further includes a fourth pad 200P4, and the third pad 200P3 and the fourth pad 200P4 at least partially overlap, in which case the package 1000 further includes: a plurality of second via holes 200V2, one end of the second via holes 200V2 being connected to the third pad 200P3, and the other end of the second via holes 200V2 being connected to the fourth pad 200P4, in this embodiment, the plurality of second via holes 200V2 are each configured for signal transmission. In some additional embodiments, one second via 200V2 may be provided between the respective third and fourth pads 200P3 and 200P4, but it should be understood by those skilled in the art that providing a plurality of second vias 200V2 between the respective third and fourth pads 200P3 and 200P4 may facilitate signal transmission and plating uniformity. Further, for simplicity, fig. 2D shows only one second via 200V2 between the respective third and fourth pads 200P3 and 200P4, but it should be understood that there may be a plurality of second vias 200V2 between the respective third and fourth pads 200P3 and 200P4. In some embodiments, the spacing S3 between the second through holes 200V2 corresponding to the adjacent third pads 200P3 may be adjusted according to practical applications, such as in a range between about 10 to 50 μm.

In some embodiments, the maximum diameter M2 of the second via 200V2 is substantially the same, and in the cross section shown in fig. 2C, since the second via 200V2 is tapered in a direction toward the third pad 200P3, the maximum diameter M2 of the second via 200V2 is the diameter of the second via 200V2 at the top near the fourth pad 200P4. Specifically, the maximum diameter M2 of the second via 200V2 is located near the top of the fourth pad 200P4 and away from the top of the third pad 200P3, and further, the maximum diameter M2 of the second via 200V2 is located on the same level (or coplanar) with the bottom surface 200P4d (as shown by the dotted line in fig. 2C) of the fourth pad 200P4.

Referring next to fig. 2D, fig. 2D shows a top view along line B-B of fig. 2 or fig. 2A. Specifically, in some embodiments, the ratio of the area of the first via 200V1 to the surface area of the first pad 200P1 is smaller than the ratio of the area of the second via 200V2 to the surface area of the third pad 200P3 (see fig. 2 to 2C). In some embodiments, the area of each of the first via holes 200V1 is less than 1/9 of the surface area of the first pad 200P1. In some other embodiments, the area of the first pad 200P1 is greater than the area of the third pad 200P3, and the area of the second pad 200P2 is greater than the area of the fourth pad 200P4.

Next, referring to fig. 3A to 3C, electrical performance simulations are performed on the package 1 shown in fig. 1B and the package 1000 shown in fig. 2 using a method commonly used in the art, and the results show that the electrical performance simulation curves of the package 1 shown in fig. 1B and the package 1000 shown in fig. 2 overlap, that is, the electrical performance is the same, and there is no difference in electrical performance.

In addition, the present application further performs a practical application Test on the package 1000 shown in fig. 2, that is, performs a practical electrical verification on the structure by using a Test Vehicle (TV). Specifically, referring to fig. 4 to 4B, fig. 4B shows a TV 2000 of practical application of the package 1000 designed with the adjacent plurality of first through holes 200V 1. In the TV 2000, a pitch P between adjacent first through holes 200V1 (i.e., a pitch between centerlines of adjacent pads 200P 1) is 350 μm, a pitch S between adjacent through holes among the plurality of first through holes 200V1 is the same or different, and the pitch S is in a range between about 20 to 40 μm. Next, referring to fig. 4A to 4D, fig. 4A shows a top view along a line A1 of fig. 4, fig. 4B shows a top view along a line A2 of fig. 4 and fig. 4B-1 shows an enlarged view of a region Z of fig. 4B, fig. 4C shows a top view along a line A3 of fig. 4, and fig. 4D shows a top view along a line A4 of fig. 4.

As can be seen from fig. 4A to 4D, in the TV 2000, the design of each layer of the redistribution layers 200-1 and 200-2 is completed, and a multi-via relation is employed between the pads 200P1 and 200P2 for plating quality control of the via 200V 1. As can be seen from fig. 4B-1, a plurality of first through holes 200V1 are formed on each first pad 200P1, and a second pad 200P2 covers the plurality of first through holes 200V1 and is used for other wiring. In addition, corresponding openings 200-2O may be formed on the second pad 200P2 for forming other vias or connecting other structures. As further seen in fig. 4A-4D, the package 1000 provided herein is a redistribution layer chip having a very thin package profile, and may be widely used in other electronic applications.

Further, in the prior art, a splayed via is formed for power transmission, as shown in fig. 5, between the corresponding pads of the first and second redistribution layers 200-1 and 200-2, a plurality of third via holes 200V3 are formed, unlike the plurality of first via holes 200V1 provided in the present application that connect the first pad 200P1 to the second pad 200P2 and the plurality of second via holes 200V2 that connect the third pad 200P3 to the fourth pad 200P4, some of the plurality of third via holes 200V3 connect the fifth pad 200P5 to the sixth pad 200P6, and other of the plurality of third via holes 200V3 connect the fifth pad 200P5 to the seventh pad 200P7, thereby forming a splayed via hole in the cross-sectional view shown in fig. 5 that may see the dislocated plurality of third via holes 200V3 in the top view and that do not facilitate the corresponding cross-sectional area, while further ensuring the uniformity of signal transmission and the transmission of the plurality of first via holes 200V1 and the corresponding to the second via holes 200V2 provided in the present application between the first and second redistribution layers 200-1 and 200-2. In addition, uniformity in plating of the plurality of first through holes 200V1 and the plurality of second through holes 200V2 is further improved.

The process flow for forming the package 1000 shown in fig. 2 is described in detail below with reference to fig. 6 through 15.

Referring to fig. 6, solder balls 150 are formed on die 120 by ball-plating, ball-transferring, or the like, and connected to die 120 through dielectric layer 180, thereby forming a pre-fabricated die 100, and pre-fabricated die 100 is placed for use. In some embodiments, dielectric layer 180 is an oxide (such as SiO ₂ )。

Thereafter, referring to fig. 7, a carrier 300 is provided, and a laser release layer 400 is formed over the carrier 300 so as to be removed together with the carrier 300 upon illumination or heating. The laser release layer 400 may be made of a photosensitive material that loses its adhesion when heated. In some embodiments, carrier 300 may provide temporary mechanical and structural support for components of package 1000 formed during subsequent processing steps. For example, the carrier 300 may include glass, silicon oxide, aluminum oxide, or the like.

Referring to fig. 8, after forming the laser release layer 400, the first and second pads 200P1 and 200P2 thereon Fang Diandu, and the forming of the first and second pads 200P1 and 200P2 may include depositing a seed layer (not shown) using a mask layer (not shown) having respective openings to define the shape of the first and second pads 200P1 and 200P2. For example, the openings are then filled using an electroplating process. Excess portions of the mask layer and seed layer may then be removed. In some embodiments, the first and second pads 200P1 and 200P2 may use any suitable metal, such as copper.

Next, referring to fig. 9, a dielectric layer 200-1A is formed to cover the first and second pads 200P1 and 200P2. In some embodiments, the dielectric layer 200-1A includes an oxide (e.g., siO ₂ ) Polyimide, and the like. In other embodiments, the dielectric layer 200-1A comprises an oxide (e.g., siO) formed by a deposition process (e.g., chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), etc.) ₂ ). Thereafter, openings 200-1O (e.g., by a laser drilling process) corresponding to the locations of the plurality of first and second conductive vias 200V1 and 200V2 may be formed in the dielectric layer 200-1A. As can be seen in fig. 9, a plurality of openings 200-1O are formed in the same pad at intervals.

Subsequently, referring to fig. 10, a seed layer may be formed in these openings 200-1A and a plurality of first and second conductive vias 200V1 and 200V2 may be plated over the seed layer, thereby forming a first redistribution layer 200-1. Other forming processes such as sputtering, evaporation, PECVD, etc. may alternatively be used depending on the desired materials. Note that the plurality of first conductive vias 200V1 are spaced apart from each other and correspond to the first pads 200P1.

After forming the plurality of first and second conductive vias 200V1 and 200V2, second and fourth pads 200P2 and 200P4 are formed over the first redistribution layer 200-1. The second and fourth pads 200P2 and 200P4 are formed identically or similarly to the first and third pads 200P1 and 200P3, and a description thereof will not be repeated here.

Referring to fig. 11, a dielectric layer 200-2 is formed in a similar manner to the formation of dielectric layer 200-1A, and openings 200-2O are formed in dielectric layer 200-2 by a laser drilling process, thereby forming a second redistribution layer 200-2. The openings 200-2O correspond to the solder balls 150 in the pre-fabricated die 100 of fig. 6.

Thereafter, referring to fig. 12, the pre-fabricated die 100 of fig. 6 is bonded to the second redistribution layer 200-2, and the solder balls 150 in the pre-fabricated die 100 are bonded to the second redistribution layer 200-2 by reflow.

Referring to fig. 13, the pre-fabricated die 100 is encapsulated with an encapsulant 160, which encapsulant 160 may use a compound such as a molding compound, a molding underfill, or the like.

Referring to fig. 14 to 15, the carrier 300 and the laser release layer 400 are removed by laser irradiation or heating or the like, thereby forming the structure shown in fig. 15. Finally, solder balls 170 are formed on a surface of the first redistribution layer 200-1 of the structure shown in fig. 15 opposite the second redistribution layer 200-2, such as by ball-plating, to form the package 1000 shown in fig. 2.

In summary, the package 1000 provided herein is a redistribution layer chip having a ultra-thin package profile. The limitation of the filling capability of vias (e.g., the plurality of first conductive vias 200V1 of copper) may be addressed by the interconnection of the redistribution layers (e.g., the first and second redistribution layers 200-1 and 200-2) of the plurality of smaller vias (the plurality of first conductive vias 200V 1). And a plurality of through holes are formed on the same bonding pad so as to reduce through hole recessing after copper plating, thereby forming a flat under bump metal bonding pad, and having better flip chip assembly window and better welding spot quality.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present utility model. Those skilled in the art will appreciate that they may readily use the present utility model as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the utility model, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the utility model.

Claims (10)

1. A package, comprising:

a first redistribution layer including a first pad;

a second redistribution layer stacked on the first redistribution layer and including a second pad, wherein the second pad at least partially overlaps the first pad; and

a plurality of first through holes disposed spaced apart from each other, wherein one end of the first through holes is connected to the first pad, and the other end of the first through holes is connected to the second pad,

the surface of the second bonding pad far away from the first through hole is provided with a plurality of depressions.

2. The package of claim 1, wherein the plurality of recesses correspond to the respective plurality of first vias.

3. The package of claim 2, wherein each of the plurality of recesses vertically overlaps with a location of the corresponding first through hole.

4. The package of claim 1, wherein the depths of the plurality of recesses are different from each other.

5. The package of claim 1, wherein a lowest point of each of the plurality of depressions is higher than the first redistribution layer.

6. The package of claim 1, wherein a pitch between adjacent ones of the plurality of first vias is the same or different.

7. The package of claim 1, wherein the first via is connected at a portion where the first pad overlaps the second pad.

8. The package of claim 1, wherein the first through hole is tapered in a direction toward the first pad.

9. The package of claim 1, wherein the plurality of first vias are configured for power delivery.

10. The package of claim 9, wherein the first redistribution layer further comprises a third pad, the second redistribution layer further comprises a fourth pad, the third pad and the fourth pad at least partially overlap, wherein the package further comprises:

a plurality of second through holes, one ends of which are connected to the third pads, and the other ends of which are connected to the fourth pads,

wherein the plurality of second vias are each configured for signal transmission.