CN108305865B - Substrate structure and method for fabricating the same - Google Patents
Substrate structure and method for fabricating the same Download PDFInfo
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- CN108305865B CN108305865B CN201710059612.1A CN201710059612A CN108305865B CN 108305865 B CN108305865 B CN 108305865B CN 201710059612 A CN201710059612 A CN 201710059612A CN 108305865 B CN108305865 B CN 108305865B
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- 239000000758 substrate Substances 0.000 title claims abstract description 108
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000013461 design Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 110
- 238000002161 passivation Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000005336 cracking Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- KMWHNPPKABDZMJ-UHFFFAOYSA-N cyclobuten-1-ylbenzene Chemical compound C1CC(C=2C=CC=CC=2)=C1 KMWHNPPKABDZMJ-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920003192 poly(bis maleimide) Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
A substrate structure and a method for fabricating the same, comprising: the substrate comprises a substrate body, an insulating part arranged on one side of the substrate body, a conductive layer arranged in the insulating part, a conductive through hole formed in the substrate body and electrically connected with the conductive layer, and a metal layer formed on the other side of the substrate body and electrically connected with the conductive through hole, so that the strength of the substrate structure is enhanced through the design of the substrate body.
Description
Technical Field
The present invention relates to a semiconductor structure, and more particularly, to a substrate structure and a method for fabricating the same.
Background
With the continuous innovation of electronic industry technology and the development of electronic packaging products in the directions of light weight, high performance, high density distribution, etc., the packaging type has been developed from planar to three-dimensional stacking, and thus three-dimensional integrated circuits (3D ICs) have become the main trend of the packaging technology.
In the conventional three-dimensional integrated circuit type semiconductor package, a semiconductor chip is mounted on a Silicon interposer (TSI) Through a plurality of solder bumps, wherein the TSI has a plurality of Through-Silicon vias (TSVs) and a Redistribution layer (RDL) electrically connecting the plurality of Through-Silicon vias and the plurality of solder bumps, the TSI is bonded to a package substrate Through the plurality of Through-Silicon vias and a plurality of conductive elements, the conductive elements and the plurality of solder bumps are encapsulated by an underfill, and the semiconductor chip and the TSI are encapsulated by an encapsulant.
Fig. 1A to 1C are schematic cross-sectional views illustrating a conventional method for processing a semi-finished substrate structure 1 such as a Wafer type silicon interposer.
As shown in fig. 1A, a silicon substrate 11 is provided, on which a circuit layer 110 and an oxide layer 12 are formed, and bonded to a glass carrier 10 through an adhesive layer 100.
As shown in fig. 1B, the silicon plate 11 is then removed.
As shown in fig. 1C, an insulating layer 13 is formed on the oxide layer 12 and the circuit layer 110, a metal layer 14 is formed on the insulating layer 13, a conductive via 140 is formed in the insulating layer 13, the metal layer 14 is electrically connected to the circuit layer 110 through the conductive via 140, and a solder bump 15 is formed on the metal layer 14, so that the substrate structure 1 is combined with other electronic devices (not shown) through the solder bumps 15.
However, the conventional substrate structure 1 has a problem that the structural strength is not good, and thus cracks are likely to occur during the production process.
Therefore, how to overcome the above problems of the prior art has become a problem to be solved.
Disclosure of Invention
In view of the above drawbacks of the prior art, the present invention provides a substrate structure and a method for fabricating the same, so as to enhance the strength of the substrate structure by the design of the substrate body.
The substrate structure of the present invention includes: the substrate comprises a substrate body, a first substrate and a second substrate, wherein the substrate body is provided with a first surface and a second surface which are opposite; an insulating part arranged on the first surface of the substrate body; a conductive layer provided in the insulating portion; a conductive via formed in the substrate body and connecting the first surface and the second surface and extending to the conductive layer so that the conductive via is electrically connected to the conductive layer; and a metal layer formed on the second surface of the substrate body to electrically connect the conductive through hole.
The invention also provides a method for manufacturing the substrate structure, which comprises the following steps: providing a silicon substrate, wherein the silicon substrate comprises a substrate body with a first surface and a second surface which are opposite, an insulating part arranged on the first surface and a conducting layer arranged in the insulating part; forming a through hole on the second surface of the substrate body, wherein the through hole is communicated with the first surface and the second surface and extends to the conductive layer so that the conductive layer is exposed out of the through hole; and forming a metal layer on the second surface of the substrate body, and forming a conductive through hole in the through hole so that the metal layer is electrically connected with the conductive layer through the conductive through hole.
In the foregoing substrate structure and the manufacturing method thereof, the insulating portion includes a first insulating layer combined on the first surface, a second insulating layer disposed on the first insulating layer, and a third insulating layer disposed on the second insulating layer, wherein the conductive layer is disposed on the first insulating layer and located in the second insulating layer and the third insulating layer, and the conductive layer is exposed from the third insulating layer.
In the foregoing substrate structure and the manufacturing method thereof, an opening is further formed on the second surface of the substrate body, wherein the opening can communicate the first surface and the second surface, so that the insulating portion is exposed out of the opening.
In the foregoing substrate structure and the method for fabricating the same, the insulating portion is bonded to a carrier before the through hole is formed.
In the foregoing substrate structure and the method for fabricating the same, a conductive element is further formed on the metal layer.
In view of the above, the substrate structure and the manufacturing method thereof of the present invention mainly enhance the overall structural strength of the substrate structure through the design that the silicon substrate includes the substrate body, so compared with the prior art, the substrate structure of the present invention can avoid the problem of cracking during the production process.
Drawings
Fig. 1A to 1C are schematic cross-sectional views illustrating a conventional method for processing a semi-finished substrate structure;
FIGS. 2A to 2E are schematic cross-sectional views illustrating a method for fabricating a substrate structure according to the present invention;
FIG. 3A is a schematic partial cross-sectional view of another embodiment of a substrate structure of the present invention; and
fig. 3B is a partial top plan view of fig. 3A after a metal layer is formed.
Description of the symbols:
1,2 substrate structure
10 glass carrier plate
100 adhesive layer
11 silicon plate
110 circuit layer
12 oxide layer
13 insulating layer
14,24 metal layer
140,240 conductive vias
15 solder bump
2a silicon substrate
2b reinforcement structure
20 load bearing member
200 bonding layer
21 substrate body
21a first surface
21b second surface
210 conductive layer
22 insulating part
22a first insulating layer
22b second insulating layer
22c third insulating layer
220 perforation
23 passivation layer
230 connecting part
241 cushion part
25 conductive element
320 opening
9 patterned photoresist
t thickness.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship thereof may be regarded as the scope of the present invention without substantial technical changes.
Fig. 2A to fig. 2E are schematic cross-sectional views illustrating a method for manufacturing the substrate structure 2 according to the present invention.
As shown in fig. 2A, a silicon substrate 2A is provided, which includes a substrate body 21 having a first surface 21a and a second surface 21b opposite to each other, an insulating portion 22 disposed on the first surface 21a, and at least one conductive layer 210 disposed in the insulating portion 22. Then, the insulating portion 22 is bonded to a carrier 20.
In the present embodiment, the substrate body 21 is a silicon wafer, a silicon interposer (TSI) or a glass substrate, and the substrate body 21 serves as a non-circuit region, and the insulating portion 22 and the conductive layer 210 serve as a circuit region.
In addition, the insulating portion 22 includes a first insulating layer 22a combined on the first surface 21a, a second insulating layer 22b disposed on the first insulating layer 22a, and a third insulating layer 22c disposed on the second insulating layer 22b, wherein the conductive layer 210 is disposed on the first insulating layer 22a and located in the second and third insulating layers 22b,22 c. For example, the first insulating layer 22a is formed of silicon oxide (SiO)2) Silicon nitride (Si)xNy) Or an organic insulating material such as Polybenzoxazole (PBO), Polyimide (PI), phenylcyclobutene (BCB), Bismaleimide Triazine (BT), etc., and the second and third insulating layers 22b,22c are formed of an organic insulating material such as Polybenzoxazole (PBO), Polyimide (PI), phenylcyclobutene (BCB), Bismaleimide Triazine (BT), etc.
The insulating portion 22 is bonded to the carrier 20 by a bonding layer 200, wherein the carrier 20 is a glass plate, and the bonding layer 200 is a release film, an adhesive, or other materials that facilitate separation of the insulating portion 22 and the carrier 20.
In addition, the surface of the conductive layer 210 is exposed to the third insulating layer 22c, so that the conductive layer 210 contacts the bonding layer 200. Specifically, as shown in fig. 2A, the surface of the conductive layer 210 is flush with the surface of the third insulating layer 22 c; alternatively, an opening exposing the conductive layer 210 may be formed on the third insulating layer 22 c.
As shown in fig. 2B, at least one through hole 220 is formed on the second surface 21B of the substrate body 21, and the through hole 220 is connected to the first surface 21a and extends to the first insulating layer 22a of the insulating portion 22, so that the conductive layer 210 is exposed out of the through hole 220.
In the present embodiment, the through hole 220 is manufactured by forming the patterned photoresist 9 on the second surface 21b of the substrate body 21, etching, drilling, laser or other methods to form the through hole 220, and then removing the patterned photoresist 9.
As shown in fig. 2C, a passivation layer 23 is formed in the through hole 220 (e.g., on the sidewall of the through hole) and on the second surface 21b of the substrate body 21.
In the present embodiment, the passivation layer 23 can be formed by an oxide layer or a nitride layer, such as silicon oxide (SiO)2) Or silicon nitride (Si)xNy) The passivation layer 23 may be formed by Chemical Vapor Deposition (CVD).
As shown in fig. 2D, a metal layer 24 is formed on the passivation layer 23 on the second surface 21b of the substrate body 21, and a conductive via 240 is formed in the via 220, such that the metal layer 24 is electrically connected to the conductive layer 210 through the conductive via 240.
In the present embodiment, the metal layer 24 has a pad 241 as an Under Bump Metallurgy (UBM).
In addition, the metal layer 24 (the pad portion 241 and the conductive via 240) may be formed by a dual damascene method, or a patterning process may be performed by sputtering or plating in combination with exposure and development to form the metal layer 24 and the conductive via 240. However, the metal layer 24 and the conductive via 240 can be fabricated in a variety of ways, and are not limited to the above.
The metal layer 24 and the conductive via 240 are formed of, for example, ti/cu/ni or ti/ni-v/cu. However, the materials of the metal layer 24 and the conductive via 240 are various and not limited to the above.
As shown in fig. 2E, a conductive element 25 is formed on the pad portion 241 of the metal layer 24, such that the substrate structure 2 is combined with other electronic devices (not shown) such as a semiconductor wafer, a chip, a package substrate or a circuit board through the plurality of conductive elements 25.
In the present embodiment, the conductive elements 25 are solder bumps, metal bumps, or other blocks, and are not particularly limited.
In addition, after the conductive elements 25 are formed, the carrier 20 and the bonding layer 200 may be removed as required.
In the manufacturing method of the present invention, the non-circuit region of the silicon substrate 2a, i.e. the substrate body 21, is designed to enhance the structural strength of the substrate structure 2, so that compared with the prior art, the substrate structure 2 of the present invention can avoid the problem of cracking during the manufacturing process. Further, the substrate body 21 and the passivation layer 23 form a reinforced structure 2b, so that the substrate structure 2 can be made thinner and stronger.
In addition, compared to a silicon interposer with a general thickness of 100 micrometers (um), the substrate structure 2 of the present invention is designed as a thin interposer, and the thickness t of the circuit region (the insulating portion 21 and the conductive layer 22) and the non-circuit region (the substrate body 20) is 5 to 10 micrometers (um), respectively.
In addition, the non-circuit area can be patterned to achieve the purpose of reducing material but strengthening the substrate structure 2. As shown in fig. 3A, at least one opening 320 is further formed on the second surface 21b of the substrate body 21, and the opening 320 is communicated with the first surface 21b, so that the first insulating layer 22a of the insulating portion 22 is exposed out of the opening 320, and then the passivation layer 23 extends along the wall surface of the opening 320 to be formed in the opening 320. Specifically, the opening 320 may be formed by etching the opening 320 according to the design of the patterned photoresist 9 during the formation of the through hole 220.
In the present embodiment, the pattern formed by the openings 320 may be rectangular, hexagonal, or various geometric patterns, so that the passivation layer 23 has a plurality of connecting portions 230 to connect between the pad portions 241 of the metal layers 24, as shown in fig. 3B. For example, since the triangular profile is the most stable stress distribution state and is not easy to deform when being stressed, the preferred pattern of the opening 320 is the triangular-like profile (the connecting portion 230 or the reinforcing structure 2B constitutes the edge thereof) as shown in fig. 3B to form a stable stress structure, thereby reinforcing the strength of the substrate structure 2 and achieving the effect of light weight.
It should be understood that a single pad 241 may be connected to another pad 241 by at least one connection 230, and is not limited to the pattern shown in fig. 3B.
The present invention provides a substrate structure 2, comprising: a silicon substrate 2a, at least one conductive via 240, and a metal layer 24.
The silicon substrate 2a includes a substrate body 21 having a first surface 21a and a second surface 21b opposite to each other, an insulating portion 22 disposed on the first surface 21a, and a conductive layer 210 disposed in the insulating portion 22.
The conductive through hole 240 is formed in the substrate body 21 and communicates with the first and second surfaces 21a,21b and extends to the conductive layer 210, so that the conductive through hole 240 is electrically connected to the conductive layer 210.
The metal layer 24 is formed on the second surface 21b of the substrate body 21 to electrically connect to the conductive via 240.
In one embodiment, the insulating portion 22 includes a first insulating layer 22a bonded on the first surface 21a, a second insulating layer 22b disposed on the first insulating layer 22a, and a third insulating layer 22c disposed on the second insulating layer 22b, and the conductive layer 210 is disposed on the first insulating layer 22a and located in the second and third insulating layers 22b,22c, wherein a surface of the conductive layer 210 is exposed to the third insulating layer 22 c.
In an embodiment, an opening 320 is further formed on the second surface 21b of the substrate body 21, and the opening 320 is communicated with the first surface 21a, so that the first insulating layer 22a of the insulating portion 22 is exposed out of the opening 320.
In an embodiment, the substrate structure 2 further includes a carrier 20 bonded to the third insulating layer 22c of the insulating portion 22.
In one embodiment, the substrate structure 2 further includes a conductive element 25 formed on the metal layer 24.
In summary, the substrate structure and the method for manufacturing the same of the present invention can enhance the structural strength of the substrate structure by the arrangement of the substrate body, so as to avoid the problem of cracking of the substrate structure during the production process.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (10)
1. A substrate structure, characterized in that the substrate structure comprises:
the substrate comprises a substrate body, a first substrate and a second substrate, wherein the substrate body is provided with a first surface and a second surface which are opposite to each other, and an opening communicated with the first surface is formed on the second surface of the substrate body;
the insulating part is arranged on the first surface of the substrate body and exposed out of the opening;
a conductive layer provided in the insulating portion;
a conductive via formed in the substrate body and connecting the first surface and the second surface and extending to the conductive layer so that the conductive via is electrically connected to the conductive layer; and
and the metal layer is formed on the second surface of the substrate body and is electrically connected with the conductive through hole.
2. The substrate structure of claim 1, wherein the insulating portion comprises a first insulating layer bonded to the first surface, a second insulating layer disposed on the first insulating layer, and a third insulating layer disposed on the second insulating layer, wherein the conductive layer is disposed on the first insulating layer and within the second and third insulating layers.
3. The substrate structure of claim 2, wherein the conductive layer is exposed to the third insulating layer.
4. The base structure of claim 1, further comprising a carrier bonded to the insulating portion.
5. The substrate structure of claim 1, further comprising a conductive element formed on the metal layer.
6. A method of fabricating a substrate structure, the method comprising:
providing a silicon substrate, wherein the silicon substrate comprises a substrate body with a first surface and a second surface which are opposite, an insulating part arranged on the first surface and a conducting layer arranged in the insulating part, and an opening communicated with the first surface is formed on the second surface of the substrate body so that the insulating part is exposed out of the opening;
forming a through hole on the second surface of the substrate body, wherein the through hole is communicated with the first surface and the second surface and extends to the conductive layer so that the conductive layer is exposed out of the through hole; and
and forming a metal layer on the second surface of the substrate body, and forming a conductive through hole in the through hole so that the metal layer is electrically connected with the conductive layer through the conductive through hole.
7. The method of claim 6, wherein the insulating portion comprises a first insulating layer bonded to the first surface, a second insulating layer disposed on the first insulating layer, and a third insulating layer disposed on the second insulating layer, wherein the conductive layer is disposed on the first insulating layer and located in the second insulating layer and the third insulating layer.
8. The method of claim 7, wherein the conductive layer is exposed to the third insulating layer.
9. A method of fabricating a substrate structure according to claim 6, further comprising bonding the insulating portion to a carrier before forming the through-hole.
10. The method of claim 6, further comprising forming conductive elements on the metal layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106101182 | 2017-01-13 | ||
| TW106101182A TWI614862B (en) | 2017-01-13 | 2017-01-13 | Substrate structure and the manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108305865A CN108305865A (en) | 2018-07-20 |
| CN108305865B true CN108305865B (en) | 2020-06-09 |
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| CN201710059612.1A Active CN108305865B (en) | 2017-01-13 | 2017-01-24 | Substrate structure and method for fabricating the same |
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| CN (1) | CN108305865B (en) |
| TW (1) | TWI614862B (en) |
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| TWI679424B (en) * | 2019-03-29 | 2019-12-11 | 矽品精密工業股份有限公司 | Detection device and manufacturing method thereof |
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| CN2901485Y (en) * | 2006-05-30 | 2007-05-16 | 北京蓝星达科技有限责任公司 | Electronic dynamic medium plate |
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| CN105470235A (en) * | 2014-08-12 | 2016-04-06 | 矽品精密工业股份有限公司 | Interposer and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5502139B2 (en) * | 2012-05-16 | 2014-05-28 | 日本特殊陶業株式会社 | Wiring board |
| TWI614861B (en) * | 2015-01-30 | 2018-02-11 | 矽品精密工業股份有限公司 | Electronic package structure and the manufacture thereof |
| TWI587458B (en) * | 2015-03-17 | 2017-06-11 | 矽品精密工業股份有限公司 | Electronic package and the manufacture thereof and substrate structure |
-
2017
- 2017-01-13 TW TW106101182A patent/TWI614862B/en active
- 2017-01-24 CN CN201710059612.1A patent/CN108305865B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2901485Y (en) * | 2006-05-30 | 2007-05-16 | 北京蓝星达科技有限责任公司 | Electronic dynamic medium plate |
| CN202503026U (en) * | 2012-03-10 | 2012-10-24 | 重庆环亚电子有限公司 | Light emitting diode (LED) mounting device |
| CN105470235A (en) * | 2014-08-12 | 2016-04-06 | 矽品精密工业股份有限公司 | Interposer and method of manufacturing the same |
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| Publication number | Publication date |
|---|---|
| TWI614862B (en) | 2018-02-11 |
| CN108305865A (en) | 2018-07-20 |
| TW201826474A (en) | 2018-07-16 |
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