CN108305865A - Substrate structure and method for fabricating the same - Google Patents
Substrate structure and method for fabricating the same Download PDFInfo
- Publication number
- CN108305865A CN108305865A CN201710059612.1A CN201710059612A CN108305865A CN 108305865 A CN108305865 A CN 108305865A CN 201710059612 A CN201710059612 A CN 201710059612A CN 108305865 A CN108305865 A CN 108305865A
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- Prior art keywords
- insulating layer
- layer
- conductive
- board structure
- substrate body
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- 239000000758 substrate Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 238000009413 insulation Methods 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 238000002360 preparation method Methods 0.000 claims description 21
- 238000013461 design Methods 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000000059 patterning Methods 0.000 description 6
- 239000011230 binding agent Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 3
- 229920003192 poly(bis maleimide) Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910020776 SixNy Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- UJMBCHVRTIOTKC-UHFFFAOYSA-N cyclobutylbenzene Chemical compound C1CCC1C1=CC=CC=C1 UJMBCHVRTIOTKC-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229920000297 Rayon Polymers 0.000 description 1
- 125000002252 acyl group Chemical group 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A substrate structure and a method for fabricating the same, comprising: the substrate comprises a substrate body, an insulating part arranged on one side of the substrate body, a conductive layer arranged in the insulating part, a conductive through hole formed in the substrate body and electrically connected with the conductive layer, and a metal layer formed on the other side of the substrate body and electrically connected with the conductive through hole, so that the strength of the substrate structure is enhanced through the design of the substrate body.
Description
Technical field
The present invention is in relation to a kind of semiconductor structure, espespecially a kind of board structure and its preparation method.
Background technology
As electronic industry technology is constantly brought forth new ideas and Electronic Packaging product tends to frivolous, high-effect, high density distribution etc.
Direction is developed, and so that encapsulation pattern has been evolved by plane three-dimensional stacked, and then make three-dimensional integrated circuit (3D integrated
Circuits, 3D ICs) as the main trend of encapsulation technology now.
Semiconductor wafer is set to a silicon by existing three-dimensional integrated circuit formula semiconductor package part by multiple solder bumps
On intermediate plate (Through Silicon interposer, abbreviation TSI), wherein there are the silicon intermediate plate multiple conductive silicons to wear
Hole (Through-silicon via, abbreviation TSV) and the line for being electrically connected multiple conductive silicon perforation and multiple solder bump
Road redistribution layer (Redistribution layer, abbreviation RDL), and the silicon intermediate plate by multiple conductive silicon perforation with it is multiple
Conducting element is bound on a package substrate, then coats multiple conducting element and multiple solder bump with primer, and with envelope
Dress colloid coats the semiconductor wafer and the silicon intermediate plate.
Figure 1A to Fig. 1 C is the semi-finished product processing side of the existing such as board structure 1 of wafer-shaped (Wafer type) silicon intermediate plate
The schematic cross-sectional view of method.
As shown in Figure 1A, a silicon plate body 11 is provided, is formed with a line layer 110 and oxide layer 12 thereon, and penetrate and stick together
Layer 100 is bound in a glass support plate 10.
As shown in Figure 1B, the silicon plate body 11 is then removed.
As shown in Figure 1 C, an insulating layer 13 is formed in the oxide layer 12 and the line layer 110, re-forms a metal layer 14
In on the insulating layer 13, and conductive through holes 140 are formed in the insulating layer 13, the metal layer 14 is made to pass through the conductive through holes
140 are electrically connected the line layer 110, re-form solder bump 15 on the metal layer 14, make the board structure 1 by multiple
Solder bump 15 combines other electronic devices (figure omits).
However, in existing board structure 1, because its structural strength is bad, and it is easy to generate asking for rupture in process of production
Topic.
Therefore, how to overcome above-mentioned problem of the prior art, have become want to solve the problems, such as at present in fact.
Invention content
In view of the disadvantages of the above-mentioned prior art, a kind of board structure of present invention offer and its preparation method, to pass through the base
The design of plate ontology and the intensity for strengthening the board structure.
The present invention board structure include：Substrate body, with opposite first surface and second surface；Insulation division,
It is set on the first surface of the substrate body；Conductive layer is set in the insulation division；Conductive through holes are formed in the substrate
It in ontology and is connected to the first surface and second surface and extends to the conductive layer, to enable the conductive through holes be electrically connected the conduction
Layer；And metal layer, it is formed on the second surface of the substrate body to be electrically connected the conductive through holes.
The present invention also provides a kind of preparation methods of board structure comprising：A silicon substrate is provided, which has comprising one
The substrate body of opposite first surface and second surface, the insulation division on the first surface and in the insulation division
Conductive layer；Perforation is formed in the second surface of the substrate body, wherein the perforation is connected to the first surface and second surface and prolongs
The conductive layer is extended to, to enable the conductive layer expose to the perforation；And form metal layer on the second surface of the substrate body,
And conductive through holes are formed in the perforation, to enable the metal layer be electrically connected the conductive layer by the conductive through holes.
In board structure above-mentioned and its preparation method, the insulation division include be incorporated into the first insulating layer on the first surface,
Second insulating layer on first insulating layer and the third insulating layer in the second insulating layer, wherein the conductive layer is set
In on first insulating layer and in the second insulating layer and third insulating layer, and the conductive layer exposes to the third insulating layer.
In board structure above-mentioned and its preparation method, opening is also formed on the second surface of the substrate body, wherein this is opened
Mouth can be connected to the first surface and second surface, to enable the insulation division expose to the opening.
Further include that the insulation division is bound to one and is held before forming the perforation in board structure above-mentioned and its preparation method
In holder.
Further include forming conducting element on the metal layer in board structure above-mentioned and its preparation method.
Include mainly the substrate body by the silicon substrate from the foregoing, it will be observed that in the board structure and its preparation method of the present invention
Design, to strengthen the overall construction intensity of the board structure, therefore compared with the prior art, board structure of the invention can avoid
Rupture is led to the problem of in production process.
Description of the drawings
Figure 1A to Fig. 1 C is the diagrammatic cross-section of the method for processing semi-finished product of existing board structure；
Fig. 2A to Fig. 2 E is the schematic cross-sectional view of the preparation method of the board structure of the present invention；
Fig. 3 A are the partial schematic sectional view of another embodiment of the board structure of the present invention；And
Fig. 3 B are that Fig. 3 A form the local upper viewing view after metal layer.
Symbol description：
1,2 board structures
10 glass support plates
100 adhesion layers
11 silicon plate bodys
110 line layers
12 oxide layers
13 insulating layers
14,24 metal layers
140,240 conductive through holes
15 solder bumps
2a silicon substrates
2b reinforced structures
20 load-bearing parts
200 binder courses
21 substrate bodies
21a first surfaces
21b second surfaces
210 conductive layers
22 insulation divisions
The first insulating layers of 22a
22b second insulating layers
22c third insulating layers
220 perforation
23 passivation layers
230 interconnecting pieces
241 pad portions
25 conducting elements
320 openings
9 patterning photoresists
T thickness.
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this explanations below by way of particular specific embodiment
The revealed content of book understands other advantages and effect of the present invention easily.
It should be clear that structure, ratio, size etc. depicted in this specification institute accompanying drawings, only coordinating specification to be taken off
The content shown is not limited to the enforceable qualifications of the present invention for the understanding and reading of those skilled in the art, therefore
Do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size are not influencing the present invention
Under the effect of can be generated and the purpose that can reach, it should all still fall and obtain the model that can cover in disclosed technology contents
In enclosing.Meanwhile cited such as "upper", " first ", " second " and " one " term in this specification, it is also only convenient for narration
It is illustrated, rather than to limit the scope of the invention, relativeness is altered or modified, in without substantive change technology
It holds, when being also considered as the enforceable scope of the present invention.
Fig. 2A to Fig. 2 E is the schematic cross-sectional view of the preparation method of the board structure 2 of the present invention.
As shown in Figure 2 A, a silicon substrate 2a is provided, it includes one to have opposite first surface 21a and second surface 21b
Substrate body 21, one be set to first surface 21a on insulation division 22 and at least one be set to the insulation division 22 in conductive layer
210.Then, which is bound on a load-bearing part 20.
In this present embodiment, which is Silicon Wafer, silicon intermediate plate (TSI) or glass substrate, and the substrate sheet
Body 21 is as logicalnot circuit area, and the insulation division 22 is used as line areas with the conductive layer 210.
In addition, the insulation division 22 includes to be incorporated into the first insulating layer 22a on first surface 21a, be set to this first absolutely
The second insulating layer 22b and third insulating layer 22c on second insulating layer 22b on edge layer 22a, wherein the conductive layer
210 be set to first insulating layer 22a it is upper and positioned at this second and third insulating layer 22b, 22c in.For example, forming first insulation
The material of layer 22a is silica (SiO2), silicon nitride (SixNy) or such as polybenzoxazoles (Polybenzoxazole, abbreviation
PBO), polyimides (Polyimide, abbreviation PI), phenyl cyclobutane (benzocyclobutane, abbreviation BCB), span carry out acyl
The organic insulation material of imines triazine (Bismaleimide Triazine, abbreviation BT) etc., and formed this second with third insulating layer
The material of 22b, 22c are such as polybenzoxazoles (Polybenzoxazole, abbreviation PBO), polyimides (Polyimide, abbreviation
PI), phenyl cyclobutane (benzocyclobutane, abbreviation BCB), Bismaleimide Triazine (Bismaleimide
Triazine, abbreviation BT) etc. organic insulation material.
Also, the insulation division 22 is bound to binder course 200 on the load-bearing part 20, wherein the load-bearing part 20 is glass plate, and
The binder course 200 is fractal film, viscose or other materials for being easily isolated the insulation division 22 and the load-bearing part 20.
In addition, the conductive layer 210 is surface exposed in third insulating layer 22c, the conductive layer 210 is made to contact the binder course
200.Specifically, as shown in Figure 2 A, the surface of the conductive layer 210 flushes the surface of third insulating layer 22c；Alternatively, also can be in
The trepanning of the exposed conductive layer 210 is formed on third insulating layer 22c.
As shown in Figure 2 B, at least one perforation 220 is formed on the second surface 21b of the substrate body 21, and the perforation 220
It is connected to first surface 21a and extends to the first insulating layer 22a of the insulation division 22, worn with enabling the conductive layer 210 expose to this
Hole 220.
In this present embodiment, the processing procedure of the perforation 220 is prior to forming patterning on the second surface 21b of the substrate body 21
Photoresist 9, then the perforation 220 is formed with etching, machine drill, laser or other means, the patterning photoresist 9 is removed later.
As shown in Figure 2 C, a passivation layer 23 (side wall of such as perforation) and the substrate body 21 in the perforation 220 are formed
Second surface 21b on.
In this present embodiment, the material for forming the passivation layer 23 can be oxide layer or nitration case, such as silica (SiO2) or
Silicon nitride (SixNy), and chemical vapour deposition technique (Chemical Vapor Deposition, abbreviation CVD) mode shape can be used
At the passivation layer 23.
As shown in Figure 2 D, a metal layer 24 is formed on the passivation layer 23 of the second surface 21b of the substrate body 21, and shape
At conductive through holes 240 in the perforation 220, the metal layer 24 is made to be electrically connected the conductive layer 210 by the conductive through holes 240.
In this present embodiment, which has pad portion 241 using as convex block underlying metal layer (Under Bump
Metal, abbreviation UBM).
In addition, damascene process can be used to be integrally formed makes the metal layer 24 (the pad portion 241 and the conductive through holes 240),
Alternatively, patterning process can be carried out, in such a way that sputter (sputter) or plating (plating) coordinate exposure imaging with shape
At the metal layer 24 and the conductive through holes 240.However, the metal layer 24 and the production method of the conductive through holes 240 are various, not
It is limited to above-mentioned person.
Also, the material for forming the metal layer 24 and the conductive through holes 240 is such as titanium/copper/nickel or titanium/nickel vanadium/copper.So
And the material type of the metal layer 24 and the conductive through holes 240 is various, however it is not limited to above-mentioned person.
As shown in Figure 2 E, conducting element 25 is formed in the pad portion 241 of the metal layer 24, makes the board structure 2 by this
Multiple conducting elements 25 combine other electronic devices (figure omits), for example, semiconductor crystal wafer, chip, package substrate or wiring board.
In this present embodiment, which is solder bump, metal coupling or other blocks etc., has no special limit
System.
In addition, after forming the conducting element 25, the load-bearing part 20 and the binder course 200 can be removed on demand.
In the preparation method of the present invention, by the design in the logicalnot circuit area of silicon substrate 2a, that is, the setting of the substrate body 21,
To strengthen the structural strength of the board structure 2, therefore compared with the prior art, board structure 2 of the invention can avoid producing
Rupture is led to the problem of in journey.Further, reinforced structure 2b is constituted by the substrate body 21 and the passivation layer 23, the base can be made
Harden structure 2 is made thinner, and structure is stronger.
In addition, compared to the silicon intermediate plate that general thickness is 100 microns (um), during board structure 2 of the invention is slim
Jie's plate designs, and line areas (insulation division 21 and the conductive layer 22) and the thickness t in logicalnot circuit area (substrate body 20) distinguish
For 5 to 10 microns (um).
Also, the logicalnot circuit area can carry out patterning schemes, to reach mitigation material, but still strengthen the mesh of the board structure 2
's.As shown in Figure 3A, at least one opening 320 is also formed on the second surface 21b of the substrate body 21, and the opening 320 connects
Lead to first surface 21b, to enable the first insulating layer 22a of the insulation division 22 expose to the opening 320, then makes 23 edge of passivation layer
The wall surface of the opening 320 extends to be formed in the opening 320.Specifically, the production method of the opening 320 can be worn forming this
When hole 220, the design according to the patterning photoresist 9 etches the opening 320 together.
In this present embodiment, which, which is formed by pattern, to be rectangle, hexagon or various geometric figures etc., make
The passivation layer 23 have multiple interconnecting pieces 230 to be connected to the pad portion 241 of the respectively metal layer 24 between, as shown in Figure 3B.For example,
Since triangular-shaped profile is most stable of stress distribution, it is unlikely to deform when stress, therefore the 320 preferable pattern of opening
It is stable to be formed for class triangular-shaped profile (interconnecting piece 230 or reinforced structure 2b constitute its edge) as shown in Figure 3B
Thus stress structure body strengthens the intensity of the board structure 2, and reach structure lightened effect simultaneously.
It should be appreciated that ground, single pad portion 241 can connect another pad portion 241 by an at least interconnecting piece 230, however it is not limited to scheme
Pattern shown in 3B.
The present invention provides a kind of board structure 2 comprising：One silicon substrate 2a, at least a conductive through holes 240 and a metal
Layer 24.
The silicon substrate 2a has the substrate body 21 of opposite first surface 21a and second surface 21b comprising one, sets
In the insulation division 22 on first surface 21a and the conductive layer 210 in the insulation division 22.
The conductive through holes 240 are formed in the substrate body 21 and are connected to first and second surface 21a, 21b simultaneously
The conductive layer 210 is extended to, to enable the conductive through holes 240 be electrically connected the conductive layer 210.
The metal layer 24 is formed on the second surface 21b of the substrate body 21 to be electrically connected the conductive through holes
240。
In an embodiment, which includes the first insulating layer 22a being incorporated on first surface 21a, is set to
The second insulating layer 22b and third insulating layer 22c on second insulating layer 22b on first insulating layer 22a, and this is led
Electric layer 210 is on first insulating layer 22a and in the second and third insulating layer 22b, 22c, wherein the conductive layer
210 it is surface exposed in third insulating layer 22c.
In an embodiment, opening 320 is also formed on the second surface 21b of the substrate body 21, and the opening 320 connects
Lead to first surface 21a, to enable the first insulating layer 22a of the insulation division 22 expose to the opening 320.
In an embodiment, the board structure 2 further includes a load-bearing part 20, and the third for being incorporated into the insulation division 22 is exhausted
On edge layer 22c.
In an embodiment, board structure 2 further includes conducting element 25, is formed on the metal layer 24.
In conclusion the board structure and its preparation method of the present invention, by the setting of the substrate body, to strengthen the substrate knot
The structural strength of structure, therefore it is avoided that the board structure leads to the problem of rupture in process of production.
Above-described embodiment is only to be illustrated the principle of the present invention and its effect, and is not intended to limit the present invention.Appoint
What those skilled in the art can without violating the spirit and scope of the present invention modify to above-described embodiment.Therefore originally
The rights protection scope of invention, should be as listed in the claims.
Claims (12)
1. a kind of board structure, it is characterized in that, which includes：
Substrate body, with opposite first surface and second surface；
Insulation division is set on the first surface of the substrate body；
Conductive layer is set in the insulation division；
Conductive through holes are formed in the substrate body and are connected to the first surface and second surface and extend to the conductive layer,
To enable the conductive through holes be electrically connected the conductive layer；And
Metal layer is formed on the second surface of the substrate body to be electrically connected the conductive through holes.
2. board structure according to claim 1, it is characterized in that, which includes the be incorporated on the first surface
One insulating layer, the second insulating layer on first insulating layer and the third insulating layer in the second insulating layer, wherein
The conductive layer is set on first insulating layer and in the second insulating layer and third insulating layer.
3. board structure according to claim 2, it is characterized in that, which exposes to the third insulating layer.
4. board structure according to claim 1, it is characterized in that, it is also formed with out on the second surface of the substrate body
Mouthful.
5. board structure according to claim 1, it is characterized in that, which further includes being incorporated on the insulation division
Load-bearing part.
6. board structure according to claim 1, it is characterized in that, which further includes being formed on the metal layer
Conducting element.
7. a kind of preparation method of board structure, it is characterized in that, which includes：
A silicon substrate is provided, which has the substrate body of opposite first surface and second surface comprising one, is set to and is somebody's turn to do
Insulation division on first surface and the conductive layer in the insulation division；
Perforation is formed in the second surface of the substrate body, wherein the perforation is connected to the first surface and second surface and extends
To the conductive layer, to enable the conductive layer expose to the perforation；And
Metal layer is formed on the second surface of the substrate body, and forms conductive through holes in the perforation, to enable the metal layer
It is electrically connected the conductive layer by the conductive through holes.
8. the preparation method of board structure according to claim 7, it is characterized in that, which includes to be incorporated into the first surface
On the first insulating layer, the second insulating layer on first insulating layer insulate with the third in the second insulating layer
Layer, wherein the conductive layer is set on first insulating layer and in the second insulating layer and third insulating layer.
9. the preparation method of board structure according to claim 8, it is characterized in that, which exposes to the third insulating layer.
10. the preparation method of board structure according to claim 7, it is characterized in that, shape is gone back on the second surface of the substrate body
At there is opening.
11. the preparation method of board structure according to claim 7, it is characterized in that, the preparation method further include in formed the perforation it
Before, which is bound on a load-bearing part.
12. the preparation method of board structure according to claim 7, it is characterized in that, the preparation method further include to be formed conducting element in
On the metal layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106101182A TWI614862B (en) | 2017-01-13 | 2017-01-13 | Substrate structure and the manufacture thereof |
| TW106101182 | 2017-01-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108305865A true CN108305865A (en) | 2018-07-20 |
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| CN111751578A (en) * | 2019-03-29 | 2020-10-09 | 矽品精密工业股份有限公司 | Detection device and manufacturing method thereof |
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| CN2901485Y (en) * | 2006-05-30 | 2007-05-16 | 北京蓝星达科技有限责任公司 | Electronic dynamic medium plate |
| CN202503026U (en) * | 2012-03-10 | 2012-10-24 | 重庆环亚电子有限公司 | Light emitting diode (LED) mounting device |
| CN105470235A (en) * | 2014-08-12 | 2016-04-06 | 矽品精密工业股份有限公司 | Interposer and method of manufacturing the same |
| CN105990268A (en) * | 2015-01-30 | 2016-10-05 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
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| JP5502139B2 (en) * | 2012-05-16 | 2014-05-28 | 日本特殊陶業株式会社 | Wiring board |
| TWI587458B (en) * | 2015-03-17 | 2017-06-11 | 矽品精密工業股份有限公司 | Electronic package and the manufacture thereof and substrate structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2901485Y (en) * | 2006-05-30 | 2007-05-16 | 北京蓝星达科技有限责任公司 | Electronic dynamic medium plate |
| CN202503026U (en) * | 2012-03-10 | 2012-10-24 | 重庆环亚电子有限公司 | Light emitting diode (LED) mounting device |
| CN105470235A (en) * | 2014-08-12 | 2016-04-06 | 矽品精密工业股份有限公司 | Interposer and method of manufacturing the same |
| CN105990268A (en) * | 2015-01-30 | 2016-10-05 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111751578A (en) * | 2019-03-29 | 2020-10-09 | 矽品精密工业股份有限公司 | Detection device and manufacturing method thereof |
| CN111751578B (en) * | 2019-03-29 | 2023-05-09 | 矽品精密工业股份有限公司 | Detection device and manufacturing method thereof |
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| CN108305865B (en) | 2020-06-09 |
| TWI614862B (en) | 2018-02-11 |
| TW201826474A (en) | 2018-07-16 |
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