TW201218322A - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure includes a substrate, an annular dam, an adhesive layer, a chip, a first dielectric layer and a redistribution circuit structure. The annular dam is disposed on an upper surface of the substrate and defines an accommodating cavity with the substrate. The chip is disposed in the accommodating cavity and fixed on the substrate by the adhesive layer. The chip has an active surface away from the upper surface of the substrate and a plurality of pads disposed on the active surface. The first dielectric layer is disposed on the upper surface and surrounds the chip. The redistribution circuit structure is disposed on the first dielectric layer and includes at least a patterned conductive layer electrically connected to the pads of the chip.

Description

201218322 ASEK23 8 5- l-NEW-FINAL-TW-20110217 VI. Field of the Invention: The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor package structure and Production Method. [Prior Art] The purpose of the chip package is to protect the exposed wafer, reduce the density of dots, and provide crystals; f See (4) The piece is wire-bonded or pulled, 曰 u , ^ or flip-bonded (flip chb bondmg), etc., to the point - the _ point can be electrically connected to the package carrier. Therefore, the package on the board is reconfigured to match the distribution of the next. ΤI-level external component connection [Summary] Structure for packaging a wafer. Structure manufacturing method for

The present invention provides a semiconductor package. The present invention provides a semiconductor package for fabricating the above semiconductor package structure. The present invention proposes a semiconductor package - an annular barrier, an adhesive layer, a substrate, a substrate, and a repeating wiring structure. The substrate has a —=, — a first dielectric layer and an upper surface of the substrate, and a middle surface. The annular resist body is arranged to be recessed. The adhesive layer is disposed in the cavity, and has a plurality of pads disposed on the receiving concave active surface away from the substrate, and the active surface is disposed on the substrate Pull the layer and fix it on the base 201218322 ASEK2385-1-NEW-FINAL-TW-20110217. The first dielectric layer is disposed on the upper surface of the substrate and surrounds the wafer. The redistribution line structure is disposed on the first (di) dielectric layer and includes at least one patterned conductive layer, wherein the patterned conductive layer is electrically connected to the interface of the wafer. The present invention further proposes a method of fabricating a semiconductor package structure, wherein the fabrication method comprises the following steps. A _ substrate and a plurality of ring-shaped blocking bodies are provided. The substrate has an upper surface, and the annular resist is formed on the upper surface, and each of the annular barrier defines a receiving recess with the substrate. An adhesive layer is formed in each of the receiving pockets. Disposing a wafer in each of the accommodating pockets, wherein each of the crystals passes through the adhesive layer and is mosquito-repellent on the substrate, and each of the wafers has a surface away from the substrate and a plurality of surfaces disposed on the active surface Pads. Configuring a first dielectric layer on the upper surface of the substrate, wherein the first dielectric layer surrounds the wafer, and the surface of the first dielectric layer away from the upper surface of the substrate is substantially aligned with the active surface of the crystal moon (or low) On the active side of the film). Forming a redistribution line structure on the first (di) dielectric layer, the medium redistribution line structure includes at least a patterned conductive layer, and the patterned V electrical layer is electrically connected to the interface of the wafer. Based on the above, when the wafer is disposed on the substrate through the adhesive layer, the ring-shaped nucleus of the present invention can effectively limit the water-flip force fcU of the wafer relative to the substrate. Therefore, the alignment accuracy between the wafer and the substrate can be improved, and the process yield of the semiconductor package structure can be improved. The above features and advantages of the present invention will become more apparent from the following description. 1A is a schematic cross-sectional view of a semiconductor package structure 201218322 ASEK2385'! -NEW-FINAL-TW-20110217 according to an embodiment of the present invention. Figure 1B is a picture! A schematic view of the block of the semiconductor of the eight. Referring to FIG. 1A and FIG. 1 , the semiconductor package structure (10) includes a substrate u, an implementation body two-copper layer 125, an adhesion layer 13A, a wafer 14: two: an electrical layer 152 and A repeating line structure 2〇〇. Decrease = fr 12. The annular blocking body i2〇a is disposed on the upper surface 112 of the substrate m, wherein the annular blocking body is applied

The plate 110 defines a receiving pocket 122a, such as a substantially closed-closed frame-shaped annular blocking body, as shown in Figure 1B. The copper layer 125 is disposed on the lower surface 114 of the substrate 110 relative to the upper surface 112. The layer 130 is placed on the upper surface 112 of the substrate 110, and a portion of the tensile layer 130 is located within the receiving recess. The wafer 140 is fixed to the substrate no via the adhesive layer 130. The wafer 14G has an active surface 142 away from the upper surface 112 of the substrate 11 and a plurality of pads 144 disposed on the active surface 142. The mth electrical layer 52 is disposed on the upper surface 112 of the substrate 110 and is wound around the wafer 140. In this embodiment, the semiconductor package structure 1 further includes a conductive layer 154, 156, wherein the conductive layers 154, 156 are respectively located on opposite side surfaces of the first dielectric layer 152, and the conductive layers 154, 156 The first dielectric layer 152 can be viewed as a high structural layer. Wherein, the surface of the germanium high structure layer away from the surface of the upper surface of the substrate 11Q (that is, the surface of the conductive layer 154 away from the first dielectric layer 152) is lower than or substantially intrinsic with the W Μ0 tilting surface 142 ′ and is higher The structural layer can be fixed to the upper surface μ of the substrate 11 () through the adhesive layer 130. In another embodiment, the germanium high structural layer may also be only a dielectric layer, wherein 201218322 A〇c.ivzj85-l-lSrEW-FINAL-TW-20110217 the material of the dielectric layer is, for example, A glass fiber resin or a fiber containing no fiber, which is, for example, an ABF resin or an ABF-like resin. Among them, when the material of the dielectric layer is a resin containing glass fiber, the strength and uniformity of the package can be effectively improved. The redistribution line structure 200 is disposed on the conductive layer 154. In this embodiment, the redistribution line structure 200 includes at least one second dielectric layer 21A (only one is shown in FIG. 1A), at least one patterned conductive layer 220 (only one of which is shown in FIG. 1A), and an Zinc layer 230. The second dielectric layer 21 is disposed on the conductive layer 154 on the first dielectric layer 152 and on the wafer 14 , wherein the second dielectric layer 210 has a plurality of first openings 212 , and the first openings 212 respectively These ports 144 of the wafer 140 are exposed. The patterned conductive layer 220 is disposed on the second dielectric layer 210, wherein the patterned conductive layer 220 is electrically connected to the pads 144 of the wafer 140 through the first openings 212. The solder resist layer 230 is disposed on the patterned conductive layer 22 , and has a plurality of second openings 232 , wherein the second openings 232 expose a portion of the patterned conductive layer 220 , and a portion of the patterns of the second openings 232 are exposed. The conductive layer 220 can define a plurality of contacts 234 for use as contacts for electrical connection to an external circuit (not shown). It should be noted here that the present invention does not limit the shape of the redistribution line structure 2,, although the redistribution line structure 2 此处 described herein is embodied by a second dielectric layer 21〇, A laminated structure of a patterned conductive layer 22A and a solder resist layer 230. However, in other embodiments, the redistribution wiring structure 200 may also be a stacked structure composed of a solder resist layer 23 〇 and a plurality of alternately stacked second dielectric layers 210 and patterned conductive layers 22 , The second dielectric layer 21〇 and the patterned conductive layer 22〇201218322 ASitiK^i85-l-NEW-FINAL-TW-20110217 are located between the solder resist layer 230 and the substrate lio, and the patterned conductive layer 220 can transmit a plurality of conductive layers. Connection structures (not shown), such as conductive vias, are electrically connected to each other. Therefore, the redistribution circuit structure 200 illustrated in FIG. 1A is for illustrative purposes only and is not limited thereto. In the present embodiment, the substrate 110 is, for example, a resin substrate containing glass fibers. The material of the annular barrier 120a may include metal, solder or resin, wherein the metal is, for example, copper. Furthermore, the height of the annular barrier 12a may be between 20 micrometers and 1 micrometer, preferably between 3 micrometers and #70 micrometers, and the width of the annular barrier body 120a. It can range from 1 μm to 3000 μm. Further, although the semiconductor package structure 100 referred to herein has the copper layer 125, in other embodiments, the semiconductor package structure 100 may not have the copper layer 125. In short, the semiconductor package structure 100 of the present embodiment is merely illustrative and not limited thereto. When the cymbal sheet 140 is disposed on the substrate through the adhesive layer 130, the dam-shaped barrier 120a can effectively limit the horizontal range of motion of the wafer 14 〇 relative to the substrate 11 。. Therefore, the alignment accuracy between the wafer 14A and the substrate 11A can be improved. However, the present invention does not limit the structural design of the annular barrier 120a, although the annular barrier 12〇& referred to herein is embodied as a closed frame-shaped annular barrier 'but known Other structural designs that can rely on the locating effect are still within the scope of this (four) pleasing (four) technical solution without departing from the scope of the invention. For example, referring to FIG. 2A, the annular resisting body is, for example, a rectangular annular resist having at least one notch 124b (four notches shown in FIG. 2A), wherein the notches 1 are respectively located Rectangular ring 201218322 l-NEW-FINAL-TW-20110217 ASfcK2385- Four sides S1 of the resistive body. U ^ is 'Please refer to FIG. 2B . The annular resist body is, for example, a large barrier such as a notch 12 (the eight notches 124C are shown in FIG. 2B ), wherein each side of the rectangular annular resist is There are two notches 124c. Alternatively, in May, referring to FIG. 2C, the annular blocking body is, for example, a notch 124d (FIG. 2C shows eight missing σ 124d), and the shape-like blocking body 'the gap of the rectangular annular resisting body 124d is located at four sides S3 and four corners c of the annular barrier. The annular resist body 12% (or (10) c, md) of the present embodiment is such that the rectangular annular barrier squeegee adhesive layer 130 of the notches l24b (or 124e, 124d) is pressed by the wafer 14 而. Extending into the deficiencies (or 124c, 124d) to enable the wafer (10) to be evenly disposed in the valley of the valley, meaning that the active surface M2 of the wafer (10) can be used in conjunction with FIG. 3A in another embodiment. FIG. 3K illustrates in detail a method of fabricating a semiconductor package structure 100a. The solid 3A to FIG. 3K are cross-sectional views showing a method of fabricating a semiconductor package structure according to an embodiment of the present invention. Referring to FIG. 3A, first, a substrate 110, a plurality of annular barriers 12a (only one of which is shown in FIG. 3), and a copper layer 125 are provided. The substrate no has an upper surface 112 and a lower surface Π4 with respect to the upper surface 112, and the annular barrier 12〇a is formed on the upper surface 112 of the substrate 11〇, and the copper layer 125 is disposed on the lower surface 114 of the substrate on. Wherein, the annular resist body i2〇a and the substrate 11A define a recess 122a. Here, the annular barrier body i20a is substantially a 201218322 ASEK23 85-1 -NEW-FINAL-TW-20110217 closed annular barrier, as shown in FIG. Of course, in other embodiments, referring to FIG. 2A to FIG. 2C, the annular barriers 120b, 120b, and 120c may also be rectangular annular barriers having at least one cutouts 124b to 124d, wherein the cutouts 124b to 124d are located at least. The sides SI, S2, S3 or the corners C of the annular barriers 12〇b, 120b, 120c are not limited herein. The shape of the substrate 110 in this embodiment is, for example, a rectangle, that is, the substrate 110 is not a wafer having a specific size limitation, wherein the substrate 110

For example, it is a resin substrate containing glass fiber. The material of the annular barrier 120a includes metal, solder or resin, wherein the metal is, for example, copper. Further, in the present embodiment, the height of the 'annular barrier body 12〇a may be between 2 μm and 100 μm, preferably between 30 μm and 70 μm, and the annular barrier 120a The width can range from 100 microns to 3000 microns. Next, referring to FIG. 3B, an adhesive layer 13 is formed on the upper surface 112 of the substrate 11', wherein a portion of the adhesive layer 13 is located in the receiving recess 122a. Further, the adhesive layer 13 is made of epoxy resin.卬(10).... It must be noted herein that the present invention does not limit the position of the adhesive layer 13〇' although the adhesive layer 13〇 mentioned herein is embodied as being located on the upper surface 112 of the substrate ιι, meaning Place the recess 122a::Electrical (4) where it is to be placed. However, in other cases where the 'adhesive layer 13' can be placed in the recessed pocket, it can only be placed in the recess. This is shown in Figure 3B. The position of the adhesive layer π 仅为 is only limited by way of example. Next, referring to FIG. 3C , a wafer 140 is disposed in the receiving pocket U2a 201218322 ASEK2385-1-NEW-FINAL-TW-20110217, wherein The wafer 140 is fixed to the substrate 11 through the adhesive layer 130. The wafer 14 has an active surface 142 away from the upper surface m of the substrate 11 and a plurality of interfaces 144 disposed on the active surface 142. In particular, it can be known from 3C + that the annular resist body 120a of the present embodiment can limit the wafer 14〇. For the horizontal range of motion of the substrate 11 , it is meant that a portion of the side of the wafer 140 will bear or be located in the receiving recess 122a formed by the annular barrier 120a and the substrate 11〇. 120b (or 12〇c, 12〇d) is a rectangular annular barrier having these notches 124b (or 124c, 124d) (see Figures 2A-2C), the partial adhesive layer 130 can extend to the notch 12牝 (or 124c) 124d), so that the wafer 140 can be disposed flatly in the accommodating recess 122a. Therefore, the active surface 142 of the wafer 14 can be maintained horizontal relative to the substrate 110, which is advantageous for subsequent processes. Next, please refer to FIG. 3D. A first dielectric layer 152 is disposed on the upper surface 112 of the substrate 110, wherein the first dielectric layer 152 surrounds the wafer 14 and the first dielectric layer 152 is away from a surface and a wafer of the upper surface 112 of the substrate 11 The active surface 142 of the 140 is substantially aligned (or lower than the active surface of the wafer). Next, conductive layers 154, 156 are disposed on opposite side surfaces of the first dielectric layer 152, respectively, wherein the conductive layers 154, 156 and A dielectric layer 152 can be viewed as a high structural layer, and the entire high structure The adhesion layer 130 can be fixed on the upper surface 112 of the substrate 110. In another embodiment, please refer to FIG. 4A, the pad structure layer can also be only a first dielectric layer 150, wherein the first dielectric layer The material of 150 is, for example, a glass fiber-containing resin or a glass fiber-free resin, which is, for example, ABF resin or ABF-like 'moon 曰. When the first dielectric layer 150 is made of a glass fiber-containing resin, 201218322 ASEK2385 -1-NEW-FINAL-TW-20110217 can effectively improve the strength and uniformity of the package. Next, a redistribution wiring structure 200a (see Fig. 3J) is formed on the conductive layer 154. In the present embodiment, the steps of forming the redistribution line structure 2A are as shown in Figs. 3E to 31. First, referring to FIG. 3E, a second dielectric layer 210 is disposed on the pad structure layer (ie, the conductive layer 154 on the first dielectric layer 152) and the active surface M2 of the wafer 140. Of course, in FIG. 4B, the second dielectric layer 210 can be disposed directly on the dielectric layer 150 and the active surface 142 of the wafer 140. Then, a first opening 212 of the tabs 144 of the wafer 140 is formed on the second dielectric layer 21, wherein the first openings 212 are formed by, for example, laser drilling or exposure. The material of the second dielectric layer 210 is, for example, a resin coated COpper, a resin, an ABF-like resin, a photosensitive resin or a prepreg resin. Next, referring to FIG. 3F, a plating seed layer 225 is formed on the second dielectric layer 210 and in the first openings 212. Next, referring to FIG. 3G, a patterned photoresist layer 228 is formed on the electroplated seed layer 225, wherein the exposed photoresist layer 228 is partially exposed in the first opening 212 and the second dielectric layer 21 The electric ore seed layer 225. Next, referring to FIG. 3H, the patterned photoresist layer 228 is used as a plating mask to perform an electro-minening process to plate a patterned conductive layer 22 to expose a portion of the electro-forged seed layer exposed by the patterned photoresist layer 228. 225. The conductive layer 220 is electrically connected to the via 144 of the wafer 14 through the first opening 212. A portion of the plating seed layer 225 under the patterned photoresist layer 228 and below is then removed to expose a portion of the second dielectric layer 11 201218322 ASEK23 85-1-WW-FINAL-TW-2011〇217 210. Figure J31, forming - the solder resist layer 230 is patterned, and the portion 230 is covered with a portion of the patterned conductive layer 220 and the electrical layer 21Q. In this embodiment, 232, and the second openings 232 are violent' Part of the figure acts as a conductive layer to this point, and A completes the last of the redistributed line structure 200a.

Referring to FIG. 31 and FIG. 3j, a plurality of dicing lines are performed [to perform a -JF bulking process] to form a plurality of semiconductor package structures. FIG. 3J only shows one). Thus far, the fabrication of the semiconductor package structure 100a is substantially completed. Of course, referring to FIG. 3K, in order to increase the applicability of the semiconductor package structure i〇〇a, a plurality of solder balls 250 may be separately formed in the second openings 232 of the solder resist layer 23 before the singulation process. The portions of the patterned conductive layer 22G are exposed to mean the contacts 234 such that the solder balls 250 directly contact the patterned conductive layer 22A. Then, a single & process is performed to form a plurality of semiconductor package structures 1b (only in FIG. 3K)

Green shows one). In addition, although the semiconductor package structures 100a, 100b referred to herein have a copper layer 125' located on the lower surface 114 of the substrate 11'b, in other embodiments, the 'semiconductor package structures 100a, 100b may not have copper. Layer 125, which is intended to remove the steel layer 125 after the singulation process, exposes the lower surface 114 of the substrate. In short, the semiconductor package structures 1a, 1b of the present embodiment are merely illustrative and are not limited thereto. Further, the following two embodiments will be used to explain the application of the fabrication method of the semiconductor package junction 12 12 201218322 ASEK2385-1-NEW-FINAL-TW-20110217. It is to be noted that the following embodiments use the same reference numerals and parts in the foregoing embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. The description of the omitted portions can be referred to the foregoing embodiment. The following embodiments will not be repeated. 5A to 5K are cross-sectional views showing a method of fabricating a semiconductor package structure according to another embodiment of the present invention. Referring to Figure 5A, first, a substrate 110 and two copper layers 125a, 125b are provided. The substrate 110 has an upper surface #112 and a lower surface 114 opposite to the upper surface 112, and the copper layers 125a, 125b are disposed on the upper surface 112 and the lower surface 114 of the substrate 11A, respectively. Next, referring to FIG. 5B, at least one conductive via structure 160 is formed through the substrate 11A (only two are schematically shown in FIG. 5B), wherein the conductive via structures 160 connect the upper surface 112 and the lower surface 114 of the substrate 110. . Next, at least one first pad 162 (only two are schematically shown in FIG. 5B) and a patterned circuit layer 164 are formed on the upper surface φ 112 of the substrate 110, and at least one second pad 166 is formed (FIG. 5B). Only two are shown schematically on the lower surface 114 of the substrate 110. In this embodiment, the conductive via structures 160 are formed by mechanical drilling and plated through holes (PTH). The first pads 162 and the second pads 166 are formed by patterning the copper layers 125a, 125b, respectively. In addition, the first pads 162 and the second pads 166 are respectively connected to the conductive via structures 160. Next, referring again to FIG. 5B, at least one annular barrier 12a is formed on the upper surface 112 of the substrate 110. [The annular resistive body i2〇a and the base 13 201218322 j 85-1 -NEW-FINAL-TW The -20110217 plate 110 can define a receiving pocket 122a. These annular dams 12a can be formed by patterning the copper layer 125a. Here, the annular barrier 120a is substantially a closed annular resist, as shown in FIG. 1B, but is not limited thereto.

Next, referring to FIG. 5C, at least one conductive pillar 168 (FIG. 5C = only two schematically shown) is formed on the first pads 162 ±, and the material of the V pillars 168 is, for example, copper. In this embodiment, the conductive posts 168 can be formed by lithography forming a plating mask and by electroplating. Next, referring to FIG. 5D, an adhesive layer 13 is formed on the upper surface 112 of the substrate ι, wherein a portion of the adhesive layer 130 is located in the accommodating recess i22a. More specifically, the adhesive layer 13 is located in the accommodating recess 122a and behind, the first dielectric layer 152 shown in FIG. 5E is placed, and the adhesive layer m is further filled with the first age 162. The annular barrier i2〇a is between the annular barrier layer 164 and the patterned circuit layer 164. Next, the wafer-140 is disposed in the receiving cavity 122a, wherein the wafer 14 is fixed to the substrate U through the adhesive layer 13 , wherein the crystal # 140 has an active surface 142 away from the upper surface 112 of the substrate 110 and A plurality of f ΪΓ 4 disposed on the active surface 142. In particular, it can be seen from s 5D that the ring μ i i2 〇 a of the present embodiment can limit the horizontal movement of the wafer 140 relative to the substrate no = the side of the 〜 曰 170 丨 〇 〇 〇 〇 〇 会 或It is located in the receiving recess 122a formed by the annular blocking body 12'' and the substrate 110. Next, referring to FIG. 5E, a first dielectric layer 152= and two conductive layers 154 and 156 surrounding the wafer 140 are disposed on the upper surface ι2 of the substrate, wherein the conductive layers B4 and 156 are respectively located on the first dielectric. The opposite sides of the layer 152 201218322 ASEK2385-1-NEW-FINAL-TW-20110217, and the conductive layers 154, 156 and the second dielectric layer 丨 52 can be regarded as a high structural layer, and the high structural layer The town is fixed to the upper surface U2 of the substrate 1 through the adhesive layer 130. Before the high structural layer is disposed on the substrate 110, at least one through hole 152a (only two are schematically shown in FIG. 5E) penetrating through the first dielectric layer 152 and the conductive layers 154, 156 is formed. Then, please refer to FIG. 5F. The conductive pillars 168 are respectively disposed in the through holes 152a, and the high structural layer is fixed to the partial adhesive layer 130 and the partial first pads 162 through a bonding film 132 or the like. The annular barrier 120a and the patterned wiring layer ι64. Next, a redistribution wiring structure 200a (see Fig. 5J) is formed on the conductive layer 154. In the present embodiment, the steps of forming the redistribution line structure 2〇〇a are as shown in Figs. 5F to 5J. First, referring to FIG. 5F, a second dielectric layer 21A is disposed on the active structure layer 142 of the pad 140 on the pad structure layer (ie, the conductive layer 154 on the first dielectric layer 152). Then, a plurality of the contacts 144 exposing the wafer 140 and the first openings 212a of the conductive posts I68 are formed on the second dielectric layer 210a. Next, please refer to FIG. 5G to form a plating seed layer 225 on the second dielectric layer 21A and the first openings 212a. Next, referring to FIG. 5H, a patterned photoresist layer 228 is formed on the electric ore seed layer 225, wherein the exposed portion of the patterned photoresist layer 228 is located in the first port 212a and the second dielectric layer 21A. Sublayer 225. ★ Next, please refer to FIG. 51, the electroplating process is performed by patterning the photoresist layer 228 as a plating mask, and the conductive layer 220 is patterned by the electric money. FIG. 15 201218322 Αδϋ^ζ j 85-1 -NEW-FINAL-T The W-20110217 is patterned on the partially plated seed layer 225 exposed by the photoresist layer 228. The patterned conductive layer 220 is electrically connected to the pads 144 of the wafer 140 and the conductive pillars 168 through the electrodeposited seed layer 225 in the first openings 212a. Thereafter, the patterned photoresist layer 228 and a portion of the forged seed layer 225' under it are removed to expose a portion of the second dielectric layer 21A. Then, referring to FIG. 5J, a anti-friction layer 230 is formed on the patterned conductive layer 220, wherein the solder resist layer 23 covers a portion of the patterned conductive layer 22A and a portion of the second dielectric layer 210a. In the present embodiment, the solder resist layer 23 has a plurality of second openings 232, and the second openings 232 expose a portion of the patterned conductive layer 220. At this point, the production of the redistribution line structure 2〇〇a is substantially completed. Finally, referring to Fig. 5J, a singulation process is performed along the plurality of dicing lines 1 to form a plurality of semiconductor package structures 1a. Thus, the fabrication of the semiconductor package structure 1a is substantially completed. Of course, referring to FIG. 5K, in order to increase the applicability of the semiconductor package structure i〇〇a, a plurality of solder balls 250 may be respectively formed on the second openings 232 of the solder resist layer 230 after the singulation process. The portions of the patterned conductive layer 220, that is, the contacts 234, are exposed such that the solder balls 250 directly contact the patterned conductive layer 22A. That is, the semiconductor package structure 100b' can be electrically connected to an external circuit (not shown) through the solder balls 25'. Since the present embodiment has a conductive via structure 160 penetrating through the substrate 110 and a conductive pillar 168 disposed in the via hole 152a of the pad pattern structure layer (that is, the first dielectric layer 152 and the conductive layers 154, 156), wherein The patterned conductive layer 220 is electrically connected to the pads 144 of the wafer 140 and the conductive pillars 168, and the conductive pillars 201218322 ASbK.2 J 85-1 -NEW-FINAL-TW- 20110217 168 is electrically connected to the conductive via structures 16 and the second pads 166 through the first pads 162. Therefore, the heat generated by the operation of the wafer 140 can be transmitted to the patterned conductive layer 220 of the metal material, the conductive pillars 168, the first pads 162, the conductive via structures 16 and the second pads 166 to The outside world can improve the heat dissipation performance of the overall semiconductor package structure 1〇〇a. In addition, since the semiconductor package structure 1a has these second pads 166, the semiconductor package structure 〇〇a can pass through the second pads 166 and be electrically connected to an external circuit (not shown). Increase its applicability. 6A to 6K are cross-sectional views showing a method of fabricating a semiconductor package structure according to still another embodiment of the present invention. Referring to the figure, first, a substrate no and a two-copper layer 125a' 125b are provided. The substrate 11A has an upper surface 112 and a lower surface 丨μ with respect to the upper surface 112, and the copper layers 125a, i25b are disposed on the upper surface 112 and the lower surface 114 of the substrate 11A, respectively. Next, referring to FIG. 6B, at least the annular barrier body 120a is formed on the upper surface 112 of the substrate 110, wherein the annular resist 1 is applied to the substrate to define a receiving recess 122a. These annular hindering bodies (10) a J are formed by the method of forming the copper layer 125a. Here, the ring-shaped resistance, |2〇a beiwu is a - sealing_ring blocking body, as shown in Figure ΐβ, but not limited to this. Then, the copper layers 125a, 125b are patterned to form a first patterned circuit layer a' on the upper surface 112 of the substrate 110 and a second pattern on the lower surface ι4 of the substrate UG. The patterned circuit layer reveals the substrate. The upper surface 112 of the substrate 110 is exposed by the second patterned circuit layer 16 and the second patterned circuit layer 16 is exposed to 17 201218322 ASEK2385-1-NEW-FINAL-TW-20110217. Next, an adhesive layer 130 is formed on the upper surface 112 of the substrate 11' with reference to Fig. 6C' in which the adhesive layer 130 is located in the receiving recess 122a. Next, referring to FIG. 6D, a wafer 140 is disposed in the receiving recess 122a. The wafer 140 is fixed to the substrate u through the adhesive layer. In detail, the wafer 14 has an active surface 142 away from the upper surface U2 of the substrate n0 and a plurality of pads 144 disposed on the active surface 142. In particular, as can be seen from FIG. 6D, the annular barrier 120a of the present embodiment can limit the horizontal range of motion of the wafer 140 relative to the substrate 11', meaning that part of the sides of the wafer 140 will bear or be placed in a ring-shaped barrier. The body 120a and the substrate 11 are formed in the receiving pockets 122a. Next, referring to FIG. 6E, a first dielectric layer 15 is disposed on the upper surface 112 of the substrate 110. The first dielectric layer 15 surrounds the wafer i4 and covers the annular barrier 12a and the first The circuit layer i64a is patterned. A surface of the w-th electrical layer 150 transported away from the upper surface 112 of the substrate 11 is substantially aligned with (or below the active surface of the wafer) the active surface 142 of the wafer 140. The material of the first dielectric layer 15A is, for example, a glass-containing resin or a glass-free resin, which is, for example, an ABF resin or an ABF-like resin. When the material of the first dielectric layer 150 is a resin containing glass fiber, the uniformity and strength can be effectively improved. Next, a redistribution wiring structure 200b (see Fig. 6J) is formed on the first dielectric layer 150. In the present embodiment, the steps of forming the redistribution line structure 2〇〇b are as shown in Figs. 6F to 6J. First, referring to FIG. 6F, a second dielectric layer 210b is disposed on the first dielectric layer 150 and the active surface 142 of the wafer 140. Then, a plurality of first openings 212b exposing the interfaces 144 of the 201218322 AStK2385-l-NEW-FINAL-TW-2011〇217 exiting film are formed on the second dielectric layer 21b, and formed to v_bay a second dielectric layer 2i〇b, a first dielectric layer 15〇, a substrate 11〇 and a through hole s of the first patterned circuit layer 164b (two are schematically shown in FIG. 6F ), wherein the through holes are formed The method of S includes a laser drilling method. -8, please refer to FIG. 6G, forming a plating seed layer 225a on the first Sichuan electric layer 210b, the first openings 212b, the inner walls of the through holes s, the second patterned circuit layer 164b and the second pattern. A portion of the lower surface I" of the substrate 11A exposed by the wiring layer 164b. # Next, please refer to FIG. 6H, forming a first patterned photoresist layer 228a on a portion of the plating seed layer 225a on the second dielectric layer 210b, and forming a second patterned photoresist layer 228b in the second The patterned wiring layer 164b and the partially patterned seed layer 225a on a portion of the lower surface 114 of the substrate 110 exposed by the first patterned wiring layer 164b. The first patterned photoresist layer 228a exposes the electric money seed layer 225a partially located in the first openings 212b and on the second dielectric layer 21b. Next, referring to FIG. 61, an electroplating process is performed on the first patterned photoresist layer 228a for a φ plating mask to plate a portion of the conductive layer 22 to be exposed by the patterned photoresist layer 228a. The seed layer 225a is plated with at least one conductive via structure 16〇b (only two of the schematic layers are shown in FIG. 61). The patterned conductive layer 220 is electrically connected to the pads 144 of the wafer 140 through the openings 212b, and the conductive via structures 160b connect the patterned conductive layer 22 and the second patterned circuit layer 164b. Thereafter, the first patterned photoresist layer 228a and a portion of the plating seed layer 225a thereunder are removed to expose a portion of the first dielectric layer 210b. At the same time, the second patterned photoresist layer 228b and its partially plated seed layer 225a under 19 201218322 j 85-1 -NEW-FINAL-TW-20110217 are removed to expose the second patterned circuit layer 164b and its exposure. Part of the lower surface (1) of the substrate u〇. Then, referring to FIG. 6J, a solder resist layer 23 is formed on the patterned conductive layer 220, wherein the solder resist layer 23 covers a portion of the patterned conductive layer and a portion of the second dielectric layer 21b. In this embodiment, the anti-friction layer now has a plurality of second openings 232, and these second openings add a portion of the patterned conductive layer 220. At this point, the re-distribution line is roughly completed. . Finally, referring again to Fig. 61, a singulation process is performed along a plurality of nano lines L to form a plurality of semiconductor package structures 1a, . So far, the fabrication of the semiconductor package structure 100a has been substantially completed. Of course, referring to FIG. 6K', in order to increase the applicability of the semiconductor package structure 1a, a plurality of fresh balls 250 may be formed in the second openings 232 of the solder resist layer 230 after the singulation is performed. The portions of the patterned conductive layer 220, that is, the contacts 234, are exposed such that the solder balls 250 directly contact the patterned conductive layer 22A. That is, the semiconductor package structure loob'' can pass through the solder balls 250 and external circuits (not shown) because the present embodiment has through the second dielectric layer 210b, the first dielectric layer 150, the substrate 11 and the second The conductive circuit layer 160b of the patterned wiring layer 16牝, wherein the patterned conductive layer 220 of the redistributed wiring structure 2〇〇b is electrically connected to the pads 144 of the wafer 14〇. Therefore, the heat generated during the operation of the wafer can be The conductive semiconductor layer 220, the conductive via structures 16Bb, and the second patterned circuit layers 164b are quickly transferred to the outside, thereby improving the overall semiconductor package structure 201218322 ASEK23 85-1 -NEW-FINAL-TW -20110217 low (or semiconductor package structure 1G%,,) heat dissipation performance. In addition, t semiconductor package structure chest, (or semiconductor package structure just b") 第n some f: patterned circuit layer (10), so the semiconductor package structure a or a semiconductor package structure 〇%,,) can be electrically connected to an external circuit (not shown) through the second pattern, thereby increasing the size of the wafer when the wafer is disposed through the adhesive layer* In the upper case, the annular barrier can effectively limit the water consumption of the wafer relative to the substrate. Therefore, the alignment accuracy between the wafer and the substrate can be improved: 'The manufacturing yield of the semiconductor package structure can also be improved. 2, the portion «layer is pressed by the wafer to extend into the annular resisting limb and the notch, so that the wafer can be disposed flatly in the receiving cavity. In addition, the present invention can adopt a substrate without specific size limitation. Therefore, the device for fabricating the circuit substrate can be directly used without using the wafer-level clock, thereby reducing the cost. The present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. Those of ordinary skill in the art, in the spirit and scope of the present invention, should be able to make a few changes and the scope of the invention. The scope of protection of the invention is attached to the scope of the patent application; The sectional conductor package structure FIG. 1B is the semiconductor package structure of FIG. 1A.

AbHK2385-l-NEW-FINAL-TW-20110217 View schematic. 2A through 2C are top plan views of annular resist members of various embodiments of the present invention. 3A to 3K are cross-sectional views showing a method of fabricating a semiconductor package structure according to an embodiment of the present invention. 4A-4B are cross-sectional views showing a method of fabricating a partial semiconductor package structure in accordance with an embodiment of the present invention. 5A to 5K are cross-sectional views showing a method of fabricating a semiconductor package structure according to another embodiment of the present invention. 6A to 6K are cross-sectional views showing a method of fabricating a semiconductor package structure according to still another embodiment of the present invention. 100, 100a, i〇〇b, 100a, 100b, 100a, ', 100 [Description of main component symbols] Semiconductor package structure 110. Substrate 114: Lower surface 122a: accommodating recesses 125, 125a, 125b: copper layer 132. Attaching film 142 · Active surface 150, 152. First dielectric layer 154 ' 156 : Conductive layer 楫 162 : First pad 112 : Upper surface 120 a 〜 120 d : Annular blocking body 124 b ～ 124 d : Notch 鲁 130 : Adhesive layer 140 · Wafer 144 : pads 152 , S : through holes 160 , 160b : conductive via junction 164 : patterned circuit layer

22 S 201218322 ASEK2385-1-NEW-FINAL-TW-20110217 164a: first patterned circuit layer 164b: second patterned circuit layer 166: second pad 168: conductive pillars 200, 200a, 200a', 200b: heavy The wiring structure 210, 210a: the second dielectric layer 212, 212a: the first opening 220: the patterned conductive layer 225, 225a: the plating seed layer 228: the patterned photoresist layer 228a: the first patterned photoresist 230: Solder layer 234: Contact S1~S3: Side L: Cutting line

228b: second patterned photoresist layer 232: second opening 250: solder ball C: corner

twenty three

Claims (1)

201218322 ASEK2385-1-NEW-FINAL-TW-20110217 VII. Patent Application Range: 1. A semiconductor package structure comprising: a substrate having an upper surface; an annular barrier disposed on the upper surface of the substrate The annular barrier body and the substrate define a receiving recess; an adhesive layer disposed in the receiving recess; a wafer disposed in the receiving recess and having a distance away from the substrate An active surface of the f-plane and a plurality of interfaces disposed on the active surface, wherein the wafer is fixed to the substrate through the adhesive layer; the gate-dielectric layer is disposed on the upper surface of the substrate And a repeating wiring structure, and a repeating wiring structure, disposed on the first dielectric layer, and the =:= layer, wherein the patterned conductive layer and the wafer are further packaged: The semiconductor package structure according to Item (4), wherein the wiring is on the redistribution line structure, wherein the heavy connection is performed. And eight have at least one contact, and the solder ball is electrically connected to the contact. 3. As described in claim 2, wherein the thin circuit structure further includes: (4) Sealing I. The second dielectric layer is disposed on the first dielectric layer, the dielectric layer has a plurality of first openings, and the plurality of first openings are disposed on the pads, wherein the patterned conductive layer distribution layer And the patterned conductive layer is electrically connected to the pads through the openings of the first 24 S 201218322 AStK^85-l-NEW-FINAL-TW-2011 〇217; and the one-solder layer is disposed on The patterned conductive layer has a plurality of = i openings exposing a portion of the patterned conductive layer: = 4 out of the portion of the patterned conductive layer defines the 4. as described in the scope of the patent application; =; rr a rectangular annular barrier body, and the side or the second of the two resistances is located at least in the rectangular annular shape. 5. The adhesive layer extends into the notch as part of the application for the interception. (4) Sealing I, ·. [6] The semi-conducting layer of the semi-conducting layer as described in the application (4) is located on the "patterned circuit layer on both sides of the first dielectric layer and the "small-^ two-junction", wherein the substrate Having at least a conductive via ς = junction and the patterned circuit layer disposed on the substrate ^ the second pad is disposed on the substrate The conductive via structure on the upper surface penetrates the substrate and is connected to the pad, and the adhesive layer is filled between the first pad and the patterned circuit layer, and the annular barrier 8 As described in claim 7, the method further includes at least a conductive branch, wherein the first dielectric layer 4 is configured to form a through hole, and the conductive pillar is disposed in the through hole and is connected with "Ter 2: 25". 201218322 ASEK23 85-1 -NEW-FINAL-TW-20110217 Patterned Conductive Layer. The semiconductor package structure described in Item 7 further includes a ruthenium film attached to the joint, the rings, and the body. Widely the pattern 1 line V: divided into the first structure, and further includes the semiconductor package junction described in item 1 - the third layer: the first layer of the circuit layer and the first layer of the pattern The circuit layer is disposed on the base sound, and the first dielectric layer covers the first patterned circuit: the two-layer layer is disposed on the upper surface of the substrate opposite to the upper surface, the conductive via a structure penetrating the first substrate and connecting the patterned germanium layer. The conductive layer and the second patterned line The method for fabricating a semiconductor package structure includes: a plurality of annular resistive bodies, wherein the substrate has a shaped barrier body defining a receiving recess with the substrate; and each of the coatings forms an adhesive layer thereon Each of the receiving pockets; (9) in each of the receiving pockets, wherein each of the wafers transmits === mosquitoes on the substrate, and each of the wafers has a distance away from the base = the upper surface _-active surface and is disposed in a plurality of first dielectric layers on the active surface are disposed on the upper surface of the substrate, wherein the dielectric layer surrounds the wafers, and the first dielectric layer is away from a surface of the upper surface of the substrate The active surfaces of the wafers are substantially aligned; and S 26 201218322 85-1 -NEW-FINAL-TW-20110217 form a redistribution line structure on the first dielectric layer, wherein the redistribution line structure includes at least one The conductive layer is patterned, and the patterned conductive layer is electrically connected to the pads of the wafer. 12. The method of fabricating a semiconductor package structure according to claim 11, further comprising: after forming the redistribution line structure, forming a plurality of solder balls on a surface of the redistribution line structure, wherein the rewiring The surface of the circuit structure has a plurality of contacts, and the solder balls are electrically connected to the contacts. The method of fabricating the semiconductor package structure of claim 12, wherein the step of forming the redistribution line structure comprises: disposing at least a second dielectric layer on the first dielectric layer and the Forming, on the second active layer, a plurality of first openings exposing the pads of the plurality of pads; forming the patterned conductive layer on the second dielectric layer, wherein The patterned conductive layer is electrically connected to the pads through the first openings; and a solder resist is formed on the patterned conductive layer, wherein the solder resist has a plurality of second openings, and the plurality of openings The second opening exposes a portion of the patterned conductive layer, and a portion of the patterned conductive layer exposed by the second openings defines the contacts. The method of fabricating the semiconductor package structure of claim 13, further comprising: after forming the first openings, forming a plating seed layer on the second dielectric layer and the first openings 27 201218322 ASEK2385-1-NEW-FINAL-TW-20110217 Forming a patterned photoresist layer on the electroplated seed layer; performing an electroplating process on the patterned photoresist layer for electroplating, to electroplate 4 patterns And forming a conductive layer on a portion of the plating seed layer exposed by the patterned photoresist layer; and removing the patterned photoresist layer. The method for fabricating a semiconductor package structure according to the invention of claim 5, further comprising: forming at least one conductive via structure extending through the substrate before forming the adhesive layer in each of the receiving recesses; a first interface and a patterned circuit layer on the substrate: a surface, and a bottom surface forming at least a second interface opposite the substrate, wherein the first pad is connected to the second pad Conductive via structure; forming at least - a conductive pillar on the first pad; 逍 the adhesive layer in each of the receiving recesses (4) 'the adhesive layer is further connected to the pad, the planar barrier and the patterned circuit layer The step of forming the redistributed wiring structure in the semiconductor package structure ~ s / described in Item 15 includes: a second dielectric layer on the first dielectric layer and the wafers 28 S 201218322 ASEK2385 On the active surface of the -1 -NEW-FIN AL-T W-20110217; forming a plurality of the pads exposing the wafers and the first opening of the conductive pillars on the second dielectric layer; forming The patterned conductive layer is on the second dielectric layer, wherein The patterned conductive layer is electrically connected to the pads and the conductive pillars through the first openings; and a solder resist layer is formed on the patterned conductive layer, wherein the solder resist layer has a plurality of second openings, and The second openings expose a portion of the patterned conductive layer, and a portion of the patterned conductive layer exposed by the second openings defines the contacts. The method of fabricating a semiconductor package structure according to claim 16, wherein after forming the first openings, forming a plating seed layer on the second dielectric layer and the first openings; Forming a patterned photoresist layer on the electro-mineral seed layer; performing an electroplating process on the patterned photoresist layer as a plating mask to electroplate the patterned conductive layer exposed by the patterned photoresist layer Part of the electrowinning seed layer; and removing the patterned photoresist layer and a portion of the electroplated seed layer exposed by the patterned conductive layer. 29