TWI490986B - Semiconductor package structure and manufacturing method thereof - Google Patents

Description

Semiconductor package structure and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor package structure and a method of fabricating the same.

The purpose of the chip package is to protect the exposed wafer, reduce the density of the wafer contacts, and provide good heat dissipation from the wafer. A common packaging method is that the wafer is mounted to a loading board by wire bonding or flip chip bonding so that the contacts on the wafer can be electrically connected to the package carrier. Therefore, the contact distribution of the wafer can be reconfigured by the package carrier to conform to the junction distribution of the external components of the next level.

The present invention provides a semiconductor package structure for packaging a wafer.

The present invention provides a method of fabricating a semiconductor package structure for fabricating the semiconductor package structure described above.

The invention provides a semiconductor package structure comprising a substrate, an annular barrier, an adhesive layer, a wafer, a first dielectric layer and a redistribution line structure. The substrate has an upper surface. The annular barrier is disposed on the upper surface of the substrate, wherein the annular barrier defines a receiving recess with the substrate. The adhesive layer is disposed in the receiving pocket. The wafer is disposed in the receiving cavity, and has an active surface away from the upper surface of the substrate and a plurality of pads disposed on the active surface, wherein the wafer is fixed on the substrate through the adhesive layer. The first dielectric layer is disposed on the upper surface of the substrate and surrounds the wafer. The redistribution line structure is disposed on the first (di) dielectric layer and includes at least one patterned conductive layer, wherein the patterned conductive layer is electrically connected to the pads of the wafer.

The present invention further provides a method of fabricating a semiconductor package structure, wherein the fabrication method comprises the following steps. A substrate and a plurality of annular barriers are provided. The substrate has an upper surface, and the annular barrier is formed on the upper surface, and each of the annular barrier defines a receiving recess with the substrate. An adhesive layer is formed in each of the receiving pockets. Configuring a wafer in each of the accommodating pockets, wherein each of the wafers is fixed to the substrate through the adhesive layer, and each of the wafers has an active surface away from the upper surface of the substrate and a plurality of pads disposed on the active surface . Configuring a first dielectric layer on the upper surface of the substrate, wherein the first dielectric layer surrounds the wafer, and a surface of the first dielectric layer away from the upper surface of the substrate is substantially aligned with (or below) the active surface of the wafer Chip active surface). Forming a redistribution line structure on the first (di) dielectric layer, wherein the redistribution line structure comprises at least one patterned conductive layer, and the patterned conductive layer is electrically connected to the pads of the wafer.

Based on the above, when the wafer is disposed on the substrate through the adhesive layer, the present invention can effectively limit the horizontal range of motion of the wafer relative to the substrate by the annular barrier. Therefore, the alignment accuracy between the wafer and the substrate can be improved, and the process yield of the semiconductor package structure can also be improved.

The above described features and advantages of the present invention will be more apparent from the following description.

1A is a cross-sectional view showing a semiconductor package structure according to an embodiment of the present invention. 1B is a top plan view of the annular barrier of the semiconductor package structure of FIG. 1A. Referring to FIG. 1A and FIG. 1B , in the embodiment, the semiconductor package structure 100 includes a substrate 110 , an annular barrier 120 a , a copper layer 125 , an adhesive layer 130 , a wafer 140 , and a first dielectric layer . 152 and a repeating wiring structure 200.

The substrate 110 has an upper surface 112. The annular barrier 120a is disposed on the upper surface 112 of the substrate 110. The annular barrier 120a and the substrate 110 define a receiving recess 122a. The annular barrier 120a is substantially a closed frame-shaped annular barrier. , as shown in Figure 1B. The copper layer 125 is disposed on the lower surface 114 of the substrate 110 relative to the upper surface 112. The adhesive layer 130 is disposed on the upper surface 112 of the substrate 110, and a portion of the adhesive layer 130 is located in the receiving recess 122a. The wafer 140 is fixed to the substrate 110 through the adhesive layer 130. The wafer 140 has an active surface 142 away from the upper surface 112 of the substrate 110 and a plurality of pads 144 disposed on the active surface 142.

The first dielectric layer 152 is disposed on the upper surface 112 of the substrate 110 and surrounds the wafer 140. In this embodiment, the semiconductor package structure 100 further includes two conductive layers 154, 156, wherein the conductive layers 154, 156 are respectively located on opposite side surfaces of the first dielectric layer 152, and the conductive layers 154, 156 and A dielectric layer 152 can be viewed as a high structural layer. Wherein, the pad structure layer is away from a surface of the upper surface 112 of the substrate 110 (that is, the surface of the conductive layer 154 away from the first dielectric layer 152) is lower than or substantially cut with the active surface 142 of the wafer 140, and the pad The high structural layer can be fixed to the upper surface 112 of the substrate 110 through the adhesive layer 130. In another embodiment, the pad structure layer may also be only a dielectric layer, wherein the material of the dielectric layer is, for example, a glass fiber-containing resin or a glass fiber-free resin, such as ABF. Resin or ABF-like resin. Wherein, when the material of the dielectric layer is a resin containing glass fiber, the strength and uniformity of the package can be effectively improved.

The redistribution line structure 200 is disposed on the conductive layer 154. In this embodiment, the redistribution circuit structure 200 includes at least one second dielectric layer 210 (only one is shown in FIG. 1A ), at least one patterned conductive layer 220 (only one is shown in FIG. 1A ), and a solder resist. Layer 230. The second dielectric layer 210 is disposed on the conductive layer 154 on the first dielectric layer 152 and on the wafer 140. The second dielectric layer 210 has a plurality of first openings 212, and the first openings 212 are respectively exposed. These pads 144 of the wafer 140. The patterned conductive layer 220 is disposed on the second dielectric layer 210 , wherein the patterned conductive layer 220 is electrically connected to the pads 144 of the wafer 140 through the first openings 212 . The solder resist layer 230 is disposed on the patterned conductive layer 220 and has a plurality of second openings 232, wherein the second openings 232 expose a portion of the patterned conductive layer 220, and portions of the second openings 232 are partially patterned. The conductive layer 220 defines a plurality of contacts 234 for use as contacts for electrical connection to an external circuit (not shown).

It should be noted that the present invention does not limit the form of the redistribution wiring structure 200, although the redistribution wiring structure 200 mentioned herein is embodied by a second dielectric layer 210 and a patterned conductive layer 220. And a laminated structure formed by a solder resist layer 230. However, in other embodiments, the redistribution wiring structure 200 may also be a stacked structure composed of a solder resist layer 230 and a plurality of alternately stacked second dielectric layers 210 and patterned conductive layers 220, wherein the second dielectric layers The electrically conductive layer 210 and the patterned conductive layer 220 are located between the solder resist layer 230 and the substrate 110, and the patterned conductive layer 220 is transparent to a plurality of conductive connection structures (not shown), such as conductive vias, and electrically connected to each other. connection. Therefore, the redistribution circuit structure 200 illustrated in FIG. 1A is merely illustrative and not limited thereto.

In the present embodiment, the substrate 110 is, for example, a resin substrate containing glass fibers. The material of the annular barrier 120a may include metal, solder or resin, wherein the metal is, for example, copper. Furthermore, the height of the annular barrier 120a may be between 20 microns and 100 microns, preferably between 30 microns and 70 microns, and the width of the annular barrier 120a may be between 100 microns and Between 3000 microns. In addition, although the semiconductor package structure 100 mentioned herein has the copper layer 125, in other embodiments, the semiconductor package structure 100 may not have the copper layer 125. In short, the semiconductor package structure 100 of the embodiment is merely illustrative and not limited thereto.

When the wafer 140 is disposed on the substrate 110 through the adhesive layer 130, the annular barrier 120a can effectively limit the horizontal range of motion of the wafer 140 relative to the substrate 110. Therefore, the alignment accuracy between the wafer 140 and the substrate 110 can be improved.

However, the present invention does not limit the structural design of the annular barrier 120a, although the annular barrier 120a referred to herein is embodied as a closed frame-shaped annular barrier, but other known positions can be achieved. The structural design of the effect still belongs to the technical solution that can be adopted by the present invention without departing from the scope of the present invention.

For example, referring to FIG. 2A, the annular blocking body 120b is, for example, a rectangular annular blocking body having at least one notch 124b (four notches 124b is illustrated in FIG. 2A), wherein the notches 124b are respectively located in a rectangular annular block. The four sides of the body S1.

Alternatively, referring to FIG. 2B, the annular barrier 120c is, for example, a rectangular annular barrier having at least one notch 124c (eight notches 124c is illustrated in FIG. 2B), wherein each side of the rectangular annular barrier S2 has two notches 124c.

Alternatively, referring to FIG. 2C, the annular barrier 120d is, for example, a rectangular annular barrier having at least one notch 124d (eight notches 124d in FIG. 2C), wherein the notches 124d of the rectangular annular barrier are located. The four sides S3 and the four corners C of the rectangular annular barrier.

When the annular barrier 120b (or 120c, 120d) of the present embodiment is a rectangular annular barrier having the notches 124b (or 124c, 124d), the partial adhesive layer 130 is pressed by the wafer 140 to extend to the gap. 124b (or 124c, 124d) is such that the wafer 140 can be disposed flatly within the receiving pocket 122a, meaning that the active surface 142 of the wafer 140 can be maintained horizontal.

A method of fabricating a semiconductor package structure 100a will be described in detail below with reference to FIGS. 3A through 3K in another embodiment.

3A to 3K are cross-sectional views showing a method of fabricating a semiconductor package structure according to an embodiment of the present invention. Referring to FIG. 3A, first, a substrate 110, a plurality of annular barriers 120a (only one is shown in FIG. 3A), and a copper layer 125 are provided. The substrate 110 has an upper surface 112 and a lower surface 114 opposite to the upper surface 112, and an annular barrier 120a is formed on the upper surface 112 of the substrate 110, and a copper layer 125 is disposed on the lower surface 114 of the substrate 110. The annular barrier 120a and the substrate 110 define a receiving recess 122a. Here, the annular barrier 120a is substantially a closed annular barrier as shown in FIG. 1B.

Of course, in other embodiments, referring to FIG. 2A to FIG. 2C, the annular blocking body 120b, 120b, 120c may also be a rectangular annular blocking body having at least one notch 124b-124d, wherein the notches 124b-124d are located at least The sides S1, S2, S3 or the corner C of the annular barriers 120b, 120b, 120c are not limited herein.

In this embodiment, the shape of the substrate 110 is, for example, a rectangle, that is, the substrate 110 is not a wafer having a specific size limitation, wherein the substrate 110 is, for example, a resin substrate containing glass fibers. The material of the annular barrier 120a may include metal, solder or resin, wherein the metal is, for example, copper. In addition, in the embodiment, the height of the annular barrier 120a may be between 20 micrometers and 100 micrometers, preferably between 30 micrometers and 70 micrometers, and the width of the annular barrier body 120a may be Between 100 microns and 3000 microns.

Next, referring to FIG. 3B, an adhesive layer 130 is formed on the upper surface 112 of the substrate 110, and a portion of the adhesive layer 130 is located in the receiving recess 122a. Further, the material of the adhesive layer 130 is, for example, epoxy.

It must be noted herein that the present invention does not limit the location of the adhesive layer 130, although the adhesive layer 130 referred to herein is embodied to be located on the upper surface 112 of the substrate 110, that is, within the receiving pocket 122a and subsequent The location at which the first dielectric layer 152 is to be placed. However, in other embodiments not shown, the adhesive layer 130 may be disposed only in the receiving pocket 122a. Therefore, the position of the adhesive layer 130 illustrated in FIG. 3B is merely illustrative and not limited thereto.

Next, referring to FIG. 3C , a wafer 140 is disposed in the receiving cavity 122 a , wherein the wafer 140 is fixed on the substrate 110 through the adhesive layer 130 . In detail, the wafer 140 has an active surface 142 away from the upper surface 112 of the substrate 110 and a plurality of pads 144 disposed on the active surface 142. In particular, as can be seen from FIG. 3C, the annular barrier 120a of the present embodiment can limit the horizontal range of motion of the wafer 140 relative to the substrate 110, meaning that portions of the sides of the wafer 140 will bear or be located in the annular barrier. 120a and the substrate 110 are formed in the receiving pocket 122a.

When the annular barrier 120b (or 120c, 120d) of the present embodiment is a rectangular annular barrier having these notches 124b (or 124c, 124d) (see FIGS. 2A to 2C), the partial adhesive layer 130 may extend to the notch. In the 124b (or 124c, 124d), the wafer 140 can be placed flat in the receiving pocket 122a. Thus, the active face 142 of the wafer 140 can be maintained horizontal relative to the substrate 110, which facilitates subsequent processing.

Next, referring to FIG. 3D, a first dielectric layer 152 is disposed on the upper surface 112 of the substrate 110, wherein the first dielectric layer 152 surrounds the wafer 140, and the first dielectric layer 152 is away from the upper surface 112 of the substrate 110. A surface is substantially aligned with (or below the active surface of the wafer) the active surface 142 of the wafer 140. Then, conductive layers 154 and 156 are respectively disposed on opposite side surfaces of the first dielectric layer 152, wherein the conductive layers 154 and 156 and the first dielectric layer 152 can be regarded as a padded structure layer, and the pad structure is high. The layer may be fixed to the upper surface 112 of the substrate 110 through the adhesive layer 130. In another embodiment, referring to FIG. 4A, the pad structure layer may also be only a first dielectric layer 150, wherein the material of the first dielectric layer 150 is, for example, a glass fiber-containing resin or a fiberglass-free fiber. A resin which is, for example, an ABF resin or an ABF-like resin. When the material of the first dielectric layer 150 is a resin containing glass fiber, the strength and uniformity of the package can be effectively improved.

Next, a redistribution wiring structure 200a (see FIG. 3J) is formed on the conductive layer 154. In the present embodiment, the steps of forming the redistribution line structure 200a are as shown in FIGS. 3E to 3I. First, referring to FIG. 3E, a second dielectric layer 210 is disposed on the pad structure layer (ie, the conductive layer 154 on the first dielectric layer 152) and the active surface 142 of the wafer 140. Of course, in FIG. 4B, the second dielectric layer 210 can be disposed directly on the dielectric layer 150 and the active surface 142 of the wafer 140. Then, a plurality of first openings 212 exposing the pads 144 of the wafer 140 are formed on the second dielectric layer 210, wherein the first openings 212 are formed by, for example, laser drilling or exposure into holes (" Photo via"), and the material of the second dielectric layer 210 is, for example, resin coated copper, ABF resin, ABF-like resin, photosensitive resin or Prepreg resin.

Next, referring to FIG. 3F, a plating seed layer 225 is formed on the second dielectric layer 210 and in the first openings 212.

Next, referring to FIG. 3G, a patterned photoresist layer 228 is formed on the plating seed layer 225, wherein the patterned photoresist layer 228 exposes electroplated seeds partially located in the first openings 212 and on the second dielectric layer 210. Layer 225.

Next, referring to FIG. 3H, the patterned photoresist layer 228 is subjected to an electroplating process for plating a pattern to electrically plate a patterned conductive layer 220 on a portion of the plating seed layer 225 exposed by the patterned photoresist layer 228. The patterned conductive layer 220 is electrically connected to the pads 144 of the wafer 140 through the first openings 212. Thereafter, the patterned photoresist layer 228 and a portion of the plating seed layer 225 thereunder are removed to expose a portion of the second dielectric layer 210.

Then, referring to FIG. 3I, a solder resist layer 230 is formed on the patterned conductive layer 220, wherein the solder resist layer 230 covers the partially patterned conductive layer 220 and a portion of the second dielectric layer 210. In the present embodiment, the solder resist layer 230 has a plurality of second openings 232, and the second openings 232 expose a portion of the patterned conductive layer 220. So far, the production of the redistribution line structure 200a is substantially completed.

Finally, please refer to FIG. 3I and FIG. 3J simultaneously, and a singulation process is performed along the plurality of dicing lines L to form a plurality of semiconductor package structures 100a (only one is shown in FIG. 3J). So far, the fabrication of the semiconductor package structure 100a has been substantially completed.

Of course, referring to FIG. 3K, in order to increase the applicability of the semiconductor package structure 100a, a plurality of solder balls 250 may be separately formed on the exposed portions of the second openings 232 of the solder resist layer 230 before the singulation process. These contacts 234 are patterned on the conductive layer 220 such that the solder balls 250 directly contact the patterned conductive layer 220. Then, a singulation process is performed to form a plurality of semiconductor package structures 100b (only one is shown in FIG. 3K). In addition, although the semiconductor package structures 100a, 100b mentioned herein have the copper layer 125 on the lower surface 114 of the substrate 110, in other embodiments, the semiconductor package structures 100a, 100b may not have the copper layer 125, The copper layer 125 can be removed after the singulation process to expose the lower surface 114 of the substrate. In short, the semiconductor package structures 100a and 100b of the present embodiment are merely illustrative and not limited thereto.

Further, the application of the method of fabricating the semiconductor package structure will be described below using two embodiments. It is to be noted that the following embodiments use the same reference numerals and the same elements in the foregoing embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

5A to 5K are cross-sectional views showing a method of fabricating a semiconductor package structure according to another embodiment of the present invention. Referring to FIG. 5A, first, a substrate 110 and two copper layers 125a, 125b are provided. The substrate 110 has an upper surface 112 and a lower surface 114 opposite to the upper surface 112, and the copper layers 125a, 125b are disposed on the upper surface 112 and the lower surface 114 of the substrate 110, respectively.

Next, referring to FIG. 5B, at least one conductive via structure 160 (only two are schematically shown in FIG. 5B) is formed through the substrate 110, wherein the conductive via structures 160 connect the upper surface 112 and the lower surface 114 of the substrate 110. Next, at least one first pad 162 (only two are schematically shown in FIG. 5B) and a patterned circuit layer 164 on the upper surface 112 of the substrate 110 are formed, and at least one second pad 166 is formed (FIG. 5B only Two) are schematically shown on the lower surface 114 of the substrate 110.

In this embodiment, the conductive via structures 160 are formed by mechanical drilling and plated through holes (PTH). The first pads 162 and the second pads 166 can be formed by patterning the copper layers 125a and 125b, respectively. In addition, the first pads 162 and the second pads 166 are respectively connected to the conductive via structures 160.

Next, referring to FIG. 5B, at least one annular barrier 120a is formed on the upper surface 112 of the substrate 110. The annular barrier 120a and the substrate 110 define a receiving recess 122a. These annular barriers 120a can be formed by patterning the copper layer 125a. Here, the annular barrier 120a is substantially a closed annular barrier, as shown in FIG. 1B, but is not limited thereto.

Next, referring to FIG. 5C, at least one conductive pillar 168 (only two are schematically shown in FIG. 5C) is formed on the first pads 162, and the conductive pillars 168 are made of copper, for example. In this embodiment, the conductive pillars 168 can be formed by forming a plating mask by lithography and by electroplating.

Next, referring to FIG. 5D, an adhesive layer 130 is formed on the upper surface 112 of the substrate 110, and a portion of the adhesive layer 130 is located in the receiving recess 122a. More specifically, the adhesive layer 130 is located in the receiving recess 122a and the position of the first dielectric layer 152 shown in FIG. 5E, and the adhesive layer 130 is further filled in the first pad 162 and the ring. Between the barrier body 120a and the patterned wiring layer 164. Next, a wafer 140 is disposed in the receiving cavity 122a. The wafer 140 is fixed on the substrate 110 through the adhesive layer 130. The wafer 140 has an active surface 142 away from the upper surface 112 of the substrate 110 and is disposed on the active surface. A plurality of pads 144 on 142. In particular, as can be seen from FIG. 5D, the annular barrier 120a of the present embodiment can limit the horizontal range of motion of the wafer 140 relative to the substrate 110, meaning that portions of the sides of the wafer 140 will bear or be located in the annular barrier. 120a and the substrate 110 are formed in the receiving pocket 122a.

Next, referring to FIG. 5E, a first dielectric layer 152 surrounding the wafer 140 and two conductive layers 154, 156 are disposed on the upper surface 112 of the substrate 110, wherein the conductive layers 154, 156 are respectively located on the first dielectric layer 152. On the opposite sides of the surface, the conductive layers 154, 156 and the first dielectric layer 152 can be regarded as a pad structure layer, and the pad structure layer can be fixed on the upper surface 112 of the substrate 110 through the adhesive layer 130. . Before the pad structure layer is disposed on the substrate 110, at least one through hole 152a (only two are schematically shown in FIG. 5E) penetrating through the first dielectric layer 152 and the conductive layers 154, 156 is formed.

Then, referring to FIG. 5F, the conductive pillars 168 are respectively disposed in the through holes 152a, and the padded structural layer is further fixed to the partial adhesive layer 130, the partial first pads 162, and the ring through an attaching film 132. The barrier 120a and the patterned wiring layer 164 are formed.

Next, a redistribution wiring structure 200a' (see Fig. 5J) is formed on the conductive layer 154. In the present embodiment, the steps of forming the redistribution line structure 200a' are as shown in Figs. 5F to 5J. First, referring to FIG. 5F, a second dielectric layer 210a is disposed on the active structure layer 142 of the pad 140 on the pad structure layer (ie, the conductive layer 154 on the first dielectric layer 152). Then, a plurality of the pads 144 exposing the wafer 140 and the first openings 212a of the conductive pillars 168 are formed on the second dielectric layer 210a.

Next, referring to FIG. 5G, a plating seed layer 225 is formed on the second dielectric layer 210a and in the first openings 212a.

Next, referring to FIG. 5H, a patterned photoresist layer 228 is formed on the plating seed layer 225, wherein the patterned photoresist layer 228 exposes electroplated seeds partially located in the first openings 212a and on the second dielectric layer 210a. Layer 225.

Next, referring to FIG. 5I, an electroplating process is performed by patterning the photoresist layer 228 for a plating mask to plate a patterned conductive layer 220 on a portion of the plating seed layer 225 exposed by the patterned photoresist layer 228. The patterned conductive layer 220 is electrically connected to the pads 144 of the wafer 140 and the conductive pillars 168 through the plating seed layer 225 in the first openings 212a. Thereafter, the patterned photoresist layer 228 and a portion of the plating seed layer 225 thereunder are removed to expose a portion of the second dielectric layer 210a.

Then, referring to FIG. 5J, a solder resist layer 230 is formed on the patterned conductive layer 220, wherein the solder resist layer 230 covers the partially patterned conductive layer 220 and a portion of the second dielectric layer 210a. In the present embodiment, the solder resist layer 230 has a plurality of second openings 232, and the second openings 232 expose a portion of the patterned conductive layer 220. Thus far, the fabrication of the redistribution line structure 200a' is substantially completed. Finally, referring again to FIG. 5J, a singulation process is performed along the plurality of dicing lines L to form a plurality of semiconductor package structures 100a'. Thus far, the fabrication of the semiconductor package structure 100a' has been substantially completed.

Of course, referring to FIG. 5K, in order to increase the applicability of the semiconductor package structure 100a', after the singulation process is performed, a plurality of solder balls 250 may be respectively formed on the exposed portions of the second openings 232 of the solder resist layer 230. These contacts 234 are patterned on the conductive layer 220 such that the solder balls 250 directly contact the patterned conductive layer 220. That is, the semiconductor package structure 100b' can be electrically connected to an external circuit (not shown) through the solder balls 250.

Since the present embodiment has the conductive via structure 160 penetrating the substrate 110 and the conductive pillars 168 disposed in the via holes 152a of the pad pattern layer (that is, the first dielectric layer 152 and the conductive layers 154, 156), wherein The patterned conductive layer 220 of the redistribution wiring structure 200a' is electrically connected to the pads 144 of the wafer 140 and the conductive pillars 168, and the conductive pillars 168 pass through the first pads 162 and the conductive via structures 160 and the first The two pads 166 are electrically connected.

Therefore, the heat generated by the operation of the wafer 140 can be transmitted to the outside through the patterned conductive layer 220 of the metal material, the conductive pillars 168, the first pads 162, the conductive via structures 160, and the second pads 166. The heat dissipation performance of the overall semiconductor package structure 100a' can be improved. In addition, since the semiconductor package structure 100a' has the second pads 166, the semiconductor package structures 100a' can be electrically connected to external circuits (not shown) through the second pads 166, thereby increasing the applicability.

6A-6K illustrate, in cross section, a method of fabricating a semiconductor package structure according to still another embodiment of the present invention. Referring to FIG. 6A, first, a substrate 110 and two copper layers 125a, 125b are provided. The substrate 110 has an upper surface 112 and a lower surface 114 opposite to the upper surface 112, and the copper layers 125a, 125b are disposed on the upper surface 112 and the lower surface 114 of the substrate 110, respectively.

Next, referring to FIG. 6B, at least one annular barrier 120a is formed on the upper surface 112 of the substrate 110, wherein the annular barrier 120a and the substrate 110 define a receiving recess 122a. These annular barriers 120a can be formed by patterning the copper layer 125a. Here, the annular barrier 120a is substantially a closed annular barrier, as shown in FIG. 1B, but is not limited thereto. Then, the copper layers 125a, 125b are patterned to form a first patterned wiring layer 164a on the upper surface 112 of the substrate 110, and a second patterned wiring layer 164b is formed on the lower surface 114 of the substrate 110, wherein the first layer The patterned wiring layer 164a exposes a portion of the upper surface 112 of the substrate 110, while the second patterned wiring layer 164b exposes a portion of the lower surface 114 of the substrate 110.

Next, referring to FIG. 6C, an adhesive layer 130 is formed on the upper surface 112 of the substrate 110, wherein the adhesive layer 130 is located in the receiving recess 122a.

Next, referring to FIG. 6D, a wafer 140 is disposed in the receiving cavity 122a, wherein the wafer 140 is fixed on the substrate 110 through the adhesive layer 130. In detail, the wafer 140 has an active surface 142 away from the upper surface 112 of the substrate 110 and a plurality of pads 144 disposed on the active surface 142. In particular, as can be seen from FIG. 6D, the annular barrier 120a of the present embodiment can limit the horizontal range of motion of the wafer 140 relative to the substrate 110, meaning that a portion of the sides of the wafer 140 will bear or be located in the annular barrier. 120a and the substrate 110 are formed in the receiving pocket 122a.

Next, referring to FIG. 6E, a first dielectric layer 150 is disposed on the upper surface 112 of the substrate 110, wherein the first dielectric layer 150 surrounds the wafer 140 and covers the annular barrier 120a and the first patterned wiring layer 164a. A surface of the first dielectric layer 150 away from the upper surface 112 of the substrate 110 is substantially aligned with (or below the active surface of the wafer) the active surface 142 of the wafer 140. Here, the material of the first dielectric layer 150 is, for example, a glass fiber-containing resin or a glass fiber-free resin, which is, for example, an ABF resin or an ABF-like resin. When the material of the first dielectric layer 150 is a resin containing glass fiber, the uniformity and strength can be effectively improved.

Next, a redistribution wiring structure 200b (see FIG. 6J) is formed on the first dielectric layer 150. In the present embodiment, the steps of forming the redistribution line structure 200b are as shown in FIGS. 6F to 6J. First, referring to FIG. 6F, a second dielectric layer 210b is disposed on the first dielectric layer 150 and the active surface 142 of the wafer 140. Then, a plurality of first openings 212b exposing the pads 144 of the wafer 140 are formed on the second dielectric layer 210b, and at least one through the second dielectric layer 210b, the first dielectric layer 150, and the substrate 110 are formed. The through holes S of the second patterned circuit layer 164b (two are schematically shown in FIG. 6F), wherein the method of forming the through holes S includes a laser drilling method.

Next, referring to FIG. 6G, a plating seed layer 225a is formed on the second dielectric layer 210b, the first openings 212b, the inner walls of the through holes S, the second patterned circuit layer 164b, and the second patterning. A portion of the lower surface 114 of the substrate 110 exposed by the wiring layer 164b.

Next, referring to FIG. 6H, a first patterned photoresist layer 228a is formed on a portion of the plating seed layer 225a on the second dielectric layer 210b, and a second patterned photoresist layer 228b is formed on the second pattern. The circuit layer 164b and the portion of the lower plating surface 225a of the portion of the lower surface 114 of the substrate 110 exposed by the second patterned wiring layer 164b are exposed. The first patterned photoresist layer 228a exposes a plating seed layer 225a partially located in the first openings 212b and on the second dielectric layer 210b.

Next, referring to FIG. 6I, an electroplating process is performed on the first patterned photoresist layer 228a as a plating mask to plate a portion of the electroplated seed exposed by the patterned conductive layer 220 on the first patterned photoresist layer 228a. The layer 225a and the at least one conductive via structure 160b (only two of which are schematically shown in FIG. 6I) are plated in the through holes S. The patterned conductive layer 220 is electrically connected to the pads 144 of the wafer 140 through the first openings 212b, and the conductive via structures 160b connect the patterned conductive layer 220 and the second patterned circuit layer 164b. Thereafter, the first patterned photoresist layer 228a and a portion of the plating seed layer 225a thereunder are removed to expose a portion of the second dielectric layer 210b. At the same time, the second patterned photoresist layer 228b and a portion of the plating seed layer 225a thereunder are removed to expose the second patterned wiring layer 164b and a portion of the lower surface 114 of the substrate 110 from which it is exposed.

Then, referring to FIG. 6J, a solder resist layer 230 is formed on the patterned conductive layer 220, wherein the solder resist layer 230 covers the partially patterned conductive layer 220 and a portion of the second dielectric layer 210b. In the present embodiment, the solder resist layer 230 has a plurality of second openings 232, and the second openings 232 expose a portion of the patterned conductive layer 220. So far, the fabrication of the redistribution line structure 200b is substantially completed.

Finally, referring again to FIG. 6J, a singulation process is performed along the plurality of dicing lines L to form a plurality of semiconductor package structures 100a". Thus, fabrication of the semiconductor package structure 100a" is substantially completed.

Of course, referring to FIG. 6K, in order to increase the applicability of the semiconductor package structure 100a", a plurality of solder balls 250 may be formed after the singulation process to expose a portion of the patterns of the second openings 232 of the solder resist layer 230. The conductive layer 220, that is, the contacts 234, is such that the solder balls 250 directly contact the patterned conductive layer 220. That is, the semiconductor package structure 100b" can pass through the solder balls 250 and external circuits (not shown ) Electrical connection.

Since the embodiment has a conductive via structure 160b penetrating through the second dielectric layer 210b, the first dielectric layer 150, the substrate 110, and the second patterned wiring layer 164b, wherein the patterned conductive layer 220 of the redistributed wiring structure 200b is electrically These pads 144 of the wafer 140 are connected. Therefore, the heat generated by the operation of the wafer 140 can be quickly transmitted to the outside through the patterned conductive layer 220 of the metal material, the conductive via structures 160b, and the second patterned wiring layers 164b, thereby improving the overall semiconductor package structure 100a" (or semiconductor package structure 100b") heat dissipation performance. In addition, since the semiconductor package structure 100a" (or the semiconductor package structure 100b") has these second patterned wiring layers 164b, the semiconductor package structure 100a" (or the semiconductor package structure 100b") can pass through the second patterned wiring layers 164b. It is electrically connected to an external circuit (not shown), thereby increasing its applicability.

In summary, when the wafer is disposed on the substrate through the adhesive layer, the present invention can effectively limit the horizontal range of motion of the wafer relative to the substrate by the annular barrier. Therefore, the alignment accuracy between the wafer and the substrate can be improved, and the process yield of the semiconductor package structure can also be improved. In addition, the present invention allows a portion of the adhesive layer to be extruded by the wafer to extend into the gap of the annular barrier so that the wafer can be disposed flatly within the receiving pocket. In addition, the present invention can employ a substrate without a specific size limitation, so that a device for generally manufacturing a circuit substrate can be directly used without using a wafer level device, thereby reducing the cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 100a, 100b, 100a', 100b', 100a", 100b". . . Semiconductor package structure

110. . . Substrate

112. . . Upper surface

114. . . lower surface

120a～120d. . . Annular barrier

122a. . . Accommodating pocket

124b ~ 124d. . . gap

125, 125a, 125b. . . Copper layer

130. . . Adhesive layer

132. . . Attachment film

140. . . Wafer

142. . . Active surface

144. . . Pad

150, 152. . . First dielectric layer

152, S. . . Through hole

154, 156. . . Conductive layer

160, 160b. . . Conductive via structure

162. . . First pad

164. . . Patterned circuit layer

164a‧‧‧First patterned circuit layer

164b‧‧‧Second patterned circuit Floor

166‧‧‧second mat

168‧‧‧conductive column

200, 200a, 200a’, 200b‧‧‧ redistributed line structure

210, 210a‧‧‧Second dielectric layer

212, 212a‧‧‧ first opening

220‧‧‧ patterned conductive layer

225, 225a‧‧‧ plating seed layer

228‧‧‧ patterned photoresist layer

228a‧‧‧First patterned photoresist Floor

228b‧‧‧Second patterned photoresist layer

230‧‧‧ solder mask

232‧‧‧second opening

234‧‧‧Contacts

250‧‧‧ solder balls

S1~S3‧‧‧ side

C‧‧‧ corner

L‧‧‧ cutting line

1A is a cross-sectional view showing a semiconductor package structure according to an embodiment of the present invention.

1B is a top plan view of the annular barrier of the semiconductor package structure of FIG. 1A.

2A-2C are top plan views of an annular barrier of various embodiments of the present invention.

3A to 3K are cross-sectional views showing a method of fabricating a semiconductor package structure according to an embodiment of the present invention.

4A-4B are cross-sectional views showing a method of fabricating a partial semiconductor package structure according to an embodiment of the present invention.

5A to 5K are cross-sectional views showing a method of fabricating a semiconductor package structure according to another embodiment of the present invention.

6A-6K illustrate, in cross section, a method of fabricating a semiconductor package structure according to still another embodiment of the present invention.

100. . . Semiconductor package structure

110. . . Substrate

112. . . Upper surface

114. . . lower surface

120a. . . Annular barrier

122a. . . Accommodating pocket

125. . . Copper layer

130. . . Adhesive layer

140. . . Wafer

142. . . Active surface

144. . . Pad

152. . . First dielectric layer

154, 156. . . Conductive layer

200. . . Redistributed line structure

210. . . Second dielectric layer

212. . . First opening

220. . . Patterned conductive layer

230. . . Solder mask

232. . . Second opening

234. . . contact

Claims (19)

A semiconductor package structure comprising: a substrate having an upper surface; an annular barrier disposed on the upper surface of the substrate, wherein the annular barrier defines a receiving recess and the ring The material of the blocking body is a metal; an adhesive layer is disposed in the receiving cavity; a wafer is disposed in the receiving cavity, has an active surface away from the upper surface of the substrate, and is disposed on the active surface a plurality of pads on the surface, wherein the wafer is fixed on the substrate through the adhesive layer; a first dielectric layer disposed on the upper surface of the substrate and surrounding the wafer, wherein the first dielectric layer a glass-containing resin; and a redistribution wiring structure disposed on the first dielectric layer and including at least one patterned conductive layer, wherein the patterned conductive layer is electrically connected to the pads of the wafer, wherein The thickness of the annular barrier is less than the thickness of the wafer. The semiconductor package structure of claim 1, further comprising: at least one solder ball disposed on the redistribution line structure, wherein a surface of the redistribution line structure has at least one contact, the solder ball and the solder ball The contacts are electrically connected. The semiconductor package structure of claim 2, wherein the redistribution circuit structure further comprises: at least one second dielectric layer disposed on the first dielectric layer and the wafer, the second dielectric layer Having a plurality of first openings, and the first openings respectively expose the pads of the wafer, wherein the patterned conductive layer is disposed on the second dielectric layer, and the patterned conductive layer transmits the first openings An opening electrically connected to the pads; And a solder resist layer disposed on the patterned conductive layer, having a plurality of second openings, wherein the second opening exposes a portion of the patterned conductive layer, and a portion of the second opening exposed by the patterned conductive The layer defines the contact. The semiconductor package structure of claim 1, wherein the annular barrier is a rectangular annular barrier, and the rectangular annular barrier has at least one notch, and the cutout is at least located in the rectangular annular barrier The side or corner of the body. The semiconductor package structure of claim 4, wherein a portion of the adhesive layer extends into the gap. The semiconductor package structure of claim 1, further comprising two conductive layers respectively located on opposite side surfaces of the first dielectric layer. The semiconductor package structure of claim 1, further comprising at least one first pad, a patterned circuit layer, and at least one second pad, wherein the substrate has at least one conductive via structure, the first The pad and the patterned circuit layer are disposed on the upper surface of the substrate, and the second pad is disposed on a lower surface of the substrate relative to the upper surface, the conductive via structure penetrating the substrate and connecting the first surface a pad and the second pad, and the adhesive layer is filled between the first pad, the annular barrier, and the patterned circuit layer. The semiconductor package structure of claim 7, further comprising at least one conductive pillar, wherein the first dielectric layer has at least a uniform hole, and the conductive pillar is disposed in the through hole and connected to the first pad And the patterned conductive layer. The semiconductor package structure of claim 7, further comprising an attaching film disposed on a portion of the adhesive layer, a portion of the first pad, the annular barrier, and the patterned circuit layer. The semiconductor package structure of claim 1, further comprising a conductive via structure, a first patterned circuit layer and a second patterned circuit layer, wherein the first patterned circuit layer is disposed on the substrate The first dielectric layer covers the first patterned circuit layer on the upper surface, and the second patterned circuit layer is disposed on a lower surface of the substrate opposite to the upper surface, the conductive via structure runs through the The first dielectric layer and the substrate are connected to the patterned conductive layer and the second patterned circuit layer. The semiconductor package structure of claim 1, further comprising a conductive layer on a surface of the first dielectric layer adjacent to the upper surface of the substrate, the conductive layer being in contact with the annular barrier . A method for fabricating a semiconductor package structure, comprising: providing a substrate and a plurality of annular barriers, wherein the substrate has an upper surface, the annular barriers are formed on the upper surface, and each of the annular barriers The substrate defines a receiving recess, and the annular blocking body is made of metal; an adhesive layer is formed in each of the receiving recesses; and a wafer is disposed in each of the receiving recesses, wherein each of the wafers The substrate is fixed on the substrate through the adhesive layer, and each of the wafers has an active surface away from the upper surface of the substrate and a plurality of pads disposed on the active surface, wherein the annular barrier has a thickness smaller than the a thickness of the wafer; a first dielectric layer disposed on the upper surface of the substrate, wherein the first dielectric layer surrounds the wafers, and the first dielectric layer is away from a surface of the upper surface of the substrate The active surfaces of the wafers are substantially aligned, the first dielectric layer contains a glass fiber resin, and a redistribution wiring structure is formed on the first dielectric layer, wherein the redistribution wiring structure includes at least one pattern Conductive layer, the pattern The conductive layer and the wafer, Some pads are electrically connected. The method for fabricating a semiconductor package structure according to claim 12, further comprising: after forming the redistribution line structure, forming a plurality of solder balls on a surface of the redistribution line structure, wherein the redistribution line structure The surface has a plurality of contacts, and the solder balls are electrically connected to the contacts. The method of fabricating a semiconductor package structure according to claim 13 , wherein the step of forming the redistribution line structure comprises: disposing at least one second dielectric layer on the first dielectric layer and the plurality of wafers Forming a plurality of first openings exposing the pads of the wafers on the second dielectric layer; forming the patterned conductive layer on the second dielectric layer, wherein the patterning The conductive layer is electrically connected to the pads through the first openings; and a solder resist layer is formed on the patterned conductive layer, wherein the solder resist layer has a plurality of second openings, and the second openings are exposed A portion of the patterned conductive layer is formed, and a portion of the patterned conductive layer exposed by the second openings defines the contacts. The method of fabricating the semiconductor package structure of claim 14, further comprising: after forming the first openings, forming a plating seed layer on the second dielectric layer and the first openings; Forming a patterned photoresist layer on the electroplated seed layer; performing an electroplating process on the patterned photoresist layer as a plating mask to electroplate the portion of the patterned conductive layer exposed by the patterned photoresist layer Electroplating species On the sub-layer; and removing the patterned photoresist layer. The method for fabricating a semiconductor package structure according to claim 12, further comprising: forming at least one conductive via structure extending through the substrate before forming the adhesive layer in each of the receiving recesses; forming at least one a first pad and a patterned circuit layer on the upper surface of the substrate, and forming at least one second pad on a lower surface of the substrate opposite to the upper surface, wherein the first pad and the second a pad is connected to the conductive via structure; at least one conductive pillar is formed on the first pad; and when the adhesive layer is formed in each of the receiving recesses, the adhesive layer is further filled in the first pad, the Between the annular barrier and the patterned wiring layer; and before the first dielectric layer is disposed on the upper surface of the substrate, forming at least one through hole penetrating the first dielectric layer, wherein the conductive pillar The first dielectric layer is disposed on a portion of the adhesive layer, a portion of the first pad, the annular barrier, and the patterned circuit layer through an attaching film. The method for fabricating a semiconductor package structure according to claim 16, wherein the step of forming the redistribution line structure comprises: disposing at least one second dielectric layer on the first dielectric layer and the plurality of wafers Forming a plurality of the pads exposing the wafers and the first openings of the conductive pillars on the second dielectric layer; forming the patterned conductive layer on the second dielectric layer, The patterned conductive layer is electrically connected to the pads and the conductive pillars through the first openings; And forming a solder resist layer on the patterned conductive layer, wherein the solder resist layer has a plurality of second openings, and the second openings expose a portion of the patterned conductive layer, and the second openings are exposed A portion of the patterned conductive layer defines the contacts. The method of fabricating a semiconductor package structure according to claim 17, wherein after forming the first openings, forming a plating seed layer on the second dielectric layer and the first openings; forming a And patterning the photoresist layer on the plating seed layer; performing an electroplating process on the patterned photoresist layer as a plating mask to electroplate the portion of the patterned conductive layer exposed by the patterned photoresist layer And removing a portion of the patterned seed layer exposed by the patterned photoresist layer and the patterned conductive layer. The method of fabricating a semiconductor package structure according to claim 12, wherein the first dielectric layer is disposed on a surface of the upper surface of the substrate, and the conductive layer is in contact with the annular barrier.