CN220526904U - Electronic device - Google Patents

Abstract

Embodiments of the present application disclose an electronic device comprising: a chip having a first conductive contact; the first redistribution line layer is provided with a first conductive through hole which is directly and electrically connected with the first conductive contact piece, and the first conductive through hole is a tapered through hole which gradually becomes smaller towards the chip; and the structural reinforcement is positioned on the same side of the first redistribution layer as the chip and is used for reinforcing the integral rigidity of the electronic device. The technical scheme that the prior chip is externally connected through the silicon interposer and the silicon through hole (TSV) is replaced by the technical scheme, and at least the technical problem caused by the fact that the silicon interposer and the TSV are used as the structure of the chip for externally connecting is solved: interfacial delamination occurs due to CTE mismatch between the silicon fracture, TSV, and silicon interposer. The electronic device has stable structure and good performance.

Description

Electronic device

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to an electronic device.

Background

Fig. 1 is a schematic cross-sectional view of a prior art electronic device 10. Referring to fig. 1, the die 12 is externally connected through silicon vias (TSVs, through Silicon Via) 22 in a silicon interposer (Si interposer) 14, for example, in the design of a 2.5DIC/3DIC package, the silicon interposer 14 serves as a connection between the die 12 and the substrate 16, wherein the silicon interposer 14 has TSVs 22 for signal transmission. However, the TSV 22 is prone to silicon cracking (crack) in the silicon interposer 14, and the interface between the TSV 22 and the silicon interposer 14 delaminates due to Coefficient of Thermal Expansion (CTE) mismatch issues. In addition, the micro bumps 24 under the chip 12 or the bumps 26 under the silicon interposer 14 are typically connected outward by solder 28 as electrical connection components, and cold bonding, cracking, bridging, etc. often occur at the bond sites due to CTE mismatch issues. Therefore, the failure rate of the electronic device 10 and the cost of the electronic device 10 are very high. In addition, in the design of the 2.5DIC/3DIC package, a structure with high strength is required, and thus the thickness H of the entire electronic device 10 and the thickness H of the silicon interposer 14 are required to be large. However, during fabrication, each time the thermal process is performed, the thick structure and CTE mismatch is prone to thermal stress, resulting in silicon cracking (crack) in the silicon interposer 14 and delamination problems at the interface between the TSV 22 and the silicon interposer 14.

Disclosure of Invention

Aiming at the problem that when a chip is externally connected through a TSV in a silicon intermediate layer, the TSV is easy to cause silicon breakage in the silicon intermediate layer and CTE mismatch between the TSV and the silicon intermediate layer to cause interface layering, the embodiment of the application provides an electronic device, the prior technical scheme that the chip is externally connected through the silicon intermediate layer and the TSV is replaced, at least the technical problem brought by the fact that the silicon intermediate layer and the TSV are used as a chip externally connected structure can be solved, and the electronic device is stable in structure and good in performance.

According to one aspect of the present application, there is provided an electronic device comprising: a chip having a first conductive contact; the first redistribution line layer is provided with a first conductive through hole which is directly and electrically connected with the first conductive contact piece, and the first conductive through hole is a tapered through hole which gradually becomes smaller towards the chip; and the structural reinforcement is positioned on the same side of the first redistribution layer as the chip and is used for reinforcing the integral rigidity of the electronic device.

In some embodiments, the chip has an interconnect structure layer including a first dielectric layer and conductive pillars in the first dielectric layer, the conductive pillars constituting first conductive contacts.

In some embodiments, the structural reinforcement has an opening, and the chip is disposed within the opening.

In some embodiments, the sidewalls of the opening are sloped surfaces that face the chip.

In some embodiments, the sloped surface has a roughness greater than a roughness of a top surface of the structural reinforcement, and the first redistribution line layer is located on a bottom surface of the structural reinforcement.

In some embodiments, the electronic device further includes a first sealing layer that encapsulates the chip.

In some embodiments, the electronic device further includes a second redistribution layer, the second redistribution layer and the chip being located on opposite sides of the first redistribution layer, respectively, the second redistribution layer being disposed below the first redistribution layer and electrically connected to the first redistribution layer and having a distance from the first redistribution layer.

In some embodiments, the electronic device further includes a second sealing layer disposed within the space, the first sealing layer contacting the second sealing layer.

In some embodiments, the first sealant layer also encapsulates the structural reinforcement, a side of the first sealant layer aligned with a side of the structural reinforcement and a side of the first redistribution layer.

In some embodiments, the first sealing layer has portions disposed within the spacing such that the first sealing layer encapsulates the structural reinforcement and the first redistribution line layer.

The technical effects of the utility model include: the prior technical scheme that the chip is externally connected through the silicon interposer and the TSV is replaced, and at least the technical problem caused by the fact that the silicon interposer and the TSV are used as the structure of the chip external connection can be solved: the electronic device has stable structure and good performance.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art. It is noted that the various components are not drawn to scale and are for illustrative purposes only, according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a schematic cross-sectional view of a prior art electronic device.

Fig. 2 is a schematic cross-sectional view of an electronic device and an enlarged view of region a according to one embodiment of the present application.

Fig. 3-8 and 10 are schematic cross-sectional views of various embodiments of an electronic device.

Fig. 9A-9Y are schematic cross-sectional views at various steps of forming an electronic device according to an embodiment of the present application.

Fig. 11A and 11B show a square panel level (PNL) carrier and a circular Wafer Level (WL) carrier, respectively.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application are within the scope of the protection of the present application.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the utility model. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present utility model may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, embodiments and features of embodiments in this application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 2 is a schematic cross-sectional view of an electronic device 100 and an enlarged view of region a according to one embodiment of the present application. Referring to fig. 2, the electronic device 100 of the present application includes a chip 112, a first redistribution layer 114, and a structural stiffener 116, wherein the chip 112 has a first conductive contact 122; the first redistribution line layer 114 has a first conductive via 124 in direct electrical connection with the first conductive contact 122, the first conductive via 124 being a tapered via tapering toward the chip 112; the structural reinforcement 116 is located on the same side of the first redistribution layer 114 as the chip 112, and the structural reinforcement 116 is used to strengthen the overall rigidity of the electronic device 100. In the electronic device 100 provided by the utility model, the chip 112 is not externally connected through the silicon interposer and the TSV in the silicon interposer, so that at least the technical problems caused by the fact that the silicon interposer and the TSV serve as a structure for externally connecting the chip 112 can be avoided: the TSV is prone to fracture of the silicon in the silicon interposer, interfacial delamination due to CTE mismatch between the TSV and the silicon interposer, and the electronic device 100 of the present utility model is structurally stable and has good performance.

It will be appreciated that other structures shown in fig. 2 may be provided according to the specific requirements of the electronic device 100, and that other structures shown in fig. 2 and the relative relationships between the structures are not intended to be limiting of the present application.

Referring to the enlarged view of region a of fig. 2, in some embodiments, the maximum width BVS of the first conductive contact 122 is less than 20 μm; the pitch BVP between two adjacent first conductive vias 124 is less than 30 μm; the first conductive contact 122 and the first conductive via 124 that are directly electrically connected are offset from each other, and the central axis of the first conductive contact 122 is offset from the central axis of the first conductive via 124 by a distance HBS of less than 1mm.

In some embodiments, the structural stiffener 116 may be a silicon interposer, and there are no conductive via structures in the portion of the structural stiffener 116 adjacent to the chip 112. The chips 112 are externally connected through the first conductive vias 124 in the first redistribution layer 114 without being externally connected through TSVs, and the structural reinforcement 116 may support the first redistribution layer 114 without functioning as a structure for externally connecting the chips 112, and without a conductive via structure in a portion of the structural reinforcement 116 adjacent to the chips 112, reducing the number of TSVs, which is advantageous in reducing the thickness of the electronic device 100, and the electronic device 100 has excellent electrical properties. In some embodiments, the thickness ST of the structural reinforcement 116 may be between 30 μm and 200 μm.

In some embodiments, a seed layer 125 may be provided between the structural reinforcement 116 and the first redistribution line layer 114. The seed layer 125 enhances adhesion between the first redistribution line layer 114 of the structural reinforcement 116.

In some embodiments, the chip 112 may have an interconnect structure layer 130, and the interconnect structure layer 130 may include a first dielectric layer 131 and conductive pillars 122 'located in the first dielectric layer 131, the conductive pillars 122' constituting the first conductive contacts 122. In some embodiments, the first redistribution layer 114 has a second dielectric layer 132 surrounding the first conductive via 124, the first dielectric layer 131 directly bonded to the second dielectric layer 132 and the first conductive contact 122 directly bonded to the first conductive via 124, such that the interconnect structure layer 130 is directly hybrid bonded to the first redistribution layer 114. The chip 112 is externally connected through the first conductive via 124 in the first redistribution layer 114, which is realized by directly mixing and bonding the interconnection structure layer 130 of the chip 112 and the first redistribution layer 114, instead of the previous silicon interposer and the TSVs therein, so that the number of the TSVs is reduced by the mixed bonding connection mode, and the technical problems caused by the TSVs, such as silicon cracking and interface layering of the TSVs and the silicon interposer, are avoided. In addition, since the chip 112 is externally connected without using the silicon interposer and the TSVs therein, the micro bump under the chip 112 is not required to be used as an electrical connection component and connected to the TSVs by means of solder, and the electronic device 100 of the present utility model does not have the technical problems that the micro bump is cold-connected, broken, bridged, etc. at the soldered portion. Compared with the technical scheme of externally connecting the chip 112 through the micro bump and the TSV in the silicon interposer, the technical scheme of the present utility model has the advantages that the interconnection structure layer 130 of the chip 112 is directly mixed and bonded with the first redistribution layer 114, the first conductive via 124 of the first redistribution layer 114 directly electrically connected with the first conductive contact 122 of the chip 112, that is, the chip 112 is directly externally connected through the first conductive via 124 in the first redistribution layer 114, and has a shorter conductive path.

In some embodiments, the first redistribution line layer 114 may further have a third dielectric layer 133, where the third dielectric layer 133 is located on an opposite side of the second dielectric layer 132 from the first dielectric layer 131, and the third dielectric layer 133 includes a second conductive via 126 therein, and the second conductive via 126 has the same shape as the first conductive via 124. The first redistribution layer 114 is shown in fig. 2 as having 3 dielectric layers, the number shown being for simplicity and ease of description only and not intended to be limiting in number.

With continued reference to fig. 2, in some embodiments, the structural reinforcement 116 has an opening 140, the chip 112 is disposed within the opening 140, and the spacing GE between the chip 112 and the outermost edge of the opening 140 may be in the range of between 10 μm and 200 μm. The placement of the chip 112 within the opening 140 is more advantageous in reducing the overall thickness of the electronic device 100. In the cross-sectional schematic view shown in fig. 2, the maximum width CVS of the opening 140 may be several tens of micrometers to several hundreds of micrometers, and the width CHS of the chip 112 may be several tens of micrometers to several hundreds of micrometers, and the maximum width CVS of the opening 140 is 1.2 to 10 times the width CHS of the chip 112. In some embodiments, the sidewall 141' of the opening 140 may be an inclined surface 141, the inclined surface 141 facing the chip 112. In some embodiments, the inclined angle θ of the inclined surface 141 may be in a range between 5 ° and 85 °. In some embodiments, the roughness of the sloped surface 141 is greater than the roughness of the top surface 1161 of the structural reinforcement 116, and the first redistribution layer 114 is located on the bottom surface 1162 of the structural reinforcement 116.

In some embodiments, the electronic device 100 may further include a first sealing layer 151, the first sealing layer 151 encasing the chip 112.

In some embodiments, the first sealing layer 151 also encapsulates the structural reinforcement 116, with a side 1513 of the first sealing layer 151 aligned with a side 1163 of the structural reinforcement 116 and a side 1143 of the first redistribution layer 114.

In some embodiments, the electronic device 100 may further include a second redistribution layer 118, where the second redistribution layer 118 and the chip 112 are located on opposite sides of the first redistribution layer 114, respectively, and the second redistribution layer 118 is disposed below the first redistribution layer 114 and electrically connected to the first redistribution layer 114 and has a space 110 with the first redistribution layer 114.

In some embodiments, the first redistribution layer 114 and the second redistribution layer 118 are connected together by direct bonding of a third conductive line 137 lowermost of the first redistribution layer 114 and a bond pad 138 disposed on the second redistribution layer 118, i.e., the first redistribution layer 114 and the second redistribution layer 118 are connected together by metal-to-metal direct bonding. The absence of solder connection between the third conductive line 137 and the bonding pad 138 provides a shorter electrical path between the assembly 1110 of the structural reinforcement 116, the chip 112, the first sealing layer 151, and the first redistribution layer 114 and the second redistribution layer 118, which is advantageous for the thinning of the electronic device 100, and the electronic device 100 has excellent electrical properties because the absence of solder connection does not have technical problems such as cold joining, cracking, or bridging at the soldered joint.

In some embodiments, electronic device 100 may also include a second sealing layer 152, second sealing layer 152 disposed within gap 110. In some embodiments, second sealing layer 152 encapsulates bottom surface 1142 and side surface 1143 of first redistribution layer 114.

Fig. 3 is a schematic cross-sectional view of an electronic device 200 according to another embodiment of the present application. Referring to fig. 3, similar to the electronic device 100 shown in fig. 2, except that the first sealing layer 151 is located in the opening 140 in fig. 3, the bottom surface 1512 of the first sealing layer 151 directly contacts the first redistribution layer 114, and the top surface 1511 of the first sealing layer 151 is curved.

Fig. 4 is a schematic cross-sectional view of an electronic device 300 according to another embodiment of the present application. Referring to fig. 4, similar to the electronic device 200 shown in fig. 3, except that the first sealing layer 151 in fig. 4 further extends and also covers the top surface 1161 of the structural reinforcement 116.

Fig. 5 is a schematic cross-sectional view of an electronic device 400 according to another embodiment of the present application. Referring to fig. 5, similar to the electronic device 100 shown in fig. 2, except that the first sealing layer 151 in fig. 5 is further extended to contact the second sealing layer 152. The first sealant layer 151 encapsulates the sides 1163 of the structural reinforcement 116. The first sealing layer 151 may also contact the top surface 1181 of the second redistribution layer 118, and the side 1513 of the first sealing layer 151 is aligned with the side 1183 of the second redistribution layer 118.

Fig. 6 is a schematic cross-sectional view of an electronic device 500 according to another embodiment of the present application. Referring to fig. 6, similar to the electronic device 100 shown in fig. 2, except that the electronic device 500 in fig. 6 does not include the second sealing layer 152 (see fig. 2) disposed within the space 110, the first sealing layer 151 in fig. 6 has a portion disposed within the space 110 such that the first sealing layer 151 encapsulates the structural stiffener 116 and the first redistribution layer 114.

Fig. 7 is a schematic cross-sectional view of an electronic device 600 according to another embodiment of the present application. Referring to fig. 7, an electronic device 100 similar to that shown in fig. 2 differs in that side 1143 of first redistribution line layer 114 is aligned with side 1183 of second redistribution line layer 118 in fig. 7.

Fig. 8 is a schematic cross-sectional view of an electronic device 700 according to another embodiment of the present application. Referring to fig. 8, the electronic device 700 in fig. 8 is similar to the electronic device 100 in fig. 2 except that the electronic device 700 further includes solder 1103, and the third conductive lines 137 and the bonding pads 138 are connected together by solder 1103.

Embodiments of the present application also provide methods of forming electronic devices. Fig. 9A-9Y are schematic cross-sectional views at various steps of forming an electronic device 100 according to an embodiment of the present application.

Referring to fig. 9A, a structural reinforcement 116 is provided, wherein the structural reinforcement 116 has not been etched yet, and the structural reinforcement 116 serves as a support to support the first redistribution layer 114 (see fig. 9Q) formed later. Metal particles 1250 are deposited on the structural reinforcement 116 to form a seed layer 125 (see fig. 9B).

Referring to fig. 9B, non-metallic particles 1320 are deposited on the seed layer 125 to form a second dielectric layer 132 (see fig. 9C).

Referring to fig. 9C, a first mask layer 612 is formed over the second dielectric layer 132, and the first mask layer 612 is exposed (as indicated by an arrow in the figure). In some embodiments, the material of the first mask layer 612 may employ Photoresist (PR). In some embodiments, the first mask layer 612 is formed using a lamination process.

Referring to fig. 9D, a plurality of openings 601 are formed in the first mask layer 612 through a photolithography process, and the second dielectric layer 132 under the first mask layer 612 is further etched through the openings 601 using an etchant 701 to form openings 602 (see fig. 9E) in the second dielectric layer 132, exposing the seed layer 125. In some embodiments, the first mask layer 612 is developed to complete the lithography of the first mask layer 612.

Referring to fig. 9E, a first conductive via 124 is formed on the seed layer 125 within the opening 602, for example, the first conductive via 124 may be formed by a plating/electroplating process. In some embodiments, the first conductive via 124 is a tapered via that tapers toward the structural stiffener 116.

Referring to fig. 9F, a seed layer 127 is coated on the first conductive via 124 and the second dielectric layer 132 surrounding the first conductive via 124, for example, by PVD process.

Referring to fig. 9G, a second mask layer 613 is formed over the seed layer 127, and the second mask layer 613 is exposed (as indicated by an arrow in the figure). In some embodiments, the material of the second mask layer 613 may employ Photoresist (PR). In some embodiments, the second mask layer 613 is formed using a lamination process.

Referring to fig. 9H, a plurality of openings 603 are formed in the second mask layer 613 through a photolithography process. A metal layer 191 is then formed over seed layer 127 within opening 603, for example, metal layer 191 may be formed by an electroplating process.

Referring to fig. 9I, the second mask layer 613 (see fig. 9H) and the seed layer 127 (see fig. 9H) under the second mask layer 613 are removed by an etching process. The remaining seed layer 127 and metal layer 191 form a first conductive line 135 electrically connected to the first conductive via 124.

Referring to fig. 9J, a third dielectric layer 133 is formed over the first conductive line 135 and the second dielectric layer 132, and the third dielectric layer 133 is exposed (as indicated by an arrow in the drawing). In some embodiments, the material of the third dielectric layer 133 may be Polyamide (PA). In some embodiments, the third dielectric layer 133 is formed using a lamination process.

Referring to fig. 9K, a plurality of openings 604 exposing the first conductive lines 135 are formed in the third dielectric layer 133 using a photolithography process. The seed layer 128 is covered over the third dielectric layer 133 and within the opening 604 of the third dielectric layer 133. The seed layer 128 may be formed by a PVD process.

Referring to fig. 9L, a third mask layer 614 is formed over the seed layer 128 and within the opening 604, and the third mask layer 614 is exposed (as indicated by the arrow in the figure). In some embodiments, the material of the third mask layer 614 may employ Photoresist (PR). In some embodiments, the third mask layer 614 is formed using a lamination process.

Referring to fig. 9M, a plurality of openings 605 are formed in the third mask layer 614 through a photolithography process. A metal layer 192 is then formed on the seed layer 128 within the opening 605, for example, the metal layer 192 may be formed by an electroplating process.

Referring to fig. 9N, the third mask layer 614 (see fig. 9M) and the seed layer 128 (see fig. 9M) located under the third mask layer 614 are removed by an etching process. The remaining seed layer 128 and metal layer 192 form the second conductive via 126 and the second conductive line 136 through the third dielectric layer 133 and connect the first conductive line 135, wherein the seed layer 128 and metal layer 192 located on the third dielectric layer 133 form the second conductive line 136 and the seed layer 128 and metal layer 192 located in the third dielectric layer form the second conductive via 126.

Referring to fig. 9O, a fourth dielectric layer 134 is formed over the second conductive line 136 and the third dielectric layer 133, and the fourth dielectric layer 134 is exposed (as shown by an arrow in the drawing). In some embodiments, the material of the fourth dielectric layer 134 may be Polyamide (PA). In some embodiments, the fourth dielectric layer 134 is formed using a lamination process.

Subsequently, additional dielectric layers and conductive vias and conductive lines may be formed on the third dielectric layer 133 in a manner described with reference to fig. 9J through 9N. As shown in fig. 9P, a fourth dielectric layer 134 and third conductive via 129 and third conductive line 137 are formed on the third dielectric layer 133. The second dielectric layer 132, the third dielectric layer 133, the fourth dielectric layer 134, the first conductive via 124, the first conductive line 135, the second conductive via 126, the second conductive line 136, the third conductive via 129, and the third conductive line 137 are formed to constitute the first redistribution layer 114.

Referring to fig. 9Q, the structural reinforcement 116 and the first redistribution line layer 114 are flipped upside down, a fourth mask layer 615 is formed over the structural reinforcement 116, and the fourth mask layer 615 is exposed (as indicated by an arrow in the figure). In some embodiments, the material of the fourth mask layer 615 may employ Photoresist (PR). In some embodiments, the fourth mask layer 615 is formed using a lamination process.

Referring to fig. 9R, a plurality of openings 606 are formed in the fourth mask layer 615 through a photolithography process. The structural reinforcement 116 is then etched further to form openings 140 in the structural reinforcement 116 (see fig. 9S), for example, the structural reinforcement 116 may be etched with an etchant 702.

Referring to fig. 9S, the seed layer 125 exposed by the opening 140 is removed by an etching process using an etchant 703. The seed layer 125 can protect the first conductive via 124 during etching of the structural stiffener 116 shown in fig. 9R.

Referring to fig. 9T, the chip 112 is placed into the opening 140 of the structural stiffener 116 through a bonding process such that the chip 112 is bonded to the first redistribution layer 114.

Referring to fig. 9U, the second chip 112 is placed into the opening 140 of the structural stiffener 116 by a bonding process such that the second chip 112 is also bonded to the first redistribution layer 114. 2 chips 112 are shown in fig. 9U, the number in the illustration being for simplicity and ease of description only and not intended to be limiting in number. The two chips 112 may be identical or different and are not intended to limit the kinds of chips 112.

Referring to fig. 9V, the first sealing layer 151 is filled, and the first sealing layer 151 covers the chip 112 to fix and protect the chip 112. The first sealing layer 151 may be a molding compound. After filling the first encapsulation layer 151, the structural reinforcement 116, the chip 112, the first encapsulation layer 151, and the first redistribution layer 114 constitute an assembly 1110.

Referring to fig. 9W, the assembly 1110 is bonded to the second redistribution layer 118, wherein the lowermost third conductive line 137 of the assembly 1110 is electrically connected together by direct bonding with a bond pad 138 disposed on the second redistribution layer 118. The assembly 1110 may also be joined to a substrate (not shown).

Referring to fig. 9X, electrical connections 194 are formed on bond pads 193 disposed below second redistribution layer 118, and then a protective process is performed to fill second sealing layer 152, such as a molding compound, in space 110 between first redistribution layer 114 and second redistribution layer 118 to support assembly 1110 and protect third conductive lines 137 and bond pads 138.

Referring to fig. 9Y, a dicing process is performed on the structure after the protection process shown in fig. 9X is performed to form the electronic device 100.

In the step shown in fig. 9V, after the first sealing layer 151 is filled to cover the chip 112, the top surface 1511 of the first sealing layer 151 is formed to be a plane.

In the step shown in fig. 9V, the first sealing layer 151 may be partially encapsulated in the opening 140, and the top surface 1511 of the first sealing layer 151 formed is curved (see fig. 3), and the first sealing layer 151 is filled only in the opening 140 to cover the chip 112, and finally the electronic device 200 shown in fig. 3 is obtained.

In the step shown in fig. 9V, the first sealing layer 151 may be integrally encapsulated in the opening 140, and the top surface 1511 of the formed first sealing layer 151 is curved (see fig. 4), and the first sealing layer 151 not only encapsulates the chip 112 in the opening 140, but also extends further to encapsulate the top surface 1161 of the stiffener 116, resulting in the electronic device 300 shown in fig. 4.

In some embodiments, the structural reinforcement 116, the chip 112, and the first redistribution layer 114 are first bonded to the second redistribution layer 118, and after filling the second sealing layer 152 in the space 110 between the first redistribution layer 114 and the second redistribution layer 118, the first sealing layer 151 is refilled, resulting in the electronic device 400 as shown in fig. 5.

In some embodiments, the structural stiffener 116, the chip 112, and the first redistribution layer 114 are first bonded to the second redistribution layer 118, but the second sealing layer 152 is not filled in the space 110 between the first redistribution layer 114 and the second redistribution layer 118, but the first sealing layer 151 is directly filled, the first sealing layer 151 covers the chip 112 and the first sealing layer 151 has a portion disposed in the space 110, and the first sealing layer 151 covers both the structural stiffener 116 and the first redistribution layer 114, ultimately resulting in the electronic device 500 as shown in fig. 6.

Referring to fig. 9W, the bonding of the chip-scale assembly 1110 to the second redistribution layer 118 is shown. Referring to fig. 7, a Wafer Level (WL) or panel level (PNL) structural stiffener 116, a first redistribution layer 114, and a second redistribution layer 118 may be bonded together, then an opening 140 is formed in the structural stiffener 116, a chip 112 is placed in the opening 140, such that the chip 112 is bonded to the first redistribution layer 114, then a first sealing layer 151 is refilled to cover the chip 112, and finally a dicing process is performed, finally the electronic device 600 as shown in fig. 7 is obtained.

Fig. 10 is a schematic cross-sectional view of an electronic device 800 according to another embodiment of the present application. In the embodiment shown in fig. 10, a third sealing layer 153 is further included, and the third sealing layer 153 further coats the first sealing layer 151 and the second sealing layer 152.

Referring to fig. 2, in some embodiments, any one or more of the first sealing layer 151, the second sealing layer 152, the dielectric layer in the second redistribution layer 118, and the dielectric layer in the first redistribution layer 114 may be a non-metallic material, which is Polyimide (PI), epoxy, an ajinomotobald-up film (ABF), polypropylene (PP), or/and acrylic, or the like. In some embodiments, the material of the first dielectric layer 131 and/or the second dielectric layer 132 may be an organic substance, for example, polyimide (PI), epoxy (epoxy), acrylic, and an ajinomotobux-up film (ABF), and a molding compound; and/or inorganic, e.g., oxides (such as SiOx, taOx), nitrides (such as SiNx), glass, silicon, ceramic, etc. In some embodiments, any one or more of first sealing layer 151, second sealing layer 152, dielectric layer in second redistribution layer 118, dielectric layer in first redistribution layer 114, and/or first dielectric layer 131 may employ an organic photosensitive material and/or a non-photosensitive liquid and/or dry film material.

In some embodiments, the material of any one or more of the bond pad 138, the first conductive contact 122, the seed layer 125, the conductive vias and conductive lines in the first redistribution layer 114, the conductive vias and conductive lines in the second redistribution layer 118 may be Cu, au, ag, al, pd, pt, ni, an alloy thereof, a combination thereof, or the like. The material of the electrical connector 194 may be a solder alloy and/or an anisotropic conductive paste (anisotropic conductive paste, ACP) or an anisotropic conductive film (anisotropic conductive film, ACF).

In some embodiments, the bond pads 138, the first conductive contacts 122, the seed layer 125, the conductive vias and conductive lines in the first redistribution layer 114, the conductive vias and conductive lines in the second redistribution layer 118, and/or the electrical connections 194 may be formed using a physical vapor deposition (Physical Vapor Deposition, PVD), electroplating, electroless plating, printing and/or potting, and the like.

Fig. 11A and 11B illustrate a square panel level (PNL) carrier 900 and a circular Wafer Level (WL) carrier 902, respectively, in some embodiments, a plurality of chips 112 of the present application may be arranged on the PNL carrier 900 or WL carrier 902, and then the plurality of chips 112 are transferred together onto the first redistribution layer 114 to form the electronic devices of the present application in bulk.

As can be seen from the above, the chip in the electronic device of the present utility model is not externally connected through the silicon interposer and the TSV in the silicon interposer, so that at least the technical problems caused by the structure of the silicon interposer and the TSV as the external connection of the chip can be avoided: the TSVs are easy to cause silicon fracture in the silicon medium layer, and interface delamination is caused by CTE mismatch between the TSVs and the silicon medium layer. The electronic device of the utility model is also connected to the TSV by the solder without taking the micro-bump below the chip as an electric connection part, and the technical problems of cold joint, cracking, bridging and the like of the micro-bump at the welding position are avoided. The chip in the electronic device is externally connected through the conductive through holes in the redistribution line layer, and the interconnection structure layer of the chip is directly mixed and jointed with the redistribution line layer, so that the electronic device has a shorter conductive path and excellent electrical performance. The electronic device reduces the number of TSVs connected with the chip and connected externally, and is beneficial to thinning the thickness of the electronic device.

The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but rather is intended to cover any and all modifications, equivalents, alternatives, and improvements within the spirit and principles of the present application.

Claims (10)

1. An electronic device, comprising:

a chip having a first conductive contact;

a first redistribution line layer having a first conductive via in direct electrical connection with the first conductive contact, the first conductive via being a tapered via tapering toward the chip,

and the structural reinforcement is positioned on the same side of the first redistribution layer as the chip and is used for reinforcing the integral rigidity of the electronic device.

2. The electronic device of claim 1, wherein the chip has an interconnect structure layer comprising a first dielectric layer and conductive pillars in the first dielectric layer, the conductive pillars constituting the first conductive contacts.

3. The electronic device of claim 1, wherein the structural reinforcement has an opening, the die being disposed within the opening.

4. The electronic device of claim 3, wherein the side walls of the opening are sloped surfaces, the sloped surfaces facing the chip.

5. The electronic device of claim 4, wherein the sloped surface has a roughness greater than a roughness of a top surface of the structural reinforcement, and wherein the first redistribution line layer is located on a bottom surface of the structural reinforcement.

6. The electronic device of claim 3, further comprising a first sealing layer, the first sealing layer encapsulating the chip.

7. The electronic device of claim 6, further comprising a second redistribution layer located on opposite sides of the first redistribution layer from the chip, the second redistribution layer being disposed below the first redistribution layer and electrically connecting the first redistribution layer and having a spacing from the first redistribution layer.

8. The electronic device of claim 7, further comprising a second sealing layer disposed within the space, the first sealing layer contacting the second sealing layer.

9. The electronic device of claim 6, wherein the first sealing layer also encapsulates the structural reinforcement, a side of the first sealing layer being aligned with a side of the structural reinforcement and a side of the first redistribution layer.

10. The electronic device of claim 7, wherein the first sealing layer has a portion disposed within the space such that the first sealing layer encapsulates the structural reinforcement and the first redistribution layer.