CN220525978U - Battery voltage acquisition device and battery management system - Google Patents

Abstract

The present disclosure provides a battery voltage acquisition device and a battery management system. The battery voltage acquisition device includes: the sampling switches are respectively connected to the positive electrode end and the negative electrode end of the ith battery cell, i is more than or equal to 1, the sampling switch connected with the positive electrode end is used for collecting the positive electrode end voltage of the ith battery cell, and the sampling switch connected with the negative electrode end is used for collecting the negative electrode end voltage of the ith battery cell; and the first end of the operational amplifier is connected with the sampling switch connected with the voltage of the positive electrode terminal, the second end of the operational amplifier is connected with the sampling switch connected with the voltage of the negative electrode terminal, and the output end of the operational amplifier is used for outputting the voltage related to the voltage of the ith battery cell.

Description

Battery voltage acquisition device and battery management system

Technical Field

The present disclosure relates to a battery voltage acquisition device and a battery management system.

Background

During use of rechargeable batteries, the state of the battery needs to be monitored, and one important monitoring index is the voltage of each battery. The use state of the battery pack is evaluated by collecting the voltage of each battery, and the like.

During the voltage acquisition process of each battery, the voltage of each battery can be sampled through a sampling switch. In the current battery voltage acquisition device, a sampling switch and an operational amplifier are generally arranged for each battery. In the battery voltage detection device disclosed in japanese patent publication JP2018017621a, for example, an operational amplifier is provided for each battery. Although with the development of chip integration technology, more devices may be integrated on one chip. However, the increase of the operational amplifier also causes an increase in chip area, a complication of a circuit, and the like. In addition, in the case of using one operational amplifier, the design of the sampling switch circuit is complicated, and in the case of requiring disconnection, substantial disconnection or the like cannot be achieved.

Disclosure of Invention

In order to solve one of the above technical problems, the present disclosure provides a battery voltage acquisition device and a battery management system.

According to one aspect of the present disclosure, there is provided a battery voltage acquisition device for acquiring voltages of respective battery cells of a battery pack, including: the sampling switches are respectively connected to the positive electrode end and the negative electrode end of the ith battery cell, i is more than or equal to 1, the sampling switch connected with the positive electrode end is used for collecting the positive electrode end voltage of the ith battery cell, and the sampling switch connected with the negative electrode end is used for collecting the negative electrode end voltage of the ith battery cell; and the first end of the operational amplifier is connected with the sampling switch connected with the positive terminal voltage, the second end of the operational amplifier is connected with the sampling switch connected with the negative terminal voltage, and the output end of the operational amplifier is used for outputting the voltage related to the voltage of the ith battery cell.

According to the battery voltage acquisition device of at least one embodiment of the present disclosure, each sampling switch includes a first switch PMOS transistor and a second PMOS transistor, a drain electrode of the first switch PMOS transistor is connected to a positive terminal voltage or a negative terminal voltage of the battery cell, a source electrode of the first switch PMOS transistor is connected to a source electrode of the second switch PMOS transistor, an output voltage of a drain electrode of the second switch PMOS transistor is provided to the operational amplifier, and a gate electrode of the first switch PMOS transistor and a gate electrode of the second PMOS transistor are connected.

According to the battery voltage acquisition device of at least one embodiment of the present disclosure, the sampling switch further comprises a diode, the source electrode of the first switch PMOS transistor and the source electrode of the second switch PMOS transistor are connected to the cathode of the diode, and the anode of the diode is connected to the power supply voltage.

According to the battery voltage acquisition device of at least one embodiment of the present disclosure, the sampling switch further includes a first switching resistor, and two ends of the first switching resistor are respectively connected to sources of the first switching PMOS transistor and the second switching PMOS transistor and gates of the first switching PMOS transistor and the second switching PMOS transistor.

According to the battery voltage acquisition device of at least one embodiment of the present disclosure, at least two PMOS transistors or diodes connected in series are further connected between the sources of the first and second switch PMOS transistors and the gates of the first and second switch PMOS transistors.

According to the battery voltage acquisition device of at least one embodiment of the present disclosure, the gates of the first switch PMOS transistor and the second switch PMOS transistor are connected to a ground voltage via a first current source.

According to the battery voltage acquisition device of at least one embodiment of the present disclosure, each sampling switch includes a first switching NMOS transistor and a second NMOS transistor, a drain electrode of the first switching NMOS transistor is connected to a positive terminal voltage or a negative terminal voltage of the battery cell, a source electrode of the first switching NMOS transistor is connected to a source electrode of the second switching NMOS transistor, an output voltage of a drain electrode of the second switching NMOS transistor is provided to the operational amplifier, and a gate electrode of the first switching NMOS transistor and a gate electrode of the second NMOS transistor are connected.

According to the battery voltage acquisition device of at least one embodiment of the present disclosure, the sampling switch further comprises a diode, the source electrode of the first switch NMOS transistor and the source electrode of the second switch NMOS transistor are connected with the cathode of the diode, and the anode of the diode is connected with the ground voltage.

According to the battery voltage acquisition device of at least one embodiment of the present disclosure, the sampling switch further includes a second switching resistor, and two ends of the second switching resistor are respectively connected to sources of the first switching NMOS transistor and the second switching NMOS transistor and gates of the first switching NMOS transistor and the second switching NMOS transistor.

According to the battery voltage acquisition device of at least one embodiment of the present disclosure, at least two NMOS transistors or diodes connected in series are further connected between the sources of the first and second NMOS transistors and the gates of the first and second NMOS transistors.

According to the battery voltage acquisition device of at least one embodiment of the present disclosure, the gates of the first and second switching NMOS transistors are connected to a supply voltage via a first current source.

According to another aspect of the present disclosure, there is provided a battery management system including: the battery voltage acquisition device according to any one of the above, configured to acquire voltages of battery cells of a battery pack; and the analog-to-digital conversion module is used for receiving the voltage of each battery cell.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 is a schematic structural view of a battery voltage acquisition device according to one embodiment of the present disclosure.

Fig. 2 is a circuit schematic diagram of a sampling switch according to one embodiment of the present disclosure.

Fig. 3 is a circuit schematic of a sampling switch according to one embodiment of the present disclosure.

Fig. 4 is a circuit schematic diagram of a sampling switch according to one embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a battery management system according to one embodiment of the present disclosure.

Detailed Description

The present disclosure is described in further detail below with reference to the drawings and the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant content and not limiting of the present disclosure. It should be further noted that, for convenience of description, only a portion relevant to the present disclosure is shown in the drawings.

In addition, embodiments of the present disclosure and features of the embodiments may be combined with each other without conflict. The technical aspects of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the exemplary implementations/embodiments shown are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Thus, unless otherwise indicated, features of the various implementations/embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concepts of the present disclosure.

The use of cross-hatching and/or shading in the drawings is typically used to clarify the boundaries between adjacent components. As such, the presence or absence of cross-hatching or shading does not convey or represent any preference or requirement for a particular material, material property, dimension, proportion, commonality between illustrated components, and/or any other characteristic, attribute, property, etc. of a component, unless indicated. In addition, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. While the exemplary embodiments may be variously implemented, the specific process sequences may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order from that described. Moreover, like reference numerals designate like parts.

When an element is referred to as being "on" or "over", "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. For this reason, the term "connected" may refer to physical connections, electrical connections, and the like, with or without intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "under … …," under … …, "" under … …, "" lower, "" above … …, "" upper, "" above … …, "" higher "and" side (e.g., as in "sidewall"), etc., to describe one component's relationship to another (other) component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary term "below" … … can encompass both an orientation of "above" and "below". Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising," and variations thereof, are used in the present specification, the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof is described, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not as degree terms, and as such, are used to explain the inherent deviations of measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

According to one embodiment of the present disclosure, a battery voltage acquisition device is provided. The battery voltage acquisition device can be used for acquiring the voltage of each battery cell of the battery pack.

As shown in FIG. 1, the battery pack can be formed by connecting n battery cells B1, B2, bn-1 and Bn in series, wherein n is more than or equal to 2. The battery voltage acquisition device can be used for acquiring voltages VB 1-VBn of battery cells of each battery.

For example, in the process of collecting the battery cell B1, the voltage of the positive terminal of the battery cell B1 may be collected to realize the detection of the voltage of the battery cell B1. In the process of collecting the battery cells B2-Bn, the voltages of the positive electrode terminals and the negative electrode terminals of the battery cells B2-Bn can be collected to realize the detection of the voltages of the battery cells B2-Bn. Of course, the voltage at the negative terminal of the battery cell B1 may be acquired.

The voltage acquisition of the battery cell Bi is described below. The battery cell B2 is described as an example. In the voltage acquisition process of the battery cell B2, the voltage VB2 at the positive end and the voltage VB1 at the negative end of the battery cell B2 can be detected, and the voltage of the battery cell B2 is obtained through the voltage VB2 at the positive end and the voltage VB1 at the negative end.

As shown in fig. 1, the positive and negative terminals of the battery cell B2 may be connected to the operational amplifier OPA through sampling switches, respectively. For example, in the process of detecting the battery cell B2, sampling switches at two ends of the battery cell B2 are turned on, and other sampling switches are turned off. When the sampling switch of the acquisition voltage VB1 is turned on, the output voltage of the sampling switch is Vcxp, and when the sampling switch of the acquisition voltage VB2 is turned on, the output voltage of the sampling switch is Vcx. Vcxp may be connected to the negative terminal of the operational amplifier OPA, and Vcx may be connected to the positive terminal of the operational amplifier OPA via the first resistor Rs 1. The output terminal of the operational amplifier is connected to the gate of the first NMOS transistor Ns to control on or off of the first NMOS transistor Ns. One end of the first resistor Rs1 is connected to the drain of the first NMOS transistor Ns, the source of the first NMOS transistor Ns is connected to one end of the second resistor Rs2, and the other end of the second resistor Rs2 is grounded. The connection terminal of the source of the first NMOS transistor Ns and the second resistor Rs2 may be the output terminal of the voltage Vcell of the battery cell.

So that in case the first NMOS transistor Ns is turned on,thus doing so

The same method is also adopted for voltage collection of the battery voltage of the n-1 th section and other sections, for example, in the voltage collection process of the battery cell Bn-1, a sampling switch at the positive end and a sampling switch at the negative end of the battery cell Bn-1 are conducted, and other sampling switches are disconnected.

In this way, in the process of collecting the n battery cells, the on-off state of the corresponding sampling switch can be controlled, and the voltages of the n battery cells are collected respectively, so that the voltages of the batteries are output respectively.

The voltage acquisition of each battery cell can be realized through one operational amplifier in the mode. To accommodate the use of an operational amplifier, the present application also provides a circuit form of the sampling switch. Compared with the prior art, the sampling switch has a simpler structure, and saves the use of devices.

Fig. 2 shows a circuit form of a sampling switch according to a first embodiment of the present disclosure. As shown in fig. 2, the input terminal Vs of the circuit of the sampling switch in the dashed box may be connected to the positive terminal or the negative terminal of the battery cell, and the output terminal Vcx/Vcxp is input to the operational amplifier OPA.

As shown in fig. 2, the sampling switch may include a first switching PMOS transistor P1 and a second PMOS transistor P2. The drain electrode of the first switch PMOS transistor P1 is connected with the positive electrode terminal or the negative electrode terminal of the battery cell. The source of the first switch PMOS transistor P1 is connected to the source of the second PMOS transistor P2. The drain of the second PMOS transistor P2 serves as the output of the sampling switch. The gate of the first switching PMOS transistor P1 and the gate of the second PMOS transistor P2 are interconnected as a gate terminal Gp. The gate of the first switching PMOS transistor P1 and the gate of the second PMOS transistor P2 are connected to the ground voltage VSS via the first current source I1.

The anode of the diode D1 is connected to the supply voltage VCC, and the cathode of the diode D1 is connected to the sources of the first switching PMOS transistor P1 and the second PMOS transistor P2 and serves as the source terminal Sp. According to an embodiment of the present disclosure, a first switching resistor R1 may be connected between the gate terminal Gp and the source terminal Sp, and both ends of the first switching resistor R1 are connected to the gate terminal Gp and the source terminal Sp, respectively.

Further, at least two PMOS transistors P3 and Pn connected in series may be connected between the gate terminal Gp and the source terminal Sp, wherein the number of PMOS transistors herein may be two or more than three. For example, in the case of two, the source of the third switching PMOS transistor P3 may be connected to the sources of the first switching PMOS transistor P1 and the second PMOS transistor P2. The gate and drain of the third switch PMOS transistor P3 are connected. The drain of the third switching PMOS transistor P3 is connected to the source of the n-th switching PMOS transistor Pn. The gate and drain of the n-th switch PMOS transistor Pn are connected. The drain of the n-th switch PMOS transistor Pn is connected to the gate of the first switch PMOS transistor P1 and the gate of the second PMOS transistor P2.

In this embodiment, the on or off of the sampling switch is realized by the on or off of the first switching PMOS transistor P1 and the second switching PMOS transistor P2. In the case of employing one MOS transistor, since the MOS transistor has a parasitic diode, even in the case of the MOS transistor being turned off, a current flows through the MOS transistor due to the parasitic diode, so that the MOS transistor cannot be turned off completely. In the present disclosure, by providing two MOS transistors and disposing parasitic diodes in opposition, the flow of current can be completely blocked, so that complete turning off of the sampling switch can be achieved.

By providing the first switching resistor R1, in the case that the current of the current source I1 flows through the first switching resistor R1, the first switching resistor R1 will generate a voltage drop, thereby controlling the on or off of the first switching PMOS transistor P1 and the second PMOS transistor P2. In addition, in the case of the on state of the first switching PMOS transistor P1 and the second PMOS transistor P2, the at least two PMOS transistors P3 to Pn connected in series can realize the protection and clamping functions, thereby protecting the gate-source voltages of the first switching PMOS transistor P1 and the second PMOS transistor P2 from exceeding the prescribed value. In the present disclosure, the diode D1 may be used to protect the voltages of the source terminals Sp of the first and second switching PMOS transistors P1 and P2.

The sampling switch of the embodiment can effectively realize the disconnection of the sampling switch, and has simple control mode and less devices.

Fig. 3 shows a circuit form of a sampling switch according to a second embodiment of the present disclosure. As shown in fig. 3, the input terminal Vs of the circuit of the sampling switch in the dashed box may be connected to the positive terminal or the negative terminal of the battery cell, and the output terminal Vcx/VcxN is input to the operational amplifier OPA.

As shown in fig. 3, the sampling switch may include a first switching NMOS transistor N1 and a second NMOS transistor N2. The drain electrode of the first switch NMOS transistor N1 is connected with the positive electrode terminal or the negative electrode terminal of the battery cell. The source of the first switching NMOS transistor N1 is connected with the source of the second NMOS transistor N2. The drain of the second NMOS transistor N2 serves as the output of the sampling switch. The gate of the first switching NMOS transistor N1 and the gate of the second NMOS transistor N2 are interconnected as a gate terminal Gn. The gate of the first switching NMOS transistor N1 and the gate of the second NMOS transistor N2 are connected to the supply voltage VCC via a second current source I2.

The anode of the diode D2 is connected to the ground voltage VSS, and the cathode of the diode D2 is connected to the sources of the first and second switching NMOS transistors N1 and N2 and serves as a source terminal Sn. According to an embodiment of the present disclosure, a second switching resistor R2 may be connected between the gate terminal Gn and the source terminal Sn, and both ends of the second switching resistor R2 are connected to the gate terminal Gn and the source terminal Sn, respectively.

Further, at least two NMOS transistors N3 and Nn connected in series may be connected between the gate terminal Gn and the source terminal Sn, wherein the number of NMOS transistors herein may be two or more than three. For example, in the case of two, the source of the third switching NMOS transistor N3 may be connected to the sources of the first switching NMOS transistor N1 and the second NMOS transistor N2. The gate and drain of the third switching NMOS transistor N3 are connected. The drain of the third switching NMOS transistor N3 is connected to the source of the nth switching NMOS transistor Nn. The gate and drain of the n-th switching NMOS transistor Nn are connected. The drain of the N-th switching NMOS transistor Nn is connected to the gate of the first switching NMOS transistor N1 and the gate of the second NMOS transistor N2.

In this embodiment, the on or off of the sampling switch is realized by the on or off of the first switching NMOS transistor N1 and the second switching NMOS transistor N2. In the case of employing one MOS transistor, since the MOS transistor has a parasitic diode, even in the case of the MOS transistor being turned off, a current flows through the MOS transistor due to the parasitic diode, so that the MOS transistor cannot be turned off completely. In the present disclosure, by providing two MOS transistors and disposing parasitic diodes in opposition, the flow of current can be completely blocked, so that complete turning off of the sampling switch can be achieved.

By providing the second switching resistor R2, in the case that the current of the current source I2 flows through the second switching resistor R2, the second switching resistor R2 will generate a voltage drop, thereby controlling the on or off of the first switching NMOS transistor N1 and the second NMOS transistor N2. In addition, in the case of the on state of the first switching NMOS transistor N1 and the second NMOS transistor N2, the at least two NMOS transistors N3 to Nn connected in series can realize protection and clamping effects, thereby protecting the gate-source voltages of the first switching NMOS transistor N1 and the second NMOS transistor N2 from exceeding a prescribed value. In the present disclosure, the diode D2 may be used to protect the voltages of the source terminals Sn of the first and second switching NMOS transistors N1 and N2.

The sampling switch of the embodiment can effectively realize the disconnection of the sampling switch, and has simple control mode and less devices.

Fig. 4 shows a circuit form of a sampling switch according to another embodiment of the present disclosure. The sampling switch circuit shown in fig. 4 differs from that of fig. 3. Diode D3 may be used instead of the series connected NMOS transistors N3 to Nn. The diode D3 can achieve the same function as the NMOS transistors N3 to Nn connected in series. Based on the same principle, diodes may be used instead of the PMOS transistors P3 to Pn in series in the embodiment of fig. 2.

According to a further embodiment of the present disclosure, there is also provided a battery management system. Wherein the battery management system may include a sampling module, wherein the sampling module may include the sampling circuit described above. The analog-to-digital conversion module may receive the voltage of the battery cells of the sampling module and provide to the control logic module.

In the description of the present specification, reference to the terms "one embodiment/manner," "some embodiments/manner," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/manner or example is included in at least one embodiment/manner or example of the present application. In this specification, the schematic representations of the above terms are not necessarily for the same embodiment/manner or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/modes or examples described in this specification and the features of the various embodiments/modes or examples can be combined and combined by persons skilled in the art without contradiction.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise.

It will be appreciated by those skilled in the art that the above-described embodiments are merely for clarity of illustration of the disclosure, and are not intended to limit the scope of the disclosure. Other variations or modifications will be apparent to persons skilled in the art from the foregoing disclosure, and such variations or modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A battery voltage acquisition device for acquiring voltages of battery cells of a battery pack, comprising:

the sampling switches are respectively connected to the positive electrode end and the negative electrode end of the ith battery cell, i is more than or equal to 1, the sampling switch connected with the positive electrode end is used for collecting the positive electrode end voltage of the ith battery cell, and the sampling switch connected with the negative electrode end is used for collecting the negative electrode end voltage of the ith battery cell; and

and the first end of the operational amplifier is connected with the sampling switch connected with the voltage of the positive electrode end, the second end of the operational amplifier is connected with the sampling switch connected with the voltage of the negative electrode end, and the output end of the operational amplifier is used for outputting the voltage related to the voltage of the ith battery cell.

2. The battery voltage acquisition device of claim 1, wherein each sampling switch comprises a first switching PMOS transistor and a second PMOS transistor, a drain of the first switching PMOS transistor is connected to a positive terminal voltage or a negative terminal voltage of the battery cell, a source of the first switching PMOS transistor is connected to a source of the second switching PMOS transistor, an output voltage of a drain of the second switching PMOS transistor is provided to the operational amplifier, and a gate of the first switching PMOS transistor is connected to a gate of the second PMOS transistor.

3. The battery voltage acquisition device of claim 2 wherein the sampling switch further comprises a diode, the source of the first switching PMOS transistor and the source of the second switching PMOS transistor being connected to the cathode of the diode, the anode of the diode being connected to the supply voltage.

4. The battery voltage acquisition device of claim 2, wherein the sampling switch further comprises a first switching resistor, two ends of the first switching resistor being connected to sources of the first switching PMOS transistor and the second PMOS transistor and gates of the first switching PMOS transistor and the second PMOS transistor, respectively.

5. The battery voltage acquisition device of claim 4 wherein at least two PMOS transistors or diodes in series are also connected between the sources of the first and second PMOS transistors and the gates of the first and second PMOS transistors.

6. The battery voltage acquisition device of claim 5, wherein the gates of the first and second switching PMOS transistors are connected to ground voltage via a first current source.

7. The battery voltage acquisition device of claim 1, wherein each sampling switch comprises a first switching NMOS transistor and a second NMOS transistor, a drain of the first switching NMOS transistor is connected to a positive terminal voltage or a negative terminal voltage of the battery cell, a source of the first switching NMOS transistor is connected to a source of the second switching NMOS transistor, an output voltage of a drain of the second switching NMOS transistor is provided to the operational amplifier, and a gate of the first switching NMOS transistor is connected to a gate of the second NMOS transistor.

8. The battery voltage acquisition device of claim 7 wherein the sampling switch further comprises a diode, the source of the first switching NMOS transistor and the source of the second switching NMOS transistor being connected to the cathode of the diode, the anode of the diode being connected to ground voltage.

9. The battery voltage acquisition device of claim 7, wherein,

optionally, the sampling switch further comprises a second switching resistor, and two ends of the second switching resistor are respectively connected with sources of the first switching NMOS transistor and the second switching NMOS transistor and gates of the first switching NMOS transistor and the second switching NMOS transistor;

optionally, at least two NMOS transistors or diodes connected in series are further connected between the sources of the first and second NMOS transistors and the gates of the first and second NMOS transistors;

optionally, the gates of the first and second switching NMOS transistors are connected to a supply voltage via a first current source.

10. A battery management system, comprising:

the battery voltage acquisition device according to any one of claims 1 to 9, for acquiring voltages of individual battery cells of a battery pack; and

and the analog-to-digital conversion module is used for receiving the voltage of each battery cell.