CN220440687U - All-pass filter module based on voltage differential transconductance amplifier - Google Patents

Abstract

The utility model relates to the technical field of semiconductors, in particular to an all-pass filter module based on a voltage differential transconductance amplifier. The all-pass filter module comprises a first voltage differential transconductance amplifier VDTA1, a second voltage differential transconductance amplifier VDTA2, a capacitor C1 and a capacitor C2, wherein the VDTA1 and the VDTA2 are identical and comprise a plurality of NMOS transistors and PMOS transistors. The all-pass filter module based on the voltage differential transconductance amplifier overcomes the limitations of the existing all-pass filter circuit module, and comprises the problems that the center frequency and the quality factor cannot be controlled electronically and adjusted independently, and negative input voltage signals and transconductance values are required to be matched, so that the performance, the controllability and the flexibility of the all-pass filter are improved at low cost.

Description

All-pass filter module based on voltage differential transconductance amplifier

Technical Field

The utility model relates to the technical field of semiconductors, in particular to an all-pass filter module based on a voltage differential transconductance amplifier.

Background

The all-pass filter is used as an important integrated circuit internal circuit module and has wide application in front-end signal acquisition and processing links of various functional circuits.

However, in the prior art, there are some limitations of the same type of circuit module, including that the center frequency and the quality factor cannot be controlled electronically and cannot be adjusted independently of each other, and that some all-pass filters require input of a negative input voltage signal to achieve all-pass filtering and require matching between transconductance values, and these limitations not only limit the performance, controllability, flexibility, etc. of the all-pass filter, but also increase the complexity of the design and production cost of the all-pass filter module.

Disclosure of Invention

The utility model aims to overcome the limitations of the existing all-pass filter circuit module, including the problems that the center frequency and the quality factor cannot be controlled electronically and regulated independently, and the negative input voltage signal and the transconductance value are required to be matched, so that the performance, the controllability and the flexibility of the all-pass filter are improved at low cost.

Aiming at the problems existing in the prior art, the utility model adopts the following technical scheme:

an all-pass filter module based on a voltage differential transconductance amplifier comprises a first voltage differential transconductance amplifier VDTA1, a second voltage differential transconductance amplifier VDTA2, a capacitor C1 and a capacitor C2, wherein the VDTA1 and the VDTA2 are the same and comprise a plurality of NMOS transistors and PMOS transistors;

the 1 pin VN of VDTA1 is connected with the 4 pin X-of VDTA 2; the 2 pin of VDTA1 and the 1 pin of VDTA2 are respectively connected with the input voltage V ₁ And V ₂ The 5 pin of VDTA2 is connected with the input voltage V through a capacitor C2 ₃ The method comprises the steps of carrying out a first treatment on the surface of the The 5 pin Zp of the VDTA1 is grounded through the capacitor C1, and the 2 pin VP of the VDTA2 is connected between the 5 pin Zp of the VDTA1 and the capacitor C1; the 1 pin of VDTA1 is also connected between the 5 pin Zp of VDTA2 and the capacitor C2; 3 pins X+, 4 pins X-, 6 pins Z of VDTA1 _N 3 pins X+ and 6 pin Z of VDTA2 _N Is a current output terminal.

Optionally, the input voltage V ₁ 、V ₂ V (V) ₃ Equal.

Optionally, VDTA1 and VDTA2 comprise PMOS tube M _P1 、M _P2 、M _P3 、M _P4 、M _P5 、M _P6 、M _P7 、M _P8 、M _P9 、M _P10 、M ₁ 、M ₂ 、M ₃ 、M ₄ 、M ₅ 、M ₆ 、M ₇ M is as follows ₈ Also comprises an NMOS tube M _N1 、M _N2 、M _N3 、M _N4 、M _N5 、M _N6 、M _N7 、M _N8 、M _N9 、M _N10 、M _N11 、M _N12 、M _N13 、M _N14 、M _N15 、M _N16 、M _N17 M is as follows _N18 ；

M _P9 、M _P1 、M _P3 、M _P7 、M _P5 M is as follows _P10 Source connection V of (2) _DD ；M _P2 Gate, M of (2) _P4 Gate of (c) and M _P9 Gate connection of M _P9 The grid of (C) is also connected with M _P9 Drain electrode connection of M _P9 The drain electrode of (C) is also connected with M _N13 Is connected with the drain electrode of the transistor; m is M _P1 Gate and M of (2) _P3 Gate connection of M _P1 Drain electrode of (C) and M _P2 Is connected with the source electrode of M _P1 The grid of (C) is also connected with M _P2 Drain electrode connection of M _P2 The drain electrode of (C) is also connected with M _N5 Is connected with the drain electrode of the transistor; m is M _P3 Drain electrode of (C) and M _P4 Is connected with the source electrode of M _P4 Drain electrode of M ₃ Source of (c) and M ₄ Is connected with the source electrode of the transistor; m is M ₃ Drain electrode of (C) and M ₁ Is connected with the source electrode of M ₄ Drain electrode of (C) and M ₂ Is connected with the source electrode of M ₁ Drain electrode of M ₂ Drain of (d) and M _N7 Is connected with the drain electrode of the transistor; m is M _N7 Gate, M of (2) _N5 Gate, M of (2) _N3 Gate, M of (2) _N1 Gate of (c) and M _N17 Gate connection of M _N17 Drain of (d) and M _N1 Is passed through the drain of constant current source I _B1 Grounded M _N17 The drain electrode of (C) is also connected with M _N17 Is connected with the grid electrode; m is M _N1 The drain electrode of (C) is also connected with M _N2 Gate connection of M _N1 Source electrode of (C) and M _N2 Drain electrode connection of M _N3 Source electrode of (C) and M _N4 Drain electrode connection of M _N5 Source electrode of (C) and M _N6 Drain electrode connection of M _N7 Source electrode of (C) and M _N8 Is connected with the drain electrode of the transistor; m is M _N2 、M _N4 、M _N6 M is as follows _N8 Is connected with the grid electrode;

M _N17 、M _N2 、M _N4 、M _N6 、M _N8 、M _N16 、M _N14 、M _N12 、M _N10 m is as follows _N18 Source connection V of (2) _SS ；M _P6 Gate, M of (2) _P8 Gate of (c) and M _P10 Gate connection of M _P10 The grid of (C) is also connected with M _P10 Drain electrode connection of M _P10 The drain electrode of (C) is also connected with M _N11 Is connected with the drain electrode of the transistor; m is M _P5 Gate and M of (2) _P7 Gate connection of M _P5 Drain electrode of (C) and M _P6 Is connected with the source electrode of M _P5 The grid of (C) is also connected with M _P6 Drain electrode connection of M _P6 The drain electrode of (C) is also connected with M _N13 Is connected with the drain electrode of the transistor; m is M _P7 Drain electrode of (C) and M _P8 Is connected with the source electrode of M _P8 Drain electrode of M ₇ Source of (c) and M ₈ Is connected with the source electrode of the transistor; m is M ₇ Drain electrode of (C) and M ₅ Is connected with the source electrode of M ₈ Drain electrode of (C) and M ₆ Is connected with the source electrode of M ₅ Drain electrode of M ₆ Drain of (d) and M _N15 Drain electrode connection of M ₇ And M ₅ The grid of (C) is also connected with M ₄ Drain electrode connection of M ₈ Gate and M of (2) ₆ Is grounded; m is M _N15 Gate, M of (2) _N13 Gate, M of (2) _N11 Gate, M of (2) _N9 Is a gate of (2)Pole and M _N18 Gate connection of M _N18 Drain of (d) and M _N9 Is passed through the drain of constant current source I _B2 Grounded M _N18 The drain electrode of (C) is also connected with M _N18 Is connected with the grid electrode; m is M _N9 The drain electrode of (C) is also connected with M _N10 Gate connection of M _N9 Source electrode of (C) and M _N10 Drain electrode connection of M _N11 Source electrode of (C) and M _N12 Drain electrode connection of M _N13 Source electrode of (C) and M _N14 Drain electrode connection of M _N15 Source electrode of (C) and M _N16 Is connected with the drain electrode of the transistor; m is M _N10 、M _N12 、M _N14 M is as follows _N16 Is connected with the grid electrode;

M ₃ and M ₁ The grid electrode of the gate electrode is commonly used as a VP pin; m is M ₃ Drain electrode of (C) and M ₁ Together as Z _N Pins; m is M ₄ Gate and M of (2) ₂ Is commonly used as a VN pin; m is M ₇ Gate and M of (2) ₅ Is taken as Z together with the grid electrode of (C) _P Pins; m is M ₇ Drain electrode of (C) and M ₅ Together as an X-pin; m is M ₈ Drain electrode of (C) and M ₆ The sources of (2) are commonly used as the X+ pins.

In summary, the all-pass filter module based on the voltage differential transconductance amplifier has the following beneficial effects:

the utility model provides a three-input and single-output electronic tunable mixed multimode (transadmittance and voltage mode) biquad filter circuit structure based on a voltage differential transconductance amplifier VDTA module, which adopts 2 VDTAs and 2 capacitors, does not need element selection conditions to realize a specific filtering function, has a natural frequency which can be electronically regulated by bias current, has a quality factor which can be independently regulated by frequency, can obtain two different modes, namely a voltage mode and a transadmittance mode, and overcomes the limitations of the traditional all-pass filter circuit module, including the problems that the center frequency and the quality factor cannot be electronically controlled and mutually independently regulated, and the negative input voltage signal and transconductance value are required to be matched, so that the performance, the controllability and the flexibility of the all-pass filter are improved at low cost.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an all-pass filter module based on a voltage differential transconductance amplifier according to a first embodiment of the present utility model;

fig. 2 is a schematic circuit connection structure of a voltage differential transconductance amplifier module according to a first embodiment of the present utility model.

Detailed Description

The present utility model will be described in further detail with reference to the accompanying drawings and examples of implementation in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.

Furthermore, the terms "mounted," "configured," "provided," "connected," and "connected" are to be construed broadly. For example, it may be a fixed connection, a removable connection, or a unitary construction; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements, or components. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

Referring to fig. 1, an embodiment of the utility model provides an all-pass filter module based on a voltage differential transconductance amplifier, which includes a first voltage differential transconductance amplifier VDTA1, a second voltage differential transconductance amplifier VDTA2, a capacitor C1, and a capacitor C2, where VDTA1 and VDTA2 are the same and include a plurality of NMOS transistors and PMOS transistors;

the 1 pin VN of VDTA1 is connected with the 4 pin X-of VDTA 2; the 2 pin of VDTA1 and the 1 pin of VDTA2 are respectively connected with the input voltage V ₁ And V ₂ The 5 pin of VDTA2 is connected with the input voltage V through a capacitor C2 ₃ The method comprises the steps of carrying out a first treatment on the surface of the The 5 pin Zp of the VDTA1 is grounded through the capacitor C1, and the 2 pin VP of the VDTA2 is connected between the 5 pin Zp of the VDTA1 and the capacitor C1; the 1 pin of VDTA1 is also connected between the 5 pin Zp of VDTA2 and the capacitor C2; 3 pins X+, 4 pins X-, 6 pins Z of VDTA1 _N 3 pins X+ and 6 pin Z of VDTA2 _N Is a current output terminal.

The utility model provides a three-input and single-output electronic tunable hybrid multimode (transadmittance and voltage mode) biquad filter circuit structure based on a voltage differential transconductance amplifier VDTA module, which is shown in figure 1, adopts 2 VDTAs and 2 capacitors, does not need element selection conditions to realize a specific filtering function, has an inherent frequency which can be electronically regulated by bias current, and has a quality factor which can be regulated independently of frequency. It can be given two different modes, namely a voltage mode and a transadmittance mode.

The natural frequency ω0 and the quality factor Q of the filter circuit shown in fig. 1 are respectively:

from the above formula, the figure of merit can be determined by g _ms2 Adjusting the value without affecting the natural frequency w ₀ 。

The all-pass filter module based on the voltage differential transconductance amplifier overcomes the limitations of the existing all-pass filter circuit module, and comprises the problems that the center frequency and the quality factor cannot be controlled electronically and adjusted independently, and negative input voltage signals and transconductance values are required to be matched, so that the performance, the controllability and the flexibility of the all-pass filter are improved at low cost.

Further, input voltage V ₁ 、V ₂ V (V) ₃ Equal to the input voltage signal V _IN 。

Further, referring to fig. 2, VDTA1 and VDTA2 include PMOS transistor M _P1 、M _P2 、M _P3 、M _P4 、M _P5 、M _P6 、M _P7 、M _P8 、M _P9 、M _P10 、M ₁ 、M ₂ 、M ₃ 、M ₄ 、M ₅ 、M ₆ 、M ₇ M is as follows ₈ Also comprises an NMOS tube M _N1 、M _N2 、M _N3 、M _N4 、M _N5 、M _N6 、M _N7 、M _N8 、M _N9 、M _N10 、M _N11 、M _N12 、M _N13 、M _N14 、M _N15 、M _N16 、M _N17 M is as follows _N18 ；

M _P9 、M _P1 、M _P3 、M _P7 、M _P5 M is as follows _P10 Source connection V of (2) _DD ；M _P2 Gate, M of (2) _P4 Gate of (c) and M _P9 Gate connection of M _P9 The grid of (C) is also connected with M _P9 Drain electrode connection of M _P9 The drain electrode of (C) is also connected with M _N13 Is connected with the drain electrode of the transistor; m is M _P1 Gate and M of (2) _P3 Gate connection of M _P1 Drain electrode of (C) and M _P2 Is connected with the source electrode of M _P1 The grid of (C) is also connected with M _P2 Drain electrode connection of M _P2 The drain electrode of (C) is also connected with M _N5 Is connected with the drain electrode of the transistor; m is M _P3 Drain electrode of (C) and M _P4 Is connected with the source electrode of M _P4 Drain electrode of M ₃ Source of (c) and M ₄ Is connected with the source electrode of the transistor; m is M ₃ Drain electrode of (C) and M ₁ Is connected with the source electrode of M ₄ Drain electrode of (C) and M ₂ Is connected with the source electrode of M ₁ Drain electrode of M ₂ Drain of (d) and M _N7 Is connected with the drain electrode of the transistor; m is M _N7 Gate, M of (2) _N5 Gate, M of (2) _N3 Gate, M of (2) _N1 Gate of (c) and M _N17 Gate connection of M _N17 Drain of (d) and M _N1 Is passed through the drain of constant current source I _B1 Grounded M _N17 The drain electrode of (C) is also connected with M _N17 Is connected with the grid electrode; m is M _N1 The drain electrode of (C) is also connected with M _N2 Gate connection of M _N1 Source electrode of (C) and M _N2 Drain electrode connection of M _N3 Source electrode of (C) and M _N4 Drain electrode connection of M _N5 Source electrode of (C) and M _N6 Drain electrode connection of M _N7 Source electrode of (C) and M _N8 Is connected with the drain electrode of the transistor; m is M _N2 、M _N4 、M _N6 M is as follows _N8 Is connected with the grid electrode;

M _N17 、M _N2 、M _N4 、M _N6 、M _N8 、M _N16 、M _N14 、M _N12 、M _N10 m is as follows _N18 Source connection V of (2) _SS ；M _P6 Gate, M of (2) _P8 Gate of (c) and M _P10 Gate connection of M _P10 The grid of (C) is also connected with M _P10 Drain electrode connection of M _P10 The drain electrode of (C) is also connected with M _N11 Is connected with the drain electrode of the transistor; m is M _P5 Gate and M of (2) _P7 Gate connection of M _P5 Drain electrode of (C) and M _P6 Is connected with the source electrode of M _P5 The grid of (C) is also connected with M _P6 Drain electrode connection of M _P6 The drain electrode of (C) is also connected with M _N13 Is connected with the drain electrode of the transistor; m is M _P7 Drain electrode of (C) and M _P8 Is connected with the source electrode of M _P8 Drain electrode of M ₇ Source of (c) and M ₈ Is connected with the source electrode of the transistor; m is M ₇ Drain electrode of (C) and M ₅ Is connected with the source electrode of M ₈ Drain electrode of (C) and M ₆ Is connected with the source electrode of M ₅ Drain electrode of M ₆ Drain of (d) and M _N15 Drain electrode connection of M ₇ And M ₅ The grid of (C) is also connected with M ₄ Drain electrode connection of M ₈ Gate and M of (2) ₆ Is grounded; m is M _N15 Gate, M of (2) _N13 Gate, M of (2) _N11 Gate, M of (2) _N9 Gate of (c) and M _N18 Gate connection of M _N18 Drain of (d) and M _N9 Is passed through the drain of constant current source I _B2 Grounded M _N18 The drain electrode of (C) is also connected with M _N18 Is connected with the grid electrode; m is M _N9 The drain electrode of (C) is also connected with M _N10 Gate connection of M _N9 Source electrode of (C) and M _N10 Drain electrode connection of M _N11 Source electrode of (C) and M _N12 Drain electrode connection of M _N13 Source electrode of (C) and M _N14 Drain electrode connection of M _N15 Source electrode of (C) and M _N16 Is connected with the drain electrode of the transistor; m is M _N10 、M _N12 、M _N14 M is as follows _N16 Is connected with the grid electrode;

M ₃ and M ₁ The grid electrode of the gate electrode is commonly used as a VP pin; m is M ₃ Drain electrode of (C) and M ₁ Together as Z _N Pins; m is M ₄ Gate and M of (2) ₂ Is commonly used as a VN pin; m is M ₇ Gate and M of (2) ₅ Is taken as Z together with the grid electrode of (C) _P Pins; m is M ₇ Drain electrode of (C) and M ₅ Together as an X-pin; m is M ₈ Drain electrode of (C) and M ₆ The sources of (2) are commonly used as the X+ pins.

According to the DATA module provided by the utility model, the wide-swing cascode current source has the advantages of high precision and high output resistance according to the basic current mirror image.

The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model.

Claims (3)

1. An all-pass filter module based on a voltage differential transconductance amplifier is characterized by comprising a first voltage differential transconductance amplifier VDTA1, a second voltage differential transconductance amplifier VDTA2, a capacitor C1 and a capacitor C2, wherein the VDTA1 and the VDTA2 are the same and comprise a plurality of NMOS transistors and PMOS transistors;

the 1 pin VN of VDTA1 is connected with the 4 pin X-of VDTA 2; the 2 pin of VDTA1 and the 1 pin of VDTA2 are respectively connected with the input voltage V ₁ And V ₂ The 5 pin of VDTA2 is connected with the input voltage V through a capacitor C2 ₃ The method comprises the steps of carrying out a first treatment on the surface of the The 5 pin Zp of the VDTA1 is grounded through the capacitor C1, and the 2 pin VP of the VDTA2 is connected between the 5 pin Zp of the VDTA1 and the capacitor C1; the 1 pin of VDTA1 is also connected between the 5 pin Zp of VDTA2 and the capacitor C2; VDT (VDT)3 pin X+, 4 pin X-, 6 pin Z of A1 _N 3 pins X+ and 6 pin Z of VDTA2 _N Is a current output terminal.

2. The all-pass filter module based on a voltage differential transconductance amplifier according to claim 1, wherein the input voltage V ₁ 、V ₂ V (V) ₃ Equal.

3. The all-pass filter module based on a voltage differential transconductance amplifier according to claim 1, wherein VDTA1 and VDTA2 comprise PMOS tubes M _P1 、M _P2 、M _P3 、M _P4 、M _P5 、M _P6 、M _P7 、M _P8 、M _P9 、M _P10 、M ₁ 、M ₂ 、M ₃ 、M ₄ 、M ₅ 、M ₆ 、M ₇ M is as follows ₈ Also comprises an NMOS tube M _N1 、M _N2 、M _N3 、M _N4 、M _N5 、M _N6 、M _N7 、M _N8 、M _N9 、M _N10 、M _N11 、M _N12 、M _N13 、M _N14 、M _N15 、M _N16 、M _N17 M is as follows _N18 ；

M _P9 、M _P1 、M _P3 、M _P7 、M _P5 M is as follows _P10 Source connection V of (2) _DD ；M _P2 Gate, M of (2) _P4 Gate of (c) and M _P9 Gate connection of M _P9 The grid of (C) is also connected with M _P9 Drain electrode connection of M _P9 The drain electrode of (C) is also connected with M _N13 Is connected with the drain electrode of the transistor; m is M _P1 Gate and M of (2) _P3 Gate connection of M _P1 Drain electrode of (C) and M _P2 Is connected with the source electrode of M _P1 The grid of (C) is also connected with M _P2 Drain electrode connection of M _P2 The drain electrode of (C) is also connected with M _N5 Is connected with the drain electrode of the transistor; m is M _P3 Drain electrode of (C) and M _P4 Is connected with the source electrode of M _P4 Drain electrode of M ₃ Source of (c) and M ₄ Is connected with the source electrode of the transistor; m is M ₃ Drain electrode of (C) and M ₁ Is connected with the source electrode of (a)Connect M ₄ Drain electrode of (C) and M ₂ Is connected with the source electrode of M ₁ Drain electrode of M ₂ Drain of (d) and M _N7 Is connected with the drain electrode of the transistor; m is M _N7 Gate, M of (2) _N5 Gate, M of (2) _N3 Gate, M of (2) _N1 Gate of (c) and M _N17 Gate connection of M _N17 Drain of (d) and M _N1 Is passed through the drain of constant current source I _B1 Grounded M _N17 The drain electrode of (C) is also connected with M _N17 Is connected with the grid electrode; m is M _N1 The drain electrode of (C) is also connected with M _N2 Gate connection of M _N1 Source electrode of (C) and M _N2 Drain electrode connection of M _N3 Source electrode of (C) and M _N4 Drain electrode connection of M _N5 Source electrode of (C) and M _N6 Drain electrode connection of M _N7 Source electrode of (C) and M _N8 Is connected with the drain electrode of the transistor; m is M _N2 、M _N4 、M _N6 M is as follows _N8 Is connected with the grid electrode;

M _N17 、M _N2 、M _N4 、M _N6 、M _N8 、M _N16 、M _N14 、M _N12 、M _N10 m is as follows _N18 Source connection V of (2) _SS ；M _P6 Gate, M of (2) _P8 Gate of (c) and M _P10 Gate connection of M _P10 The grid of (C) is also connected with M _P10 Drain electrode connection of M _P10 The drain electrode of (C) is also connected with M _N11 Is connected with the drain electrode of the transistor; m is M _P5 Gate and M of (2) _P7 Gate connection of M _P5 Drain electrode of (C) and M _P6 Is connected with the source electrode of M _P5 The grid of (C) is also connected with M _P6 Drain electrode connection of M _P6 The drain electrode of (C) is also connected with M _N13 Is connected with the drain electrode of the transistor; m is M _P7 Drain electrode of (C) and M _P8 Is connected with the source electrode of M _P8 Drain electrode of M ₇ Source of (c) and M ₈ Is connected with the source electrode of the transistor; m is M ₇ Drain electrode of (C) and M ₅ Is connected with the source electrode of M ₈ Drain electrode of (C) and M ₆ Is connected with the source electrode of M ₅ Drain electrode of M ₆ Drain of (d) and M _N15 Drain electrode connection of M ₇ And M ₅ The grid of (C) is also connected with M ₄ Drain electrode connection of M ₈ Gate and M of (2) ₆ Is grounded; m is M _N15 Gate, M of (2) _N13 Gate, M of (2) _N11 Gate, M of (2) _N9 Gate of (c) and M _N18 Gate connection of M _N18 Drain of (d) and M _N9 Is passed through the drain of constant current source I _B2 Grounded M _N18 The drain electrode of (C) is also connected with M _N18 Is connected with the grid electrode; m is M _N9 The drain electrode of (C) is also connected with M _N10 Gate connection of M _N9 Source electrode of (C) and M _N10 Drain electrode connection of M _N11 Source electrode of (C) and M _N12 Drain electrode connection of M _N13 Source electrode of (C) and M _N14 Drain electrode connection of M _N15 Source electrode of (C) and M _N16 Is connected with the drain electrode of the transistor; m is M _N10 、M _N12 、M _N14 M is as follows _N16 Is connected with the grid electrode;

M ₃ and M ₁ The grid electrode of the gate electrode is commonly used as a VP pin; m is M ₃ Drain electrode of (C) and M ₁ Together as Z _N Pins; m is M ₄ Gate and M of (2) ₂ Is commonly used as a VN pin; m is M ₇ Gate and M of (2) ₅ Is taken as Z together with the grid electrode of (C) _P Pins; m is M ₇ Drain electrode of (C) and M ₅ Together as an X-pin; m is M ₈ Drain electrode of (C) and M ₆ The sources of (2) are commonly used as the X+ pins.