CN220368698U

CN220368698U - Packaging structure of chip and communication equipment

Info

Publication number: CN220368698U
Application number: CN202321693848.8U
Authority: CN
Inventors: 喻建明; 袁安平; 黄志成
Original assignee: Quanzhou San'an Integrated Circuit Co ltd
Current assignee: Quanzhou San'an Integrated Circuit Co ltd
Priority date: 2023-06-29
Filing date: 2023-06-29
Publication date: 2024-01-19
Anticipated expiration: 2033-06-29

Abstract

The application discloses packaging structure and communications facilities of chip relates to semiconductor packaging technical field, and the packaging structure of chip of this application includes package and apron, and package indent forms the encapsulation groove, and the apron lid is established on the encapsulation groove, and with the lateral wall fixed connection in encapsulation groove in order to form closed cavity, be provided with back-to-back structure in the encapsulation groove, back-to-back structure includes fixed connection's first chip and second chip, and the functional surface of first chip has first clearance towards the tank bottom in encapsulation groove and with the tank bottom, has the second clearance between second chip and the apron, is provided with a plurality of wiring structures that are connected with first chip and second chip respectively in the package. The packaging structure of the chip and the communication equipment can reduce the packaging volume without glue overflow.

Description

Packaging structure of chip and communication equipment

Technical Field

The application relates to the technical field of semiconductor packaging, in particular to a packaging structure of a chip and communication equipment.

Background

With the continuous development of wireless communication systems, portable terminal devices have been widely used, and one of important components for filtering is a duplexer. The diplexer, also called diplexer, is a relatively special bi-directional three-terminal filter that includes a transmit port, a receive port, and an antenna end. The function of the diplexer is to couple in weak received signals while feeding a large transmit power to the antenna and requiring that the two are isolated from each other.

Specifically, the duplexer is generally composed of two filter chips having different operating frequencies, and package substrates respectively connected to the two filter chips. When in packaging, the packaging substrate is sealed with packaging materials to form a packaging structure. For the packaging of the diplexer, the following two modes are mostly adopted in the prior art: the first is chip-level packaging, wherein a copper column is connected to a packaging substrate by adopting an ultrasonic welding technology, then film-coated packaging is carried out, or tin paste is printed, and then reflow is carried out to form a film-coated packaging after a tin ball is connected with the substrate; the second is wafer level chip scale package, which uses resin or wafer cap to cover and form cavity, then uses the metal layer under the salient point to grow copper column or brush tin to form solder, to connect the internal circuit and outer pin. However, on one hand, the two packages adopt single-layer packages, that is, filter chips are placed side by side on the same plane, so that the package structure occupies a larger area; on the other hand, the packaging substrate is plate-shaped, so that the problems of insufficient packaging of packaging materials, excessive glue overflow and the like easily occur in the packaging process.

Disclosure of Invention

The utility model provides a chip packaging structure and communication equipment, which can reduce the packaging volume without glue overflow.

The embodiment of the application provides a packaging structure of chip on the one hand, including package and apron, package indent forms the encapsulation groove, and the apron lid is established on the encapsulation groove, and with the lateral wall fixed connection in encapsulation groove in order to form sealed cavity, is provided with back-to-back structure in the encapsulation groove, back-to-back structure includes fixed connection's first chip and second chip, the functional surface of first chip towards the tank bottom of encapsulation groove and with the tank bottom has first clearance, the functional surface of second chip towards the apron and with have the second clearance between the apron, be provided with a plurality of wiring structures that are connected with first chip and second chip respectively in the package.

As an embodiment, the first chip is connected to the wiring structure by flip-chip technology, and the second chip is connected to the wiring structure by wire bonding.

As an embodiment, the back side of the first chip is fixedly connected to the back side of the second chip by means of an adhesive, or the back side of the first chip is fixedly connected to the back side of the second chip by means of vacuum lamination.

As an implementation manner, the lower surface of the cover plate is coated with a metal layer, or the cover plate is a metal cover plate, a shielding circuit is arranged in the side wall of the packaging groove, and the wiring structure comprises a grounding circuit, and the shielding circuit is connected with the cover plate and the grounding circuit.

As an embodiment, the second gap is smaller than 60 μm.

As an embodiment, the first chip and/or the second chip is a filter chip.

As an embodiment, the filter chip includes a high frequency filter chip, a low frequency filter chip, a duplexer chip, or a multiplexer chip.

As an embodiment, the wiring structure includes a first connection region connected to the first chip and a second connection region connected to the second chip, the second connection region being located at an outer periphery of the first connection region.

As an implementation manner, a third gap is formed between the side wall of the back-to-back structure and the side wall of the packaging groove, and the third gap is between 50 um and 300 um.

As an implementation manner, a plurality of groups of back-to-back structures are arranged in the packaging groove, and the plurality of groups of back-to-back structures are respectively connected with the bottom wall of the packaging groove.

As an embodiment, the cover plate is connected to the side wall of the packaging groove by one of gluing, reflow soldering or riveting.

In another aspect, an embodiment of the present application provides a communication device, including a package structure of the above chip.

The beneficial effects of the embodiment of the application include:

the utility model provides a packaging structure of chip, including package and apron, package indent forms the encapsulation groove, and the apron lid is established on the encapsulation groove, and makes the encapsulation groove be sealed cavity with the lateral wall fixed connection of encapsulation groove, be provided with back-to-back structure in the encapsulation groove, back-to-back structure includes fixed connection's first chip and second chip for two chips only possess the encapsulation area of a chip, thereby promote the utilization ratio of the encapsulation area of package, reduce the encapsulation volume, the functional surface of first chip is towards the tank bottom of encapsulation groove, be provided with a plurality of wiring structures of being connected with first chip and second chip respectively in the package. The first chip and the second chip are fixedly arranged in the packaging groove, and no additional packaging material is needed, so that no glue overflow phenomenon exists, and the packaging structure of the chip provided by the application can not cause glue overflow on the premise of reducing the packaging volume.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a package structure of a chip according to an embodiment of the present application;

FIG. 2 is a second schematic structural diagram of a package structure of a chip according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a package according to an embodiment of the present application;

FIG. 4 is a second schematic structural diagram of a package according to the embodiment of the present disclosure;

FIG. 5 is a third schematic structural diagram of a package structure of a chip according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a package structure of a chip according to an embodiment of the present application.

Icon: 10-packaging structure of chip; 11-packaging; 12-a first chip; 13-a second chip; 14-wiring structure; 141-a first connection region; 142-a second connection region; 16-cover plate; 17-shielding the line; 18-an adhesive.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the present application, it should be noted that, the terms "center," "vertical," "horizontal," "inner," "outer," and the like indicate an azimuth or a positional relationship based on that shown in the drawings, or an azimuth or a positional relationship that a product of the application is conventionally put in use, merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.

The packaging structure of the chip in the prior art adopts a packaging mode that two chips are packaged on the surface of the substrate, so that the area of the substrate is larger, and the packaging area is larger.

The embodiment of the application provides a packaging structure 10 of chip, including package 11 and apron 16, as shown in fig. 1 and 2, package 11 indent forms the encapsulation groove, and the apron 16 lid is established on the encapsulation groove, and with the lateral wall fixed connection in encapsulation groove in order to form closed cavity, be provided with back-to-back fixed connection's first chip 12 and second chip 13 in the encapsulation groove, the functional surface of first chip 12 is towards the tank bottom in encapsulation groove, be provided with a plurality of wiring structures 14 that are connected with first chip 12 and second chip 13 respectively in the package 11.

According to the embodiment of the application, the package 11 with the package groove is adopted, the package 11 is used as a substrate of the package structure, the wiring structures 14 connected with the first chip 12 and the second chip 13 are arranged inside the package 11, the first chip 12 and the second chip 13 are fixedly connected back to back, the first chip 12 and the second chip 13 comprise a functional surface provided with a connecting point and a back surface opposite to the functional surface, the back surface is a substrate generally, the connecting point is not arranged, the back surface of the first chip 12 and the back surface of the second chip 13 are fixedly connected, normal operation of the first chip 12 and the second chip 13 cannot be influenced, in addition, the back-to-back first chip 12 and the second chip 13 are arranged in the package groove, at the moment, only the first chip 12 occupies the package area of the package 11, so that the two chips occupy the package area of one chip, and the utilization rate of the package area of the package 11 is improved, and the package area is reduced.

In addition, in the embodiment of the present application, the first chip 12 and the second chip 13 are disposed in the packaging groove, and the side wall of the packaging groove and the cover plate 16 realize protection of the first chip 12 and the second chip 13, so that the first chip 12 and the second chip 13 may not be packaged by using packaging materials, and no glue overflow phenomenon exists due to no use of packaging materials.

The specific structure and function of the first chip 12 and the second chip 13 are not limited in this embodiment, as long as they need to work together and have a back surface and a functional surface, the functional surface has a connection point of the chip, the back surface is a substrate, and there is no connection point. Specifically, the connection point on the functional surface is a connection piece for realizing information transmission between the chip and the outside, and more specifically, the connection point can include an interdigital transducer, a reflector, a wiring pattern and the like.

Specifically, when the back-to-back structure forms the duplexer, those skilled in the art should know that the duplexer is composed of two filters with different working frequencies, and the filters need a certain space to form vibration of sound waves during working, so that the functional surface of the first chip 12 has a first gap with the bottom of the groove, the functional surface of the second chip 13 has a second gap with the cover plate 16, and the numerical values of the specific first gap and the specific second gap are not limited in the embodiment of the present application, and can be set by those skilled in the art according to practical situations.

The application provides a packaging structure 10 of chip, including package 11 and apron 16, package 11 indent forms the encapsulation groove, the apron 16 lid is established on the encapsulation groove, and make the encapsulation groove be closed cavity with the lateral wall fixed connection of encapsulation groove, be provided with back-to-back fixed connection's first chip 12 and second chip 13 in the encapsulation groove, make two chips only possess the encapsulation area of a chip, thereby promote the utilization ratio of package 11's encapsulation area, reduce the encapsulation volume, the functional surface of first chip 12 is towards the tank bottom of encapsulation groove, be provided with a plurality of wiring structure 14 that are connected with first chip 12 and second chip 13 respectively in the package 11, fix first chip and second chip and set up in the encapsulation inslot, then do not need extra packaging material, so there is not the phenomenon of glue spilling, consequently, the packaging structure of the chip that this application provided, and there is not the glue spilling phenomenon, consequently, the packaging structure 10 of the chip that this application provided can not cause glue spilling under the prerequisite of reducing the encapsulation volume.

Alternatively, as shown in fig. 1 and 2, the first chip 12 is connected to the wiring structure 14 through a flip-chip process, and the second chip 13 is connected to the wiring structure 14 through wire bonding.

Specifically, the first chip 12 is connected to the wiring structure 14 through a flip-chip process, so that the first chip 12 can be electrically connected to the package, and the second chip 13 is electrically connected to the wiring structure 14 through a wire bonding method. The first chip 12 is connected with the wiring structure 14 through a flip-chip process, the second chip 13 is connected with the wiring structure 14 through a wire bonding mode, the first chip 12 and the second chip 13 can be connected with the packaging piece 11, and the area of the packaging surface of the packaging piece 11 can be reasonably utilized.

In one possible implementation of this embodiment, as shown in fig. 1, the back surface of the first chip 12 and the back surface of the second chip 13 are fixedly connected by an adhesive 18.

Specifically, when the back surface of the first chip 12 and the second chip 13 are fixedly connected by using an adhesive, an epoxy glue or a related adhesive material may be used. The back of the first chip 12 and the back of the second chip 13 are connected through an adhesive, so that the fixing step can be simplified, the back of the second chip 13 is bonded with the back of the first chip 12 and then pressed after the back of the first chip 12 is glued, and the operation is simple and quick.

When the back surface of the first chip 12 and the back surface of the second chip 13 are fixedly connected by the adhesive 18, they may be fixed and then connected to the package 11, or the functional surface of the first chip 12 may be connected to the package 11 and then connected to the second chip 13.

Alternatively, as shown in fig. 2, the back surface of the first chip 12 and the back surface of the second chip 13 are fixedly connected by vacuum lamination.

Specifically, when the back surface of the first chip 12 and the back surface of the second chip 13 are fixedly connected by vacuum lamination, the back surface of the first chip 12 and the back surface of the second chip 13 are mechanically ground to form a connection surface with mirror surface degree, and then the back surfaces of the first chip 12 and the second chip 13 are oppositely arranged and placed in a vacuum lamination machine, and the first chip 12 and the second chip 13 are fixedly connected by a vacuum lamination process.

The first chip 12 and the second chip 13 are fixed by vacuum lamination, so that additional connecting pieces can be avoided, and the connection fastness of the fixed connection formed by vacuum lamination is high.

Since the first chip 12 and the second chip 13 are fixed by a vacuum press, the functional surface of the first chip 12 is connected with the package 11 after the first chip 12 and the second chip 13 are fixedly connected.

Since the back surfaces of the first chip 12 and the second chip 13 are substrates, the mechanical polishing is only performed to form a connection surface with a mirror surface level, and thus the thickness of the mechanical polishing is not thick, and normal operation of the first chip 12 and the second chip 13 is not affected.

In one implementation manner of this embodiment, as shown in fig. 4, 5 and 6, the lower surface of the cover plate 16 is coated with a metal layer, or the cover plate is a metal cover plate, a shielding circuit is disposed in a side wall of the packaging groove, and the wiring structure includes a grounding circuit, and the shielding circuit is connected with the cover plate and the grounding circuit.

In order to avoid interference of external signals to the operation of the first chip 12 and the second chip 13, the lower surface of the cover plate 16 is coated with a metal layer, or the cover plate is a metal cover plate, so that the cover plate is a shielding cover, and a shielding circuit is arranged in the side wall of the packaging groove, and the wiring structure comprises a grounding circuit, and the shielding circuit is connected with the cover plate and the grounding circuit.

The cover plate 16 is connected to the ground line of the wiring structure 14 through the shielding line 17, specifically, the cover plate 16 is connected to the ground line of the wiring structure 14, so that the cover plate 16 is grounded, and shielding of external signals is achieved. The shielding circuit 17 is disposed in the side wall of the package groove, so that the connection of the shielding circuit is realized while the cover plate 16 is connected in the side wall structure of the package groove.

In one possible implementation of this embodiment, as shown in fig. 2, the distance between the functional surface of the second chip 13 and the lower surface of the cover plate 16 is smaller than 60 μm, i.e. the second gap is smaller than 60 μm.

The first chip 12 and the second chip 13 are disposed in the packaging space formed by the cover plate 16 and the packaging piece 11, and the functional surface of the second chip 13 faces the cover plate 16, so as to avoid the waste of the packaging space caused by the longer distance between the functional surface of the second chip 13 and the cover plate 16, in the embodiment of the application, the distance between the functional surface of the second chip 13 and the lower surface of the cover plate 16 is smaller than 60 μm. In addition, in order to avoid abrasion of the surface of the second chip 13 caused by contact between the functional surface of the second chip 13 and the cover plate 16 and influence the shielding performance of the cover plate 16, the distance between the functional surface of the second chip 13 and the lower surface of the cover plate 16 cannot be set too small, and may be, for example, greater than 50 μm. Preferably, the distance between the functional surface of the second chip 13 and the lower surface of the cover plate 16 may be between 5 and 25 μm.

Optionally, the first chip 12 and/or the second chip 13 are filter chips. Further, the filter chip includes a high frequency filter chip, a low frequency filter chip, a duplexer chip, or a multiplexer chip.

It should be understood by those skilled in the art that when the package structure is a duplexer, the duplexer employs two filter chips having different operating frequencies, and in this embodiment, the first chip 12 and the second chip 13 are both filter chips. One of the filter chips is a high frequency filter chip and the other is a low frequency filter chip, or both are diplexer or multiplexer chips.

Alternatively, as shown in fig. 1 and 2, the wiring structure 14 includes a first connection region 141 connected to the first chip 12 and a second connection region 142 connected to the second chip 13, and the second connection region 142 is located at an outer periphery of the first connection region 141.

Because the functional surface of the first chip 12 is opposite to the packaging surface of the packaging piece 11, the connection point of the first chip 12 can be directly contacted with the packaging surface, and the first connection area connected with the first chip 12 is arranged at the central position of the packaging surface, so that the connection of the first chip 12 can be facilitated, and the area of the packaging surface is fully utilized. The functional surface of the second chip 13 is away from the package surface, and it is necessary to guide the connection point of the second chip 13 to the package surface by a wire or the like, and the second connection region 142 connected to the second chip 13 is provided on the outer periphery of the first connection region 141, so that the area of the package surface can be fully utilized.

Optionally, a third gap is formed between the side wall of the back-to-back structure and the side wall of the packaging groove, and the third gap is between 50 um and 300 um.

As can be seen from the foregoing, the second chip 13 is connected to the second connection region 142 by wire bonding, and in order to facilitate connection between the second chip 13 and the second connection region 142, the second connection region is disposed on the periphery of the orthographic projection of the first chip 12, that is, the second connection region 142 is orthographic projection of the third gap. In order to facilitate the connection between the second chip and the second connection region, the second connection region 142 cannot be too small, that is, the third gap cannot be too small, and of course, the third gap cannot be too large in consideration of the package volume, and based on the two considerations, the embodiment of the present application sets the third gap between 50 and 300 um.

In practical application, the second connection region 142 is a region of the outer periphery of the first chip, and is a ring-shaped region, and the third gap is a distance between the back-to-back structure and the side wall of the package groove, and for convenience of description, the second connection region 142 and the third gap are described as an example, and in practical application, the second connection region 142 corresponds to a plurality of third gaps.

In one implementation of the present embodiment, the first chip 12 is connected to the wiring structure 14 by ultrasonic thermocompression bonding.

Specifically, the connection point on the functional surface of the first chip 12 may be a gold ball, a copper-plated pillar, a tin ball, or the like to form a conductive member, then the functional surface of the first chip 12 provided with the conductive member is opposite to the package surface of the package 11, so that the conductive member is connected with the wiring structure 14 on the package 11, and finally the conductive member is melted by ultrasonic hot-press welding to realize the connection between the first chip 12 and the wiring structure 14.

In one implementation manner of the embodiment of the application, a plurality of groups of back-to-back structures are arranged in the packaging groove, and the plurality of groups of back-to-back structures are respectively connected with the bottom wall of the packaging groove.

When a plurality of back-to-back structures are needed in practical application, the back-to-back structures can be arranged in the packaging groove, and the back-to-back structures are respectively connected with the bottom wall of the packaging groove to realize the electric connection of the back-to-back structures.

Optionally, the cover plate 16 is connected to the side walls of the package via one of gluing, reflow soldering or riveting.

Specifically, when the cover plate 16 is connected with the side wall of the packaging groove in a gluing connection manner, glue can be dropped on the side wall of the packaging groove, then the cover plate 16 is covered on the packaging groove, and the glue is cured. The mode of gluing and fixing is simple and convenient to operate. In addition, since the glue is generally not conductive, the cover plate 16 cannot be electrically connected with the shielding circuit, at this time, as shown in fig. 3, the side wall of the packaging groove may not be provided with the shielding circuit, the lower surface of the cover plate is also not provided with metal, and the cover plate 16 only plays a role in packaging and does not play a role in shielding.

When the cover plate 16 is connected with the side wall of the packaging groove in a reflow soldering connection manner, solder paste can be coated on the cover plate 16 or the side wall of the packaging groove, then the cover plate 16 is covered on the packaging groove, and then the cover plate 16 is placed into a reflow soldering device, so that the solder paste melts to fixedly connect the cover plate 16 with the packaging piece 11. The connection mode of reflow soldering is adopted, glue is not adopted, no pollution is caused to the environment, and the cover plate 16 can be electrically connected with the shielding circuit 17 in the packaging piece 11.

When the cover plate 16 is connected with the side wall of the packaging groove in a riveted connection manner, a connection hole can be correspondingly formed on the cover plate 16 and the side wall of the packaging groove, and a bolt or a screw is in threaded connection with the connection hole to fix the cover plate 16 and the packaging piece 11. By adopting the riveting mode, the cover plate 16 is directly contacted with the packaging piece 11, and the electric connection between the cover plate 16 and the shielding circuit 17 in the packaging piece 11 can be better realized.

Of course, those skilled in the art may choose other connection modes according to the actual situation.

The embodiment of the application also discloses a communication device, which comprises the encapsulation structure 10 of the chip. The communication device includes the same structure and advantages as the package structure 10 of the chip in the previous embodiment. The structure and the beneficial effects of the package structure 10 of the chip have been described in detail in the foregoing embodiments, and are not described herein again.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. The utility model provides a packaging structure of chip, its characterized in that, includes package and apron, package indent forms the encapsulation groove, the apron lid is established on the encapsulation groove, and with the lateral wall fixed connection in encapsulation groove is in order to form closed cavity, be provided with back-to-back structure in the encapsulation groove, back-to-back structure includes fixed connection's first chip and second chip, the functional surface of first chip orientation the tank bottom of encapsulation groove and with the tank bottom has first clearance, the functional surface of second chip orientation the apron and with have the second clearance between the apron, be provided with a plurality of respectively with the wiring structure that first chip and second chip are connected in the package.

2. The package structure of the chip according to claim 1, wherein the first chip is connected to the wiring structure by a flip-chip process, and the second chip is connected to the wiring structure by wire bonding.

3. The package structure of the chip according to claim 1, wherein the back surface of the first chip and the back surface of the second chip are fixedly connected by an adhesive, or the back surface of the first chip and the back surface of the second chip are fixedly connected by vacuum lamination.

4. The packaging structure of the chip according to claim 1, wherein a metal layer is coated on the lower surface of the cover plate, or the cover plate is a metal cover plate, and a shielding circuit is arranged in the side wall of the packaging groove; the wiring structure includes a ground line; the shielding circuit is connected with the cover plate and the grounding circuit.

5. The chip package structure of claim 1, wherein the second gap is less than 60 μm.

6. The chip package structure according to claim 1, wherein the first chip and/or the second chip is a filter chip.

7. The chip package structure according to claim 6, wherein the filter chip includes a high frequency filter chip, a low frequency filter chip, a duplexer chip, or a multiplexer chip.

8. The package structure of a chip according to claim 1, wherein the wiring structure includes a first connection region connected to the first chip and a second connection region connected to the second chip, the second connection region being located at an outer periphery of the first connection region.

9. The package structure of claim 4, wherein the cover plate and the side wall of the package groove are connected by one of gluing, reflow soldering or riveting.

10. The chip package structure of claim 1, wherein a third gap is provided between the side walls of the back-to-back structure and the side walls of the package trench, and the third gap is between 50 um and 300 um.

11. The package structure of any one of claims 1 to 9, wherein a plurality of sets of back-to-back structures are disposed in the package groove, and the plurality of sets of back-to-back structures are respectively connected to the bottom wall of the package groove.

12. A communication device, characterized by a package structure comprising the chip of any of claims 1-11.