CN217444379U

CN217444379U - Packaging structure of semiconductor device and electronic equipment

Info

Publication number: CN217444379U
Application number: CN202221140609.5U
Authority: CN
Inventors: 郜振豪; 杨清华
Original assignee: Suzhou Huntersun Electronics Co Ltd
Current assignee: Suzhou Huntersun Electronics Co Ltd
Priority date: 2022-05-12
Filing date: 2022-05-12
Publication date: 2022-09-16
Anticipated expiration: 2032-05-12

Abstract

The application provides a packaging structure and electronic equipment of semiconductor device, packaging structure includes: the substrate is provided with a first surface, the first surface of the substrate is provided with a groove, and the periphery of the groove is provided with a conductive pattern area; a first device disposed in the recess, the first device being electrically connected to the conductive pattern region of the first surface of the substrate; a second device located at a side close to the first surface of the substrate and having a space from the first device, the second device being electrically connected to the conductive pattern region of the first surface of the substrate, the first device having an overlapping portion with a projection of the second device on the first surface of the substrate; and an encapsulation body for encapsulating the first device and the second device. The application can keep the original performance, and the size of the packaged substrate is smaller, so that the utilization rate of the substrate is improved, and the manufacturing cost is reduced.

Description

Packaging structure of semiconductor device and electronic equipment

Technical Field

The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor device package structure and an electronic device.

Background

With the continuous development of wireless communication systems, the demand for miniaturization and light weight of electronic products is increasingly urgent, and one of the important components playing a role in filtering is a duplexer. The duplexer is used for coupling weak receiving signals, feeding larger transmitting power to the antenna and requiring the two to be isolated from each other without mutual influence. The duplexer generally includes two chips, i.e., a transmitting filter and a receiving filter, and a package substrate for carrying the chips. A common package structure is to mount two chips on a package substrate side by side and connect the chips to the package substrate in the same electrical connection manner.

Fig. 1 shows a cross-sectional view of a package structure of a related art duplexer. The left side is a receiving filter RX, the right side is a transmitting filter TX, and the receiving filter RX and the transmitting filter TX are bonded to the substrate 101 by side-by-side flip chip bonding and packaged by the package 102. Since the distance between the receiving filter RX and the transmitting filter TX is generally greater than 100um, the external size of the packaged duplexer is large, and the manufacturing cost is relatively high due to the large amount of material required for the substrate 101 and the package 102.

SUMMERY OF THE UTILITY MODEL

The application provides a packaging structure of a semiconductor device and electronic equipment, which are used for solving the problems that the overall dimension of a duplexer in the prior art is large and the manufacturing cost is relatively high.

In a first aspect, the present application provides a package structure of a semiconductor device, including:

the substrate is provided with a first surface, the first surface of the substrate is provided with a groove, and a conductive pattern area is arranged around the groove;

a first device disposed in the recess, the first device electrically connected to the conductive pattern region of the first surface of the substrate;

a second device located at a side close to the first surface of the substrate and having a space from the first device, the second device being electrically connected to the conductive pattern region of the first surface of the substrate, the first device having an overlapping portion with a projection of the second device on the first surface of the substrate;

an encapsulation for encapsulating the first device and the second device.

In an embodiment of the present application, the package structure further includes:

and one end of the first bonding wire is electrically connected with the surface of the first device close to the second device, and the other end of the first bonding wire is electrically connected with the conductive pattern area on the first surface of the substrate.

and the adhesive coating layer is positioned between the first device and the second device and wraps the first bonding lead.

and a plurality of connectors between the first surface of the substrate and the second device, each connector having one end electrically connected to the conductive pattern region of the first surface of the substrate and the other end electrically connected to the surface of the second device close to the first device.

In an embodiment of the present application, the connecting member is any one of a copper pillar, a nickel pillar, a tin pillar, and a silver pillar.

and one end of the second bonding wire is electrically connected with the conductive pattern region on the first surface of the substrate, and the other end of the second bonding wire is electrically connected with the surface of the second device far away from the first device.

In an embodiment of the present application, the first bonding wire or the second bonding wire is any one of a gold wire, a copper wire, an aluminum wire, and a silver wire.

In an embodiment of the present application, the package structure of the semiconductor device is a duplexer.

In an embodiment of the present application, the first device is a receiving filter, and the second device is a transmitting filter; or the first device is a transmitting filter and the second device is a receiving filter.

In a second aspect, the present application further provides an electronic device including the package structure of the semiconductor device according to any one of the above first aspects.

According to the packaging structure of the semiconductor device and the electronic equipment, the first device and the second device are arranged to be of the upper-layer and lower-layer overlapping structure, the packaged overall dimension can be small, and materials of the substrate and the packaging body required by the small overall dimension are relatively few, so that the manufacturing cost is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a cross-sectional view of a package structure of a duplexer of the related art;

fig. 2 is a schematic diagram of a package structure of a semiconductor device provided herein;

fig. 3 is a cross-sectional view of a package structure of a semiconductor device according to a first embodiment of the present application;

fig. 4 is a cross-sectional view of a package structure of a semiconductor device according to a second embodiment of the present application;

reference numerals:

101: a substrate; 102: a package body; 103: a first device;

104: a second device; 105: a connecting member; 106: a solder ball;

107: covering a glue layer; 1011: a first surface; 1012: a second surface;

1013: a groove; 108: first bonding wire 109: a second bonding wire;

110: a conductive pattern region.

Detailed Description

To make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely with reference to the accompanying drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein.

The communication includes microwave communication, mobile communication, optical communication, and the like. Microwave communication and mobile communication are to realize the propagation of various information by fully utilizing wide frequency resources; optical communication is the use of light to enable the propagation of information. However, in communication, information needs to be completely, reliably and timely transmitted, and simultaneously, required information needs to be completely and timely received, so that the duplexer is an indispensable device and is a key device for the complete equipment to complete the transceiving function.

As rapid development of wireless communication technology puts higher demands on the size of duplexers, it is expected that miniaturization will be increasingly performed while maintaining original performance.

The utility model provides a great and the relatively higher problem of manufacturing cost of the great and manufacturing cost of duplexer overall dimension of solving prior art, provide a semiconductor device's packaging structure and electronic equipment, through setting up first device and second device into upper and lower floor overlapping structure, can be so that the overall dimension after the encapsulation is less to because the less required base plate of overall dimension and the material of packaging body are also less relatively, thereby reduced manufacturing cost.

The package structure of the semiconductor device provided by the present application may be applied to a duplexer device, and may also be applied to other semiconductor devices, which is not limited in this application.

The package structure of the semiconductor device of the present application is described below with reference to fig. 2 to 4.

Fig. 2 is a schematic diagram of a package structure of a semiconductor device provided in the present application, as shown in fig. 2. A packaging structure of a semiconductor device comprises a substrate 101, a packaging body 102, a first device 103 and a second device 104.

The substrate 101 may be a printed circuit board, or may be various substrates for a package, such as a lead frame. The substrate 101 is internally provided with a wiring layer and the substrate 101 has opposite first and second surfaces. The first surface of the base member 101 has a conductive pattern region for making electrical connection with a semiconductor device. It should be noted that the wiring layer of the substrate 101 in the drawings is only schematic and is not a real connection relationship.

The first surface of the substrate 101 has a groove for placing the first device 103, and the size of the groove matches with the size of the first device 103, and may be specifically set according to actual requirements, and the present application is not limited, for example, the depth of the groove may be smaller than the height of the first device 103.

Illustratively, the first device 103 is electrically connected to the conductive pattern region of the first surface of the substrate 101.

Illustratively, the second device 104 is located on a side near the first surface of the substrate 101 and has a spacing from the first device 103 to facilitate isolation of the first device 103 from the second device 104. The second device 104 is electrically connected to the conductive pattern region of the first surface of the substrate 101. The projections of the first device 103 and the second device 104 on the first surface of the substrate 101 have an overlapping portion.

Exemplarily, the first device 103 may be a receive filter RX, and the second device 104 may be a transmit filter TX; or the first device 103 is a transmit filter TX and the second device 104 is a receive filter RX. In the present application, the types of the first device 103 and the second device 104 are not limited, but in practice, the first device 103 having a smaller size and the second device 104 having a larger size are preferable.

Illustratively, the package body 102 is used to encapsulate a first device 103 and a second device 104 to form a package having a plurality of semiconductor devices.

Therefore, the first device 103 and the second device 104 of the present application are in an upper-lower layer overlapping structure, and the structure can keep the original performance, so that the size of the packaged device is smaller, the substrate utilization rate is improved, and the manufacturing cost is reduced.

The package structure of the above semiconductor device is described below by two specific embodiments.

The first embodiment is as follows:

fig. 3 is a cross-sectional view of a package structure of a semiconductor device according to a first embodiment of the present application, as shown in fig. 3. A packaging structure of a semiconductor device comprises a substrate 101, a packaging body 102, a first device 103 and a second device 104.

Illustratively, the substrate 101 has a first surface 1011 and a second surface 1012, a recess 1013 on the first surface 1011, and the conductive pattern 110 around the recess 1013. The conductive pattern region 110 may include a bonding region that may allow the semiconductor device to communicate with a pad of the substrate by means of bonding and a wire bonding region that may allow the semiconductor device to communicate with the substrate by means of wire bonding. The soldering region can realize the conductive connection of the first device 103, the second device 104 and the substrate 101, and can also realize the conductive connection of other devices; the wire bonding region may realize conductive connection of other devices in addition to the first device 103 and the second device 104 to the substrate 101.

As can be seen from fig. 3, a wiring layer is provided inside the substrate 101 so that the wiring inside the substrate 101 can be electrically connected to the conductive pattern region 110 of the first surface 1011.

The material of the substrate 101 includes copper foil and substrate plate material, and the substrate plate material can be a copper clad plate of a PCB, such as a hard substrate, a flexible film substrate and a ceramic substrate. The material of the hard substrate can be BT material, ABF material, MIS material and the like; the material of the flexible film substrate can be PI (polyimide), PE (polyester) resin and other materials; the material of the ceramic substrate may be a ceramic material such as alumina, aluminum nitride, or silicon carbide.

Illustratively, the first device 103 is disposed in the recess 1013, and as can be seen in FIG. 3, the first device 103 is disposed in the recess 1013 and protrudes slightly toward the first surface 1011, it being seen that the height of the first device 103 may be greater than the depth of the recess 1013. In practical applications, the size of the recess 1013 is not limited, as long as the recess can be adapted to the first device 103.

The first device 103 is electrically connected to the conductive pattern region 110 of the first surface 1011 of the substrate 101 by wire bonding. Fig. 3 shows first device 103 connected to a conductive pattern region 110 of a first surface 1011 of substrate 101 by first bonding wires 108.

The wire bonding mode is a connection mode in which two bonding regions are electrically connected through a metal wire, and the flip-chip mode is a connection mode in which a device is flip-chip mounted on a substrate and electrically connected to the substrate.

Specifically, one end of the first bonding wire 108 is electrically connected to the conductive pattern region 110 of the first surface 1011 of the substrate 101, and the other end is electrically connected to the first device 103. The other end of the first bonding wire 108 in fig. 3 is electrically connected to the first device 103 through a small metal ball to achieve wire bonding to the substrate 101. The first bonding wire 108 may be any one of a gold wire, a copper wire, an aluminum wire, and a silver wire, or may be other conductive materials, which is not limited in this application.

It should be noted that fig. 3 shows that the first device 103 is electrically connected to the substrate 101 through two first bonding wires 108, but the number of the first bonding wires 108 is not limited in the present application, and may be determined according to practical applications.

Illustratively, the second device 104 is located on a side close to the first surface 1011 of the substrate 101 and spaced apart from the first device 103, and the second device 104 may be electrically connected to the conductive pattern region 110 of the first surface 1011 of the substrate 101 by wire bonding or flip chip.

Specifically, the package structure of the semiconductor device of the present application further includes a plurality of connectors 105, each connector 105 is located between the first surface 1011 of the substrate 101 and the lower surface of the second device 104, and the plurality of connectors 105 can be used for supporting the second device 104 and for conducting the second device 104 and the substrate 101. One end of the connecting member 105 may be electrically connected to the conductive pattern region 110 on the first surface 1011 of the substrate 101 through the solder balls 106, and the other end is electrically connected to the surface of the second device 104 close to the first device 103 to realize electrical connection to the substrate 101 in a flip chip manner. The flip-chip mode is any one of solder welding, hot-press welding, thermoacoustic welding and adhesive connection. The flip-chip auxiliary material of the second device 104 and the substrate 101 may be flux or solder paste.

Further, the connecting member 105 may be a pillar or other shape, and the material thereof is any one of copper, nickel, tin, and silver, for example, the connecting member 105 may be a copper pillar. The connecting member 105 may be made of other conductive materials, which is not limited in this application. It is understood that the second device 104 may also be electrically connected to the substrate 101 directly through the solder balls 106. The solder balls 106 may be lead or lead-free solder balls.

It can be seen that the first device 103 is electrically connected to the substrate 101 through the first bonding wires 108, and the second device 104 located above the first device 103 and isolated from the first device 103 is electrically connected to the substrate 101 through the connecting member 105, so that the overall size of the package is reduced and the manufacturing cost is also reduced because the first device 103 and the second device 104 form an overlapping structure of upper and lower layers.

Example two:

fig. 4 is a cross-sectional view of a package structure of a semiconductor device according to a second embodiment of the present application, as shown in fig. 4. A packaging structure of a semiconductor device comprises a substrate 101, a packaging body 102, a first device 103 and a second device 104. The substrate 101, the package 102, and the first device 103 may refer to the technical solutions of the above embodiments, and are not described herein again.

The second embodiment differs from the first embodiment in that the second device 104 is electrically connected to the corresponding conductive pattern region 110 on the first surface 1011 of the substrate 101 through the second bonding wire 109. And since the second embodiment has no supporting function of the connecting member, the second embodiment further includes a glue coating layer 107, the glue coating layer 107 is located between the first device 103 and the second device 104, the first bonding wire 108 is wrapped by the glue coating layer 107, and the glue coating layer 107 can be used for supporting the second device 104 and enabling the second device 104 to have a space with the first device 103. Thus, the cover layer 107 may serve not only as a support but also as a fixation, for example to fix the second component 104 to the substrate 101.

In order to achieve isolation of the first device 103 from the second device 104, such that mutual signal transmission is not subject to crosstalk, the length of the glue-coated layer 107 at the first surface 1011 of the substrate 101 may be designed to be larger than the length of the first device 103. The material of the adhesive layer 107 may be epoxy resin or adhesive film type non-conductive adhesive.

Specifically, one end of the second bonding wire 109 is electrically connected to the conductive pattern region 110 on the first surface 1011 of the substrate 101, and the other end can be electrically connected to the second device 104 through a metal ball, so as to realize the electrical connection to the substrate 101 by wire bonding.

Fig. 4 shows that the first device 103 is in communication with the substrate 101 via two first bonding wires 108, and the second device 104 is also in communication with the substrate 101 via two second bonding wires 109. However, the number of the first bonding wires 108 and the second bonding wires 109 is not limited in the present application, and may be determined according to actual requirements.

The first device 103 is electrically connected to the substrate 101 through a first bonding wire 108. Specifically, one end of the first bonding wire 108 is electrically connected to the conductive pattern region 110 on the first surface 1011 of the substrate 101, and the other end is electrically connected to the first device 103 through one metal pellet.

It can be seen that the first device 103 is electrically connected to the substrate 101 through the first bonding wires 108, and the second device 104 located above the first device 103 and spaced apart from the first device 103 is also electrically connected to the substrate 101 through the second bonding wires 109, so that the first device 103 and the second device 104 form an upper-lower overlapping structure, thereby reducing the overall size of the package and the manufacturing cost.

The present application further provides an electronic device, where the electronic device includes the semiconductor device package structure as described above, the semiconductor device package structure is a duplexer, and the electronic device may be a communication device that needs to be configured with the duplexer.

The following describes a manufacturing process of the package structure of the semiconductor device according to the present application.

For example, the manufacturing process of the second embodiment is described above. Firstly, a concave groove body, namely a groove for mounting a first device is formed on a provided substrate in a laser or etching mode. The first device is then mounted in the recess of the substrate using glue and the first device is connected to the substrate using a wire bonding process. In order to protect the leads from damage, a glue-coating layer may be provided between the first device and the second device. Finally, the second device is flip-chip bonded to the adhesive layer, and the second device is also connected to the substrate using a wire bonding process. And after the first device and the second device are pasted with the patches, performing injection molding and completing packaging.

In contrast, in the first embodiment, a copper pillar needs to be disposed on the substrate, and two ends of the copper pillar are respectively soldered to the pad of the second device and the pad of the substrate. And after welding, performing injection molding on the first device and the second device, and completing packaging.

The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A package structure of a semiconductor device, comprising:

an encapsulation for encapsulating the first device and the second device.

2. The package structure of a semiconductor device according to claim 1, further comprising:

3. The package structure of a semiconductor device according to claim 2, further comprising:

4. The package structure of a semiconductor device according to any one of claims 1 to 2, further comprising:

and a plurality of connectors located between the first surface of the substrate and the second device, wherein one end of each connector is electrically connected with the conductive pattern region of the first surface of the substrate, and the other end of each connector is electrically connected with the surface of the second device close to the first device.

5. The package structure of a semiconductor device according to claim 4, wherein the connecting member is any one of a copper pillar, a nickel pillar, a tin pillar, and a silver pillar.

6. The package structure of a semiconductor device according to claim 2, further comprising:

7. The package structure of a semiconductor device according to claim 6, wherein the first bonding wire or the second bonding wire is any one of a gold wire, a copper wire, an aluminum wire, and a silver wire.

8. The semiconductor device package structure according to claim 1, wherein the semiconductor device package structure is a duplexer.

9. The package structure of a semiconductor device according to claim 8, wherein the first device is a reception filter, and the second device is a transmission filter; or the first device is a transmitting filter and the second device is a receiving filter.

10. An electronic device, characterized in that the electronic device comprises the package structure of the semiconductor device according to any one of claims 1 to 9.