CN220368611U - Voltage regulating circuit suitable for parallel output - Google Patents
Voltage regulating circuit suitable for parallel output Download PDFInfo
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- CN220368611U CN220368611U CN202321653833.9U CN202321653833U CN220368611U CN 220368611 U CN220368611 U CN 220368611U CN 202321653833 U CN202321653833 U CN 202321653833U CN 220368611 U CN220368611 U CN 220368611U
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- 230000001105 regulatory effect Effects 0.000 title claims abstract description 44
- 239000003990 capacitor Substances 0.000 claims abstract description 85
- 238000005070 sampling Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Abstract
The utility model provides a voltage regulating circuit suitable for parallel output, which comprises a first resistor, wherein the end a of the first resistor is connected with the end a of an AUX-A1 and a sixth resistor, the end b of a seventh resistor, the end a of a fifth capacitor and the end c of a first operational amplifier; the b terminal of the first resistor is connected to the a terminal of the first capacitor, the a terminal of the first voltage reference, the a terminal of the second resistor, and the a terminal of the eighth resistor. The set voltage is output to the voltage regulating TRIM pin of the module by utilizing the first operational amplifier and the second operational amplifier, meanwhile, if the module is in fault, the fault indication ports IOG-A1 and IOG-A2 are converted from high level to low level, the first MOS tube and the third MOS tube are cut off, the corresponding modules are not regulated, and the continuous voltage regulating function is realized.
Description
Technical Field
The utility model relates to the field of voltage regulating circuits, in particular to a voltage regulating circuit suitable for parallel output.
Background
With the development of electronics technology, the requirements on power supply power of products are higher and higher, and under such circumstances, various requirements are also put on the power supply used. In power supply, it is often encountered that a plurality of modules are required to be connected in parallel to increase output power, and output needs to adjust voltage as required.
However, the existing voltage regulating circuit still needs to be improved in the use process, namely, the existing voltage regulating circuit cannot connect a plurality of modules in parallel in the power supply process so as to improve the output power, and meanwhile, the voltage cannot be regulated according to the requirement in the output process. Therefore, we make improvements to this and propose a voltage regulating circuit suitable for parallel output.
Disclosure of Invention
The utility model aims at: aiming at the problems of the prior art, the utility model provides the following technical proposal for realizing the purpose of the utility model: the voltage regulating circuit suitable for parallel output comprises a first resistor, wherein the end a of the first resistor is connected with an AUX-A1 end, the end a of a sixth resistor, the end b of a seventh resistor, the end a of a fifth capacitor and the end c of a first operational amplifier; the b end of the first resistor is connected with the a end of the first capacitor, the a end of the first voltage reference, the a end of the second resistor and the a end of the eighth resistor; the c end of the first voltage reference is connected with the b end of the second resistor, the a end of the third resistor and the a end of the second capacitor; the b end of the first capacitor is connected with the b end of the first voltage reference, the b end of the third resistor, the b end of the second capacitor, the a-VO-, the a end of the third capacitor and the b end of the first operational amplifier; TRIM-A1 is connected with the end a of the fourth resistor; the end b of the fourth resistor is connected with the end a of the first MOS tube.
As a preferable technical scheme of the utility model, the c end of the first MOS tube is connected with the a end of the second MOS tube, the a end of the seventh capacitor and the a end of the seventh resistor; the end b of the first MOS tube is connected with the end a and the end e of the first operational amplifier; the b end of the third capacitor is connected with the d end of the first operational amplifier and the a end of the fifth resistor; ext> theext> IOGext> -ext> Aext> isext> connectedext> withext> theext> bext> endext> ofext> theext> sixthext> resistorext>,ext> theext> aext> endext> ofext> theext> sixthext> capacitorext> andext> theext> cext> endext> ofext> theext> secondext> MOSext> tubeext>.ext>
As a preferable technical scheme of the utility model, the b end of the fifth resistor is connected with the a end of the fourth capacitor, the b end of the RP-tenth resistor and the a end of the eleventh capacitor; the b terminal of the eighth resistor is connected with the RP-; the A-VO-is connected with the b end of the fifth capacitor, the b end of the sixth capacitor, the b end of the second MOS tube, the b end of the seventh capacitor and the b end of the fourth capacitor; TRIM-A2 is connected to the a-terminal of the ninth resistor.
As a preferable technical scheme of the utility model, the b end of the ninth resistor is connected with the a end of the third MOS tube; the c end of the third MOS tube is connected with the a end of the fourth MOS tube, the a end of the twelfth resistor and the a end of the tenth capacitor; the end b of the third MOS tube is connected with the end a and the end e of the second operational amplifier; the A2-VO-is connected with the b end of the second operational amplifier and the a end of the eighth capacitor.
As a preferable technical scheme of the utility model, the b end of the eighth capacitor is connected with the d end of the second operational amplifier and the a end of the tenth resistor; AUX-A2 is connected to the a terminal of the eleventh resistor, the c terminal of the a terminal second operational amplifier of the ninth capacitor, and the b terminal of the twelfth resistor.
As the preferable technical scheme of the utility model, the utility model also comprises an IOG-A2, wherein the IOG-A2 is connected with the b end of the eleventh resistor, the a end of the tenth capacitor and the c end of the fourth MOS tube; the A2-VO-is connected with the b end of the ninth capacitor, the b end of the tenth capacitor, the b end of the fourth MOS tube, the b end of the eleventh capacitor and the b end of the twelfth capacitor.
As a preferable technical scheme of the utility model, the utility model further comprises sampling ports, wherein the sampling ports comprise auxiliary source ports AUX-A1 and AUX-A2, and the meanings are as follows: AUX-A1 is the positive electrode of the module auxiliary source; AUX-A2 is the positive electrode of another module auxiliary source.
As the preferable technical scheme of the utility model, the utility model also comprises pressure regulating ports TRIM-A1 and TRIM-A2, wherein the pressure regulating ports TRIM-A1 and TRIM-A2 have the following meanings: TRIM-A1 is a module voltage regulating port; TRIM-A2 is the voltage regulation port of another module, and fault indication port IOG-A1 is the fault indication port of module, and IOG-A2 is the fault indication port of another module.
As a preferable technical scheme of the utility model, the far-end compensating negative terminals A1-VO-are far-end compensating negative terminals of the DC-DC converter; the two voltage regulating ends RP1-1 and RP1-2 are one ends of a mode voltage regulating port and an RP1-1 potentiometer, and the RP1-2 is the other end of the potentiometer.
As a preferable technical scheme of the utility model, the meanings of the end a, the end b, the end c and the end d of the first MOS tube, the second MOS tube and the third MOS tube are as follows: the terminal a is the source electrode of the MOS, the terminal b is the drain electrode of the MOS, the terminal c is the grid electrode of the MOS, and the meanings of the terminal a, the terminal b, the terminal c, the terminal d and the terminal e of the first operational amplifier and the second operational amplifier are as follows: the terminal a is the output terminal of the operational amplifier, the terminal b is the positive input terminal of the power supply of the operational amplifier, the terminal c is the negative electrode of the operational amplifier, the terminal d is the reference positive electrode of the operational amplifier, and the terminal e is the reference negative electrode of the operational amplifier.
Compared with the prior art, the utility model has the beneficial effects that:
in the scheme of the utility model: the set voltage is output to the voltage regulating TRIM pin of the module by utilizing the first operational amplifier and the second operational amplifier, meanwhile, if the module is in fault, the fault indication ports IOG-A1 and IOG-A2 are converted from high level to low level, the first MOS tube and the third MOS tube are cut off, the corresponding modules are not regulated, and the continuous voltage regulating function is realized.
Description of the drawings:
FIG. 1 is a schematic diagram of a novel output power down delay start circuit of the present utility model.
The figures indicate:
1-first resistor, 2-first capacitor, 3-first voltage reference, 4-second resistor, 5-third resistor, 6-second capacitor, 7-fourth resistor, 8-first MOS transistor, 9-first operational amplifier, 10-third capacitor, 11-fifth resistor, 12-sixth resistor, 13-second MOS transistor, 14-seventh resistor, 15-fourth capacitor, 16-eighth resistor, 17-fifth capacitor, 18-sixth capacitor, 19-seventh capacitor, 20-ninth resistor, 21-third MOS transistor, 22-second operational amplifier, 23-eighth capacitor, 24-tenth resistor, 25-eleventh resistor, 26-twelfth resistor, 27-ninth capacitor, 28-tenth capacitor, 29-fourth MOS transistor, 30-eleventh capacitor, 31-twelfth capacitor.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present utility model more clear, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings. It is clear that the described embodiment is a specific implementation of the utility model and is not limited to all embodiments.
Thus, the following detailed description of the embodiments of the utility model is not intended to limit the scope of the utility model, as claimed, but is merely representative of some embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be noted that, without conflict, the embodiments of the present utility model and features and technical solutions of the embodiments may be combined with each other, and it should be noted that like reference numerals and letters denote like items in the following figures, so once a certain item is defined in one figure, no further definition or explanation is needed in the following figures.
Examples: referring to fig. 1, a voltage regulating circuit suitable for parallel output includes a first resistor 1, an a terminal of the first resistor 1 is connected with an AUX-A1, an a terminal of a sixth resistor 12, a b terminal of a seventh resistor 14, an a terminal of a fifth capacitor 17, and a c terminal of a first operational amplifier 9; the b end of the first resistor 1 is connected with the a end of the first capacitor 2, the a end of the first voltage reference 3, the a end of the second resistor 4 and the a end of the eighth resistor 16; the c end of the first voltage reference 3 is connected with the b end of the second resistor 4, the a end of the third resistor 5 and the a end of the second capacitor 6; the b end of the first capacitor 2 is connected with the b end of the first voltage reference 3, the b end of the third resistor 5, the b end of the second capacitor 6, the a end of the A1-VO-, the third capacitor 10 and the b end of the first operational amplifier 9; TRIM-A1 is connected to the a terminal of the fourth resistor 7; the b end of the fourth resistor 7 is connected with the a end of the first MOS tube 8.
The c end of the first MOS tube 8 is connected with the a end of the second MOS tube 13, the a end of the seventh capacitor 19 and the a end of the seventh resistor 14; the end b of the first MOS tube 8 is connected with the end a and the end e of the first operational amplifier 9; the b end of the third capacitor 10 is connected with the d end of the first operational amplifier 9 and the a end of the fifth resistor 11; the IOG-A1 is connected to the b terminal of the sixth resistor 12, the a terminal of the sixth capacitor 18, and the c terminal of the second MOS transistor 13.
The b terminal of the fifth resistor 11 is connected to the a terminal of the fourth capacitor 15, RP1-1, the b terminal of the tenth resistor 24, the a terminal of the eleventh capacitor 30; the b terminal of the eighth resistor 16 is connected to RP 1-2; the A1-VO-is connected with the b end of the fifth capacitor 17, the b end of the sixth capacitor 18, the b end of the second MOS tube 13, the b end of the seventh capacitor 19 and the b end of the fourth capacitor 15; TRIM-A2 is connected to the a-terminal of the ninth resistor 20.
The b end of the ninth resistor 20 is connected with the a end of the third MOS tube 21; the c end of the third MOS tube 21 is connected with the a end of the fourth MOS tube 29, the a end of the twelfth resistor 26 and the a end of the tenth capacitor 28; the b end of the third MOS tube 21 is connected with the a end and the e end of the second operational amplifier 22; the A2-VO-is connected to the b terminal of the second operational amplifier 22 and the a terminal of the eighth capacitor 23.
The b terminal of the eighth capacitor 23 is connected to the d terminal of the second operational amplifier 22 and the a terminal of the tenth resistor 24; AUX-A2 is connected to the a-terminal of the eleventh resistor 25, the c-terminal of the second operational amplifier 22 of the a-terminal of the ninth capacitor 27, and the b-terminal of the twelfth resistor 26.
IOG-A2, IOG-A2 is connected with the b end of the eleventh resistor 25, the a end of the tenth capacitor 28 and the c end of the fourth MOS tube 29; the A2-VO-is connected with the b end of the ninth capacitor 27, the b end of the tenth capacitor 28, the b end of the fourth MOS transistor 29, the b end of the eleventh capacitor 30 and the b end of the twelfth capacitor 31. Also included are sampling ports, which include auxiliary source ports AUX-A1, AUX-A2, meaning: AUX-A1 is the positive electrode of the module auxiliary source; AUX-A2 is the positive electrode of another module auxiliary source.
The pressure regulating ports TRIM-A1 and TRIM-A2, and the pressure regulating ports TRIM-A1 and TRIM-A2 have the following meanings: TRIM-A1 is a module voltage regulating port; TRIM-A2 is the voltage regulation port of another module, and fault indication port IOG-A1 is the fault indication port of module, and IOG-A2 is the fault indication port of another module.
The two remote compensation negative terminals A1-VO-, A2-VO-are the remote compensation negative terminals of the module; A1-VO-is the far-end compensating negative terminal of the DC-DC converter, A2-VO-is the far-end compensating negative terminal of the other DC-DC converter; the two voltage regulating ends RP1-1 and RP1-2 are one ends of the analog voltage regulating port and the RP1-1 potentiometer, and the RP1-2 is the other end of the potentiometer.
The meanings of the a end, the b end, the c end and the d end of the first MOS tube 8, the second MOS tube 13 and the third MOS tube 21 are as follows: the a terminal is the source of the MOS, the b terminal is the drain of the MOS, the c terminal is the gate of the MOS, the meanings of the a terminal, the b terminal, the c terminal, the d terminal and the e terminal of the first operational amplifier 9 and the second operational amplifier 22 are as follows: the terminal a is the output terminal of the operational amplifier, the terminal b is the positive input terminal of the power supply of the operational amplifier, the terminal c is the negative electrode of the operational amplifier, the terminal d is the reference positive electrode of the operational amplifier, and the terminal e is the reference negative electrode of the operational amplifier.
Working principle: in the using process of the utility model, when the output voltage of the power supply is normal, each parallel module adjusts the output voltage through the output voltage of the end a of the first operational amplifier 9 and the end a of the second operational amplifier 22 which are connected with the TRIM pin. Each path of operational amplifier is powered by an AUX pin of each parallel module. The AUX pin of the module outputs about 12V voltage, +5V voltage is regulated through the a end of the first voltage reference 3, the voltage is divided by the RP1-1 and RP1-2 and then is supplied to the d ends of the first operational amplifier 9 and the second operational amplifier 22 through the eighth resistor 16, and then the voltage of the first operational amplifier 9 and the second operational amplifier 22 is output to the TRIM pin of each module from the a end of the first operational amplifier 9 and the second operational amplifier 22, so that the voltage regulating function is realized.
The IOG pin is a fault signal indicating pin, and is low under normal conditions, and is high when the fault occurs, at this time, the ends of the second MOS tube 13 and the fourth MOS tube 29c are high, the ends a and b are conducted, the ends c of the first MOS tube 8 and the third MOS tube 21 are pulled down, at this time, the ends a and b of the first MOS tube 8 and the third MOS tube 21 are not conducted, the corresponding TRIM voltage regulating pin does not regulate voltage, after the IOG pin is recovered to be normal, the voltage regulating function can be recovered, and the corresponding circuit can be repeated when a plurality of modules are used for regulating voltage.
The utility model discloses a parallel output voltage regulating circuit. The purpose is to solve the voltage regulation problem when a plurality of modules are output in parallel. The circuit has the advantages of accurate control, simple and convenient operation, high response speed and high reliability.
The above embodiments are only for illustrating the present utility model and not for limiting the technical solutions described in the present utility model, and although the present utility model has been described in detail in the present specification with reference to the above embodiments, the present utility model is not limited to the above specific embodiments, and thus any modifications or equivalent substitutions are made to the present utility model; all technical solutions and modifications thereof that do not depart from the spirit and scope of the utility model are intended to be included in the scope of the appended claims.
Claims (10)
1. The voltage regulating circuit suitable for parallel output comprises a first resistor (1), and is characterized in that an a end of the first resistor (1) is connected with an AUX-A1 end, an a end of a sixth resistor (12), a b end of a seventh resistor (14), an a end of a fifth capacitor (17) and a c end of a first operational amplifier (9); the terminal b of the first resistor (1) is connected with the terminal a of the first capacitor (2), the terminal a of the first voltage reference (3), the terminal a of the second resistor (4) and the terminal a of the eighth resistor (16); the c end of the first voltage reference (3) is connected with the b end of the second resistor (4), the a end of the third resistor (5) and the a end of the second capacitor (6); the b end of the first capacitor (2) is connected with the b end of the first voltage reference (3), the b end of the third resistor (5), the b end of the second capacitor (6), the a end of the A1-VO-, the third capacitor (10) and the b end of the first operational amplifier (9); TRIM-A1 is connected with the end a of the fourth resistor (7); the end b of the fourth resistor (7) is connected with the end a of the first MOS tube (8).
2. The voltage regulating circuit suitable for parallel output according to claim 1, wherein the c-terminal of the first MOS transistor (8) is connected with the a-terminal of the second MOS transistor (13), the a-terminal of the seventh capacitor (19) and the a-terminal of the seventh resistor (14); the end b of the first MOS tube (8) is connected with the end a and the end e of the first operational amplifier (9); the b end of the third capacitor (10) is connected with the d end of the first operational amplifier (9) and the a end of the fifth resistor (11); the IOG-A1 is connected with the b end of the sixth resistor (12), the a end of the sixth capacitor (18) and the c end of the second MOS tube (13).
3. A voltage regulating circuit adapted for parallel output according to claim 2, characterized in that the b terminal of the fifth resistor (11) is connected to the a terminal of the fourth capacitor (15), RP1-1, the b terminal of the tenth resistor (24), the a terminal of the eleventh capacitor (30); the b terminal of the eighth resistor (16) is connected with RP 1-2; the A1-VO-is connected with the b end of the fifth capacitor (17), the b end of the sixth capacitor (18), the b end of the second MOS tube (13), the b end of the seventh capacitor (19) and the b end of the fourth capacitor (15); TRIM-A2 is connected to the a terminal of the ninth resistor (20).
4. A voltage regulating circuit adapted for parallel output according to claim 3, wherein the terminal b of the ninth resistor (20) is connected to the terminal a of the third MOS transistor (21); the c end of the third MOS tube (21) is connected with the a end of the fourth MOS tube (29), the a end of the twelfth resistor (26) and the a end of the tenth capacitor (28); the end b of the third MOS tube (21) is connected with the end a and the end e of the second operational amplifier (22); A2-VO-is connected with the b end of the second operational amplifier (22) and the a end of the eighth capacitor (23).
5. A voltage regulating circuit adapted for parallel output according to claim 4, characterized in that the b terminal of the eighth capacitor (23) is connected to the d terminal of the second operational amplifier (22) and the a terminal of the tenth resistor (24); AUX-A2 is connected to the a terminal of the eleventh resistor (25), the c terminal of the second operational amplifier (22) of the a terminal of the ninth capacitor (27), and the b terminal of the twelfth resistor (26).
6. The voltage regulating circuit for parallel output according to claim 5, further comprising an IOG-A2, the IOG-A2 being connected to the b terminal of the eleventh resistor (25), the a terminal of the tenth capacitor (28), the c terminal of the fourth MOS transistor (29); the A2-VO-is connected with the b end of the ninth capacitor (27), the b end of the tenth capacitor (28), the b end of the fourth MOS tube (29), the b end of the eleventh capacitor (30) and the b end of the twelfth capacitor (31).
7. The voltage regulating circuit of claim 6, further comprising a sampling port comprising auxiliary source ports AUX-A1, AUX-A2 meaning: AUX-A1 is the positive electrode of the module auxiliary source; AUX-A2 is the positive electrode of another module auxiliary source.
8. The voltage regulator circuit of claim 7, further comprising voltage regulator ports TRIM-A1, TRIM-A2, the voltage regulator ports TRIM-A1, TRIM-A2 meaning: TRIM-A1 is a module voltage regulating port; TRIM-A2 is the voltage regulation port of another module, and fault indication port IOG-A1 is the fault indication port of module, and IOG-A2 is the fault indication port of another module.
9. The voltage regulator circuit of claim 8, further comprising a remote compensated negative terminal A1-VO-; the remote compensation negative terminal A1-VO-is the remote compensation negative terminal of the DC-DC converter; the two voltage regulating ends RP1-1 and RP1-2 are one ends of a mode voltage regulating port and an RP1-1 potentiometer, and the RP1-2 is the other end of the potentiometer.
10. The voltage regulating circuit according to claim 9, wherein the meaning of the a end, the b end, the c end and the d end of the first MOS tube (8), the second MOS tube (13) and the third MOS tube (21) is: the terminal a is the source electrode of the MOS, the terminal b is the drain electrode of the MOS, the terminal c is the grid electrode of the MOS, the meanings of the terminal a, the terminal b, the terminal c, the terminal d and the terminal e of the first operational amplifier (9) and the second operational amplifier (22) are as follows: the terminal a is the output terminal of the operational amplifier, the terminal b is the positive input terminal of the power supply of the operational amplifier, the terminal c is the negative electrode of the operational amplifier, the terminal d is the reference positive electrode of the operational amplifier, and the terminal e is the reference negative electrode of the operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321653833.9U CN220368611U (en) | 2023-06-28 | 2023-06-28 | Voltage regulating circuit suitable for parallel output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321653833.9U CN220368611U (en) | 2023-06-28 | 2023-06-28 | Voltage regulating circuit suitable for parallel output |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220368611U true CN220368611U (en) | 2024-01-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321653833.9U Active CN220368611U (en) | 2023-06-28 | 2023-06-28 | Voltage regulating circuit suitable for parallel output |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220368611U (en) |
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2023
- 2023-06-28 CN CN202321653833.9U patent/CN220368611U/en active Active
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