CN205092772U - Linear regulator control circuit - Google Patents
Linear regulator control circuit Download PDFInfo
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- CN205092772U CN205092772U CN201520761951.0U CN201520761951U CN205092772U CN 205092772 U CN205092772 U CN 205092772U CN 201520761951 U CN201520761951 U CN 201520761951U CN 205092772 U CN205092772 U CN 205092772U
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Abstract
The utility model relates to a linear regulator control circuit. The linear regulator circuit includes the power transistor who is coupled between input voltage node and output voltage node. This linear regulator's control circuit includes the feedback network, and this feedback network has the input that is coupled to this output voltage node and is configured as the output that is used for generating feedback voltage. Error amplifier receipt reference voltage and this feedback voltage are in order to generate error signal. This error signal is received and have the output that is coupled with the control terminal that drives this power transistor to the driver circuit. The first power supply terminal of this driver circuit is coupled to first power node to the second source terminal of this driver circuit is coupled to this output voltage node. A low quiescent current operation for operating the bias current of this driver circuit correspondingly directly drawn to this output voltage node in order supporting this regulator circuit.
Description
Technical field
The utility model relates to linear regulator circuit, and relates to the linear regulator circuit with low quiescent current consumption characteristics particularly.
Background technology
Need a kind of linear regulator circuit that can keep the improvement of load-carrying ability while the electric current saving drive circuit in the art.Will preferably, no matter need how many output currents, linear regulator circuit all operates with the current drain reduced.
Utility model content
In an embodiment, the linear regulator control circuit be configured to for controlling to be coupled to the power transistor between input voltage node and output voltage node comprises: feedback network, and this feedback network has the input being coupled to this output voltage node and the output be configured to for generating feedback voltage; Error amplifier, this error amplifier has the first input end be configured to for receiving reference voltage and the second input be configured to for receiving this feedback voltage; And drive circuit, this drive circuit has the input of the output being coupled to this error amplifier and is coupled to drive the output of the control terminal of this power transistor, this drive circuit to have the first power supply terminal being coupled to the first power supply node and the second source terminal being coupled to this output voltage node.
According to an embodiment, described feedback network is coupled between described output voltage node and second source node.
According to an embodiment, described error amplifier has the first power supply terminal being coupled to described first power supply node and the second source terminal being coupled to second source node.
According to an embodiment, described first power supply node is positive supply node and described second source node is earthing power supply node.
According to an embodiment, described drive circuit comprises: buffer amplifier circuit, and described buffer amplifier circuit has the differential input transistor pair being connected to tail current source at common node place; Wherein, described differential input transistor is to being coupled to described first power supply terminal; And wherein, described tail current source is coupled to described second source terminal.
According to an embodiment, described drive circuit comprises: source follower transistor; And bias current transistor; Wherein, described source follower transistor and bias current transistor by coupled in series between described first power supply terminal and described second source terminal.
According to an embodiment, described drive circuit operates in response to by being pulled to the bias current of described first power supply terminal from described first power supply node, and described bias current exports from described drive circuit at described second source terminal place and is applied to described output voltage node.
According to an embodiment, described drive circuit is applied to described output voltage node at the bias current at described second source terminal place.
In an embodiment, the linear regulator control circuit be configured to for controlling to be coupled to the power transistor between input voltage node and output voltage node comprises: feedback network, and this feedback network has the input being coupled to this output voltage node and the output be configured to for generating feedback voltage; Error amplifier, this error amplifier has the first input end be configured to for receiving reference voltage and the second input be configured to for receiving this feedback voltage; And drive circuit, this drive circuit has the input of the output being coupled to this error amplifier and is coupled to drive the output of the control terminal of this power transistor, and this drive circuit comprises the amplifier circuit be coupled between the first power supply terminal and second source terminal; Wherein, the described second source terminal of this drive circuit is connected directly to this output voltage node.
According to an embodiment, described amplifier circuit comprises: differential input transistor pair, and described differential input transistor is connected to tail current source at common node place; Wherein, described differential input transistor is to being coupled to described first power supply terminal; And wherein, described tail current source is coupled to described second source terminal.
According to an embodiment, described drive circuit comprises: source follower transistor, and described source follower transistor is controlled by the output of described amplifier circuit; And bias current transistor; Wherein, described source follower transistor and bias current transistor by coupled in series between described first power supply terminal and described second source terminal.
According to an embodiment, described drive circuit operates in response to the bias current being pulled to described first power supply terminal, and described bias current exports from described drive circuit at described second source terminal place and is applied to described output voltage node.
According to an embodiment, described drive circuit is applied directly to described output voltage node at the bias current at described second source terminal place.
In an embodiment, the linear regulator control circuit be configured to for controlling to be coupled to the power transistor between input voltage node and output voltage node comprises: feedback network, and this feedback network to be coupled between this output voltage node and earthing power supply node and to have the output be configured to for generating feedback voltage; Error amplifier, this error amplifier has the first input end be configured to for receiving reference voltage and the second input be configured to for receiving this feedback voltage, and described error amplifier has the first power supply terminal being connected directly to positive supply node and the second source terminal being connected directly to this earthing power supply node; And drive circuit, this drive circuit has the input of the output being coupled to this error amplifier and is coupled to drive the output of the control terminal of this power transistor, this drive circuit to have the first power supply terminal being connected directly to this positive supply node and the second source terminal being connected directly to this output voltage node.
According to an embodiment, described drive circuit comprises: differential input transistor pair, and described differential input transistor is connected to tail current source at common node place; Wherein, described differential input transistor is to being coupled to described positive supply node; And wherein, described tail current source is connected directly to described output voltage node.
According to an embodiment, described drive circuit comprises: source follower transistor; And bias current transistor; Wherein, described source follower transistor and bias current transistor are by coupled in series, and described source follower transistor is connected directly to described positive supply node and described bias current transistor is directly coupled to described output voltage node.
According to an embodiment, described drive circuit is applied to described output voltage node at the bias current at described second source terminal place.
Accompanying drawing explanation
In order to understand embodiment better, incite somebody to action now only by way of example with reference to accompanying drawing, in the accompanying drawings:
Fig. 1 is the circuit diagram of the embodiment of linear regulator circuit;
Fig. 2 is the circuit diagram of embodiment of the linear regulator circuit with the quiescent current consumption reduced; And
Fig. 3 is the transistor rank circuit diagram of the linear regulator circuit of Fig. 2.
Embodiment
Linear regulator circuit 10 is shown with reference to Fig. 1, Fig. 1.Circuit 10 comprises power transistor 12, and this power transistor has and is coupled to voltage input node (V
input) the first conducting terminal and be coupled to voltage output node (V
export) the second conducting terminal.Power transistor 12 generally includes n trench MOSFET device, thus makes this first conducting terminal be drain node and this second conducting terminal is source node.The control terminal (such as, the gate node of this n trench MOSFET device) of power transistor 12 by the output of drive circuit 14 with voltage (V
grid) drive.Drive circuit 14 has and is connected to positive supply node (V
power supply) positive power terminal and be connected to the negative power source terminal of earthing power supply node (GND).In one implementation, supply voltage and input voltage can be identical voltage.The input of drive circuit 14 is coupled to the output of error amplifier circuit 16, this error amplifier circuit generated error signal Vc.Such as, error amplifier circuit 16 can comprise operation transconductance amplifier (OTA), and this operation transconductance amplifier has and coupled to receive the non-inverting input of reference voltage (Vref) and coupled to receive the inverting input of feedback voltage (Vfb).Error amplifier circuit 16 has and is connected to this positive supply node (V
power supply) positive power terminal and be connected to the negative power source terminal of this earthing power supply node (GND).Feedback circuit network 18 is coupled to this output node V
exportand to provide this feedback voltage Vfb between the second input of amplifier circuit 16.Such as, feedback circuit network 18 can comprise resistive divider circuit, and this resistive divider circuit is by being connected to this output node V
exportand resistor R1 and R2 be connected in series between this earthing power supply node (GND) is formed.The tap node of resistor divider circuit generates this feedback signal Vfb and is coupled to the inverting input of error amplifier circuit 16.Compensating network 20 is coupled between the input of drive circuit 14 and this earthing power supply node (GND) to compensate the stability of feedback loop.Such as, compensating network 20 can comprise being connected in series of resistor R3 and capacitor Cc.
OTA for error amplifier circuit 16 provides the first order of adjuster, and this first order plays the effect of the error voltage difference of amplifying between Vref and Vfb.Error signal Vc through amplifying is imported into drive circuit 14.Drive circuit 14 in response to this error signal Vc with voltage V
gridthe control terminal of driving power transistor 12.During the normal running of linear regulator circuit 10, from power supply (V
power supplyand V
input) total current that transmits provides (wherein, electric current I 1 is the bias current of error amplifier circuit 16, and circuit I 2 is bias currents of drive circuit 14, and circuit I 3 is the electric currents flowing through power transistor 12) by electric current I 1+I2+I3.Be poured into the total current of (GND) provided (wherein, electric current I 5 flows through feedback network 18 electric current to ground) by electric current I 1+I2+I5.The electric current being sent to load is electric current I 4, wherein, and I3=I4+I5.Electric current I 1 is the relatively low current consumed by the operation of OTA.But electric current I 2 is relatively more much bigger than electric current I 1, because drive circuit 14 needs the control terminal (gate capacitance) of driving power transistor 12.The quiescent current of linear regulator 10 is provided by electric current I 1+I2+I5.When requirement not to load, electric current I 4 is zero.Thus the maintenance electric current of linear regulator circuit is also provided by electric current I 1+I2+I5.
Linear regulator circuit 10 is the power-supply systems being widely used in needing in the application of good transient response and low noise.A shortcoming of linear regulator circuit 10 is power efficiencies.Power transistor device has significant power loss.In order to minimize this waste, drive circuit 14 must be powerful to use input voltage V
inputwith output voltage V
exportbetween low voltage difference carry out operating power transistor.In addition, the use support of powerful drive circuit 14 operates such as, linear regulator with good load-carrying ability (e.g., High Output Current, good transient response, good Power Supply Rejection Ratio (PSRR)).But, providing with big current consumption (current drain carrying out Self-bias Current I2 more specifically, needed for function driver circuit 14) as cost of powerful drive circuit.
Although illustrated n channel power MOS FET device in Fig. 1, will be appreciated that linear regulator circuit 10 can but use p channel power MOS FET device.N channel device is selected, because n channel device is more effective than p channel device on the electric current that the size of devices process with less is larger when output current demand is larger.In addition, n channel power MOS FET device will provide good transient response usually.But, by using n channel power MOS FET device, need powerful drive circuit 14 to realize gratifying transient response and operational stability.To the operation of this drive circuit 14 unhappy need large static working current.If linear regulator circuit framework can but support highly reduction static working current, then will be favourable.If when load request is low, linear regulator circuit framework provides low-power to maintain behavior, then will be additionally favourable.
The embodiment of the linear regulator circuit 100 with the quiescent current consumption reduced is shown referring now to Fig. 2, Fig. 2.Circuit 100 comprises power transistor 112, and this power transistor has and is coupled to voltage input node (V
input) the first conducting terminal and be coupled to output voltage node (V
export) the second conducting terminal.Power transistor 112 generally includes n trench MOSFET device, thus makes this first conducting terminal be drain node and this second conducting terminal is source node.The control terminal (such as, the gate node of this n trench MOSFET device) of power transistor 112 is by the output (V of drive circuit 114
grid) drive.Drive circuit 114 has and is connected to positive supply node (V
power supply) positive power terminal and be connected to output node (V
export) negative power source terminal.In one implementation, supply voltage and input voltage can be identical voltage.The input of drive circuit 114 is coupled to the output of error amplifier circuit 116, this error amplifier circuit generated error signal Vc.Such as, error amplifier circuit 116 can comprise operation transconductance amplifier (OTA), and this operation transconductance amplifier has and coupled to receive the non-inverting input of reference voltage (Vref) and coupled to receive the inverting input of feedback voltage (Vfb).Error amplifier circuit 116 has and is connected to this positive supply node (V
power supply) positive power terminal and be connected to the negative power source terminal of earthing power supply node (GND).Feedback circuit network 118 is coupled to this output node V
exportand between the second input of amplifier circuit 116.Such as, feedback circuit network 118 can comprise resistive divider circuit, and this resistive divider circuit is by being connected to this output node V
exportand resistor R1 and R2 be connected in series between this earthing power supply node (GND) is formed.The tap node of resistor divider circuit generates this feedback signal Vfb and is coupled to the inverting input of error amplifier circuit 116.Compensating network 120 is coupled between the input of drive circuit 114 and this earthing power supply node (GND) to compensate the stability of feedback loop.Such as, compensating network 120 can comprise being connected in series of resistor R3 and capacitor Cc.
OTA for error amplifier circuit 116 provides the first order of adjuster, and this first order plays the effect of the error voltage difference of amplifying between Vref and Vfb.The error signal Vc amplified is imported into drive circuit 114.Drive circuit 114 in response to this error signal with voltage V
gridthe control terminal of driving power transistor 112.During the normal running of linear regulator circuit 100, from power supply (V
power supplyand V
input) total current that transmits provides (wherein, electric current I 1 is the bias current of error amplifier circuit 116, and circuit I 2 is bias currents of drive circuit 114, and circuit I 3 is the electric currents flowing through power transistor 112) by electric current I 1+I2+I3.The total current being poured into the ground (GND) in the circuit 100 of Fig. 2 is provided (wherein, electric current I 5 flows through the electric current of feedback network 18 to ground) by electric current I 1+I5.In this Circnit Layout, the bias current I2 for drive circuit 114 is a part for load current, thus makes I2+I3=I4+I5, and wherein, electric current I 4 is the electric currents being sent to load.Thus the quiescent current for linear regulator circuit 100 is provided by electric current I 1+I5.Electric current I 1 is the relatively low current consumed by the operation of OTA.Electric current I 2 is relatively more much bigger than electric current I 1, because drive circuit 114 needs the control terminal of driving power transistor 12.Suppose that the electric current I 4 required for load reduces, this will cause the corresponding reduction of electric current I 2.When requirement not to load, that is, electric current I 4 is zero, and the maintenance electric current of this linear regulator circuit is also provided by electric current I 1+I5.
The transistor rank implementation of the linear regulator circuit 100 based on the framework shown in Fig. 2 is shown referring now to Fig. 3, Fig. 3.V
power supplyit is the positive voltage of the control circuit for adjuster.V
inputneed to be conditioned the input voltage that device regulates.If desired, V
power supplyand V
inputcan be identical voltage.
Error amplifier circuit 116 is the OTA using the one-level folded common source and common grid amplifier design formed by transistor M0, M1, M12, M13, M14, M15, M16 and M17 to realize.Transistor M12 and M13 forms the differential input transistor pair being used for OTA.Electric current I 1 is the right tail current flowing through tail current source CS1 of differential input transistor.Transistor M16 and M17 is configured to current source transistor, and these current source transistors are by bias voltage V
biased _ abe biased.By bias voltage V
biased _ btransistor M14 and M15 that be biased be to provide the cascade device of the voltage bias of the drain terminal for transistor M12, M13, M16 and M17.Transistor M0 and M1 is the load transistor forming current mirroring circuit.The output of error amplifier circuit 116 is got to provide error signal Vc at the drain terminal place of transistor M1 and M15.
Compensating network 120 is formed by the capacitor Cc between the output and earthing power supply node (GND) of error amplifier circuit 116 and being connected in series of resistor R3.
Clamp circuit 130 is by the output and the adjuster output node V that are connected in series in error amplifier circuit 116
exportbetween diode D1 and D2 formed.The negative electrode of diode D1 and D2 is joined together.The anode of diode D1 is connected to the output of error amplifier circuit 116, and the anode of diode D2 (such as, it is Zener diode) is connected to adjuster output node V
export.Clamp circuit 130 plays voltage clamp at Vc and V
exportbetween to protect the effect of the grid of power transistor 112, but it should be noted that about this circuit, V
exportand the voltage between Vc is not by clamp.Those skilled in the art will recognize that, the clamp circuit of any kind that diode D1 and D2 of circuit 130 can be matched by the source voltage ratings with power transistor 112 substitutes.
Drive circuit 114 is formed by current source CS2, diode D0 and transistor M2, M3, M4, M5, M6, M7, M8, M9 and M10.Vc is the input of drive circuit, and V
gridthe output of drive circuit.Diode D0 is the parasitic diode of transistor M7.When the voltage of error signal Vc is lower than output voltage V
exporttime, transistor M7 turns off and diode D0 and transistor M7 protects the grid of input transistors M4 to avoid reverse breakdown.Transistor M2, M3, M4, M5 and M9 form unity gain buffer circuit.The input of this buffer circuits is at the grid place of transistor M4.The output of this buffer circuits is in drain electrode place of transistor M5.Negative feedback is provided by being linked together by the drain and gate of transistor M5.Transistor M4 and M5 forms differential input transistor pair.Transistor M2 and M3 is the load transistor being connected to be formed current mirroring circuit.Transistor M9 is for the right tail current source transistor of this input difference.Transistor M6 is connected as source follower transistor, and its bias current is provided by transistor M10.Current source CS2 is connected to transistor M8 to form bias generator circuit, and this bias generator circuit provides bias current with a kind of relation of current mirror with the driver output stage that transistor M9 and M10 is connected for being formed by transistor M6 and M10.
Feedback network 118 is formed by resistor R1 and R2 be connected in series between output node and earthing power supply node.Tap node between resistor R1 and R2 generates feedback voltage Vfb to put on the grid of the transistor M13 in error amplifier circuit 116.Reference voltage Vref is applied to the grid of transistor M12.
Linear regulator circuit 100 operates as follows:
Output voltage V is sensed by feedback network 118
exportto generate feedback voltage Vfb.Error voltage between Vref and Vfb is amplified with generated error signal Vc by error amplifier circuit 116.Output from the voltage V of drive circuit 114
gridthe voltage of tracking error signal Vc is to control the grid voltage of power transistor 112.By negative feedback loop, feedback voltage Vfb will follow reference voltage Vref, and the output voltage V at output node place
exportbe adjusted to:
V
export=Vref* (Vfb1+Vfb2)/Vfb2, wherein, Vfb1 and Vfb2 is the voltage across resistor R1 and R2 respectively.
Output (the V of departure signal Vc, drive circuit 114 will be carried out for different load currents by feedback loop
grid) and input transistors M4 and M5 in drive circuit 114 public connection on the voltage of node Vs.Electric current I 2_1 is the fixed component not controlled by feedback loop of driver circuit current I2.Electric current I 2_2 and I2_3 is the variable componenent controlled by feedback loop of driver circuit current I2.Electric current I 3 is also the variable current controlled by feedback loop.This control is by control voltage Vs and V
gridperform.
When load current I4 is larger, so: I4=I2_1+I2_2+I2_3+I3-I5.
The voltage V of the output of drive circuit 114
gridbe controlled to meet this equation.But, along with load current I4 reduces, voltage V
gridall reduce along with the reduction of electric current I 4 with electric current I 3, until the gate source voltage of power transistor 112 (Vgs) is lower than its threshold value and electric current I 3 is zero.So: I4=I2_1+I2_2+I2_3-I5.
Along with electric current I 4 still reduces further, feedback loop will reduce voltage Vs and V
grid.Electric current I 2_2 and I2_3 also will reduce, because the drain-source voltage of transistor M9 and M10 reduces.
When I4 is reduced to 0, so: I4=I2_1+I2_2+I2_3-I5=0 and I2_1+I2_2+I2_3=I5.
When the drain-source voltage of transistor M10 and M11 is zero, the minimum value of electric current I 2_2 and I2_3 is zero.But as mentioned above, electric current I 2_1 has not by the fixed value that feedback loop controls.Therefore, because I2_1<=I5, there is constraint.If I2_1>I5, so electric current I 4 can not be zero.
So, importantly it should be noted that the drive circuit 114 in linear regulator circuit 100 is floating drives, the negative power source terminal of this floating drive is connected directly to V
export.So the bias current I2 of drive circuit 114 is also a part for output current.This is different from the linear regulator circuit 10 of Fig. 1, in this linear regulator circuit, and bias current I2 but flow to earthing power supply node.Thus, not only control the grid voltage of power transistor 112 at the voltage of the error signal Vc of the output of error amplifier circuit 116 and the input end of drive circuit 114, but also the bias current of drive circuit is controlled in the scope between electric current I 2_1 and electric current I 2_1+I2_2+I2_3 to provide the minimum current of I2_1.Thus, the bias current of quiescent current by error amplifier circuit 116 of linear regulator circuit 100 and the current definition of feedback network.
Be compared to the circuit of Fig. 1, the disclosed circuit embodiments for linear regulator circuit 100 is with the power efficient operation improved.No matter need how many output currents, lower current drain is provided to the operation of circuit and maintains load-carrying ability simultaneously.Quiescent current for circuit is reduced to the level of the quiescent current lower than the normal two-stage calculation amplifier with identical bandwidth.
By to the complete of exemplary embodiment of the present utility model and informational description exemplary and non-limiting example provide before description.But for those skilled in the relevant art, in view of description above, when reading this specification with appended claims by reference to the accompanying drawings, various amendment and adaptation can become obvious.But, will still fall within scope of the present utility model as determined in appended claims all such and similar amendment of the utility model instruction.
Claims (17)
1. a linear regulator control circuit, is characterized in that, described linear regulator control circuit is configured to for controlling the power transistor be coupled between input voltage node and output voltage node, and described linear regulator circuit comprises:
Feedback network, described feedback network has the input being coupled to described output voltage node and the output be configured to for generating feedback voltage;
Error amplifier, described error amplifier has the first input end be configured to for receiving reference voltage and the second input be configured to for receiving described feedback voltage; And
Drive circuit, described drive circuit has the input of the output being coupled to described error amplifier and is coupled to drive the output of the control terminal of described power transistor, described drive circuit to have the first power supply terminal being coupled to the first power supply node and the second source terminal being coupled to described output voltage node.
2. linear regulator control circuit as claimed in claim 1, it is characterized in that, described feedback network is coupled between described output voltage node and second source node.
3. linear regulator control circuit as claimed in claim 1, it is characterized in that, described error amplifier has the first power supply terminal being coupled to described first power supply node and the second source terminal being coupled to second source node.
4. linear regulator control circuit as claimed in claim 3, it is characterized in that, described first power supply node is positive supply node and described second source node is earthing power supply node.
5. linear regulator control circuit as claimed in claim 1, it is characterized in that, described drive circuit comprises:
Buffer amplifier circuit, described buffer amplifier circuit has the differential input transistor pair being connected to tail current source at common node place;
Wherein, described differential input transistor is to being coupled to described first power supply terminal; And
Wherein, described tail current source is coupled to described second source terminal.
6. linear regulator control circuit as claimed in claim 1, it is characterized in that, described drive circuit comprises:
Source follower transistor; And
Bias current transistor;
Wherein, described source follower transistor and bias current transistor by coupled in series between described first power supply terminal and described second source terminal.
7. linear regulator control circuit as claimed in claim 1, it is characterized in that, described drive circuit operates in response to by being pulled to the bias current of described first power supply terminal from described first power supply node, and described bias current exports from described drive circuit at described second source terminal place and is applied to described output voltage node.
8. linear regulator control circuit as claimed in claim 1, it is characterized in that, described drive circuit is applied to described output voltage node at the bias current at described second source terminal place.
9. a linear regulator control circuit, is characterized in that, described linear regulator control circuit is configured to for controlling the power transistor be coupled between input voltage node and output voltage node, and described linear regulator circuit comprises:
Feedback network, described feedback network has the input being coupled to described output voltage node and the output be configured to for generating feedback voltage;
Error amplifier, described error amplifier has the first input end be configured to for receiving reference voltage and the second input be configured to for receiving described feedback voltage; And
Drive circuit, described drive circuit has the input of the output being coupled to described error amplifier and is coupled to drive the output of the control terminal of described power transistor, and described drive circuit comprises the amplifier circuit be coupled between the first power supply terminal and second source terminal;
Wherein, the described second source terminal of described drive circuit is connected directly to described output voltage node.
10. linear regulator control circuit as claimed in claim 9, it is characterized in that, described amplifier circuit comprises:
Differential input transistor pair, described differential input transistor is connected to tail current source at common node place;
Wherein, described differential input transistor is to being coupled to described first power supply terminal; And
Wherein, described tail current source is coupled to described second source terminal.
11. linear regulator control circuits as claimed in claim 9, it is characterized in that, described drive circuit comprises:
Source follower transistor, described source follower transistor is controlled by the output of described amplifier circuit; And
Bias current transistor;
Wherein, described source follower transistor and bias current transistor by coupled in series between described first power supply terminal and described second source terminal.
12. linear regulator control circuits as claimed in claim 9, it is characterized in that, described drive circuit operates in response to the bias current being pulled to described first power supply terminal, and described bias current exports from described drive circuit at described second source terminal place and is applied to described output voltage node.
13. linear regulator control circuits as claimed in claim 9, is characterized in that, described drive circuit is applied directly to described output voltage node at the bias current at described second source terminal place.
14. 1 kinds of linear regulator control circuits, is characterized in that, described linear regulator control circuit is configured to for controlling the power transistor be coupled between input voltage node and output voltage node, and described linear regulator circuit comprises:
Feedback network, described feedback network to be coupled between described output voltage node and earthing power supply node and to have the output be configured to for generating feedback voltage;
Error amplifier, described error amplifier has the first input end be configured to for receiving reference voltage and the second input be configured to for receiving described feedback voltage, and described error amplifier has the first power supply terminal being connected directly to positive supply node and the second source terminal being connected directly to described earthing power supply node; And
Drive circuit, described drive circuit has the input of the output being coupled to described error amplifier and is coupled to drive the output of the control terminal of described power transistor, described drive circuit to have the first power supply terminal being connected directly to described positive supply node and the second source terminal being connected directly to described output voltage node.
15. linear regulator control circuits as claimed in claim 14, it is characterized in that, described drive circuit comprises:
Differential input transistor pair, described differential input transistor is connected to tail current source at common node place;
Wherein, described differential input transistor is to being coupled to described positive supply node; And
Wherein, described tail current source is connected directly to described output voltage node.
16. linear regulator control circuits as claimed in claim 14, it is characterized in that, described drive circuit comprises:
Source follower transistor; And
Bias current transistor;
Wherein, described source follower transistor and bias current transistor are by coupled in series, and described source follower transistor is connected directly to described positive supply node and described bias current transistor is directly coupled to described output voltage node.
17. linear regulator control circuits as claimed in claim 14, is characterized in that, described drive circuit is applied to described output voltage node at the bias current at described second source terminal place.
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|---|---|---|---|
| CN201520761951.0U CN205092772U (en) | 2015-09-29 | 2015-09-29 | Linear regulator control circuit |
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|---|---|---|---|
| CN201520761951.0U CN205092772U (en) | 2015-09-29 | 2015-09-29 | Linear regulator control circuit |
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| CN114578883A (en) * | 2020-11-30 | 2022-06-03 | 立积电子股份有限公司 | Voltage regulator |
| CN114846429A (en) * | 2019-12-20 | 2022-08-02 | 德克萨斯仪器股份有限公司 | Adaptive bias control for voltage regulator |
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2015
- 2015-09-29 CN CN201520761951.0U patent/CN205092772U/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106558987B (en) * | 2015-09-29 | 2019-12-20 | 意法半导体(中国)投资有限公司 | Low quiescent current linear regulator circuit |
| CN106558987A (en) * | 2015-09-29 | 2017-04-05 | 意法半导体(中国)投资有限公司 | Low quiescent current linear regulator circuit |
| CN108008757A (en) * | 2016-10-27 | 2018-05-08 | 意法设计与应用股份有限公司 | Voltage regulator with bias current boosting |
| CN108008757B (en) * | 2016-10-27 | 2020-07-31 | 意法设计与应用股份有限公司 | Voltage regulator with bias current boost |
| CN108037786A (en) * | 2016-11-03 | 2018-05-15 | 联发科技股份有限公司 | The low-dropout regulator for adjusting voltage is exported for producing |
| CN111742477A (en) * | 2018-03-06 | 2020-10-02 | 德克萨斯仪器股份有限公司 | Multiple input voltage regulator |
| CN112912814A (en) * | 2018-10-31 | 2021-06-04 | 罗姆股份有限公司 | Linear power supply circuit |
| US11550349B2 (en) | 2018-10-31 | 2023-01-10 | Rohm Co., Ltd. | Linear power supply circuit |
| CN112912814B (en) * | 2018-10-31 | 2023-01-03 | 罗姆股份有限公司 | Linear power supply circuit |
| CN113661467B (en) * | 2019-04-12 | 2022-11-18 | 罗姆股份有限公司 | Linear power supply circuit and source follower circuit |
| CN113661467A (en) * | 2019-04-12 | 2021-11-16 | 罗姆股份有限公司 | Linear power supply circuit and source follower circuit |
| CN112187202A (en) * | 2019-07-02 | 2021-01-05 | 立积电子股份有限公司 | Amplifying device |
| CN114846429A (en) * | 2019-12-20 | 2022-08-02 | 德克萨斯仪器股份有限公司 | Adaptive bias control for voltage regulator |
| CN114846429B (en) * | 2019-12-20 | 2024-05-07 | 德克萨斯仪器股份有限公司 | Adaptive bias control for voltage regulators |
| CN114578883A (en) * | 2020-11-30 | 2022-06-03 | 立积电子股份有限公司 | Voltage regulator |
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