CN220325514U - Power supply topological structure of wide-range high-efficiency data center - Google Patents
Power supply topological structure of wide-range high-efficiency data center Download PDFInfo
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Abstract
The utility model discloses a power supply topological structure of a wide-range high-efficiency data center, which comprises a full-bridge LLC circuit, a phase-shifting full-bridge circuit, a direct-current input power supply Vin and an output capacitor C0, wherein the input ends of the full-bridge LLC circuit and the phase-shifting full-bridge circuit are connected with the direct-current input power supply Vin, the full-bridge LLC circuit and the phase-shifting full-bridge circuit share a bridge arm, the output ends of the full-bridge LLC circuit and the phase-shifting full-bridge circuit are respectively connected with one end of the output capacitor C0, and the two ends of the output capacitor C0 are the output ends of the power supply topological structure. The full-bridge LLC circuit is used for working at a fixed frequency, namely a direct current transformer, and bears most of power; the switching frequency of the phase-shifting full-bridge circuit is the same as that of the full-bridge LLC circuit, the output voltage is regulated through phase-shifting control, wide-range output is achieved, and the efficiency is greatly improved while the data center power supply is adapted to various working conditions.
Description
Technical Field
The utility model belongs to the technical field of power electronic converters, and particularly relates to a power supply topological structure of a wide-range high-efficiency data center.
Background
Under the background of double carbon, the data center is a key link of energy conservation and consumption reduction of novel infrastructure, is also a powerful grip for promoting carbon reduction and synergy in the whole society, and has been a trend in green transformation development of the data center. The voltage level required by various CPUs at the tail end of a power supply system of a data center is wider, the existing power supply has the problems of narrow output range, low efficiency and the like, and a plurality of stages of DC/DC converters are required to be regulated to the required voltage level, so that a large amount of electric energy is consumed, and the efficiency is reduced. The DC/DC converter widely used in the present stage is an LLC converter, which has an advantage of high efficiency, but has a problem of a narrow output range.
Disclosure of Invention
The utility model aims to provide a power supply topological structure of a wide-range high-efficiency data center so as to solve the problem of narrow output range of the conventional converter.
The utility model provides a wide-range high efficiency data center power topological structure, including full-bridge LLC circuit, move the full-bridge circuit, direct current input power Vin and output capacitor C0, full-bridge LLC circuit and move the full-bridge circuit and share a bridge arm, full-bridge LLC circuit and move the input of full-bridge circuit and all connect in direct current input power Vin, full-bridge LLC circuit and move the output of full-bridge circuit and connect output capacitor C0's one end respectively, output capacitor C0's both ends are the output of power topological structure.
Preferably, the full-bridge LLC circuit includes a MOS transistor S1, a MOS transistor S2, a resonant inductor Lr1, an excitation inductor Lm, a resonant capacitor Cr, a transformer T1, a MOS transistor Q2, and a filter capacitor C1; the phase-shifting full-bridge circuit comprises an MOS tube S5, an MOS tube S6, leakage inductance Lr2, a transformer T2, an MOS tube Q3, an MOS tube Q4, a filter inductance L0 and a filter capacitor C2; the bridge arm shared by the full-bridge LLC circuit and the phase-shifting full-bridge circuit comprises an MOS tube S3 and an MOS tube S4;
the transformer T1 and the transformer T2 are transformers with secondary sides provided with center taps; the drain electrode of the MOS tube S1, the drain electrode of the MOS tube S3 and the drain electrode of the MOS tube S5 are connected with the positive electrode of the direct current input power supply Vin; the source electrode of the MOS tube S1 is connected with the drain electrode of the MOS tube S2, the source electrode of the MOS tube S3 is connected with the drain electrode of the MOS tube S4, and the source electrode of the MOS tube S5 is connected with the drain electrode of the MOS tube S6; the source electrode of the MOS tube S2, the source electrode of the MOS tube S4 and the source electrode of the MOS tube S6 are connected with the cathode of the direct current input power supply Vin; one end of the resonant inductor Lr1 is connected with the same-name end of the primary side of the transformer T1, and the other end of the resonant inductor Lr1 is connected with the source electrode of the MOS tube S1; the resonance capacitor Cr is connected with the synonym end of the primary side of the transformer T1, and the other end of the resonance capacitor Cr is connected with the source electrode of the MOS tube S3; the excitation inductor Lm is connected with the primary side of the transformer T1 in parallel; one end of the leakage inductance Lr2 is connected with the same-name end of the primary side of the transformer T2, the other end of the leakage inductance Lr2 is connected with the source electrode of the MOS tube S3, and the different-name end of the primary side of the transformer T2 is connected with the source electrode of the MOS tube S5; the same-name end above the secondary side of the transformer T1 is connected with the source electrode of the MOS tube Q1, the different-name end below the secondary side of the transformer T1 is connected with the source electrode of the MOS tube Q2, the drain electrode of the MOS tube Q1 is connected with the drain electrode of the MOS tube Q2, one end of the filter capacitor C1 is connected with a center tap of the transformer T1, and the other end of the filter capacitor C1 is connected with the drain electrode of the MOS tube Q1; the same-name end above the secondary side of the transformer T2 is connected with the source electrode of the MOS tube Q3, the different-name end below the secondary side of the transformer T2 is connected with the source electrode of the MOS tube Q4, the drain electrode of the MOS tube Q3 is connected with the drain electrode of the MOS tube Q4, one end of the filter capacitor C2 is connected with a center tap of the transformer T2, the other end of the filter capacitor C2 is connected with one end of the filter inductor L0, and the other end of the filter inductor L0 is connected with the drain electrode of the MOS tube Q3; one end of the output capacitor C0 is connected with the drain electrode of the MOS tube Q1, and the other end of the output capacitor C0 is connected with a secondary side center tap of the transformer T2; the drain electrode of the MOS tube Q1 is the positive electrode of the output voltage, and the center tap of the secondary side of the transformer T2 is the negative electrode of the output voltage.
Preferably, the switching frequency of the phase-shifted full-bridge circuit is the same as the switching frequency of the full-bridge LLC circuit.
Preferably, a diode and a capacitor are respectively connected between the drain electrode and the source electrode of each of the MOS tube S1, the MOS tube S2, the MOS tube S3, the MOS tube S4, the MOS tube S5 and the MOS tube S6.
Preferably, the anode of the diode is connected with the source electrode of the MOS tube, and the cathode of the diode is connected with the drain electrode of the MOS tube.
Preferably, both the transformer T1 and the transformer T2 are planar transformers.
Preferably, the leakage inductance of the transformers T1 and T2 is integrated into the planar transformer.
Preferably, the primary side of the leakage inductance integrated transformer is connected with the leakage inductance in series, and each layer of PCB is connected with each coil of the primary side and each coil of the secondary side in parallel.
Preferably, the central power supply topology operation sequence is divided into 8 time periods.
Preferably, one end of the output capacitor C0 connected to the drain of the MOS transistor Q1 is at a high level, and the other end of the output capacitor C0 is at a low level.
Compared with the prior art, the utility model has the following beneficial technical effects:
the utility model provides a power supply topological structure of a wide-range high-efficiency data center, which comprises a full-bridge LLC circuit, a phase-shifting full-bridge circuit, a direct-current input power supply Vin and an output capacitor C0, wherein the input ends of the full-bridge LLC circuit and the phase-shifting full-bridge circuit are connected with the direct-current input power supply Vin, the full-bridge LLC circuit and the phase-shifting full-bridge circuit share a bridge arm, the output ends of the full-bridge LLC circuit and the phase-shifting full-bridge circuit are respectively connected with one end of the output capacitor C0, and the two ends of the output capacitor C0 are the output ends of the power supply topological structure. The full-bridge LLC circuit is used for working at a fixed frequency, namely a direct current transformer, and bears most of power; the switching frequency of the phase-shifting full-bridge circuit is the same as that of the full-bridge LLC circuit, the output voltage is regulated through phase-shifting control, wide-range output is achieved, and the efficiency is greatly improved while the data center power supply is adapted to various working conditions.
Drawings
FIG. 1 is a topology diagram of a wide range high efficiency data center power supply in accordance with an embodiment of the present utility model.
FIG. 2 is a timing diagram of a wide range high efficiency data center power supply in accordance with an embodiment of the present utility model.
FIG. 3 illustrates a first topology mode of a wide range high efficiency data center power supply in accordance with an embodiment of the present utility model.
Fig. 4 illustrates a second topology mode of a wide range high efficiency data center power supply in accordance with an embodiment of the present utility model.
Fig. 5 illustrates a third topology mode of a wide range high efficiency data center power supply in accordance with an embodiment of the present utility model.
Fig. 6 illustrates a fourth topology mode of a wide range high efficiency data center power supply in accordance with an embodiment of the present utility model.
Fig. 7 illustrates a fifth topology mode of a wide range high efficiency data center power supply in accordance with an embodiment of the present utility model.
Fig. 8 illustrates a topology mode six of a wide range high efficiency data center power supply in accordance with an embodiment of the present utility model.
Fig. 9 illustrates a topology mode seven of a wide range high efficiency data center power supply in accordance with an embodiment of the present utility model.
FIG. 10 illustrates a topology mode eight of a wide range high efficiency data center power supply in accordance with an embodiment of the present utility model.
Detailed Description
In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As shown in fig. 1, the utility model provides a power topology structure of a wide-range high-efficiency data center, which comprises a full-bridge LLC circuit, a phase-shifting full-bridge circuit, a direct-current input power source Vin and an output capacitor C0, wherein the full-bridge LLC circuit and the phase-shifting full-bridge circuit share one bridge arm, the input ends of the full-bridge LLC circuit and the phase-shifting full-bridge circuit are both connected with the direct-current input power source Vin, the output ends of the full-bridge LLC circuit and the phase-shifting full-bridge circuit are respectively connected with one end of the output capacitor C0, and the two ends of the output capacitor C0 are the output ends of the power topology structure. The full-bridge LLC circuit is used for working at a fixed frequency, namely a direct current transformer, and bears most of power; the switching frequency of the phase-shifting full-bridge circuit is the same as that of the full-bridge LLC circuit, the output voltage is regulated through phase-shifting control, wide-range output is achieved, and the efficiency is greatly improved while the data center power supply is adapted to various working conditions.
1-10, a wide range high efficiency data center power topology is described herein; the full-bridge LLC circuit comprises two parallel bridge arms, the phase-shifting full-bridge circuit comprises two parallel bridge arms, one bridge arm in the phase-shifting full-bridge circuit and one bridge arm in the full-bridge LLC circuit are the same, namely the full-bridge LLC circuit and the phase-shifting full-bridge circuit share three bridge arms, and one or the other of the two bridge arms is the full-bridge LLC circuit or the two bridge arms in the phase-shifting full-bridge circuit.
Specifically, the following description is given with reference to fig. 1: the full-bridge LLC circuit comprises a MOS tube S1, a MOS tube S2, a resonant inductor Lr1, an excitation inductor Lm, a resonant capacitor Cr, a transformer T1, a MOS tube Q2 and a filter capacitor C1; the phase-shifting full-bridge circuit comprises an MOS tube S5, an MOS tube S6, leakage inductance Lr2, a transformer T2, an MOS tube Q3, an MOS tube Q4, a filter inductance L0 and a filter capacitor C2; the bridge arm shared by the full-bridge LLC circuit and the phase-shifting full-bridge circuit comprises an MOS tube S3 and an MOS tube S4;
the transformer T1 and the transformer T2 are transformers with secondary sides provided with center taps; the drain electrode of the MOS tube S1, the drain electrode of the MOS tube S3 and the drain electrode of the MOS tube S5 are connected with the positive electrode of the direct current input power supply Vin; the source electrode of the MOS tube S1 is connected with the drain electrode of the MOS tube S2, the source electrode of the MOS tube S3 is connected with the drain electrode of the MOS tube S4, and the source electrode of the MOS tube S5 is connected with the drain electrode of the MOS tube S6; the source electrode of the MOS tube S2, the source electrode of the MOS tube S4 and the source electrode of the MOS tube S6 are connected with the cathode of the direct current input power supply Vin; one end of the resonant inductor Lr1 is connected with the same-name end of the primary side of the transformer T1, and the other end of the resonant inductor Lr1 is connected with the source electrode of the MOS tube S1; the resonance capacitor Cr is connected with the synonym end of the primary side of the transformer T1, and the other end of the resonance capacitor Cr is connected with the source electrode of the MOS tube S3; the excitation inductor Lm is connected with the primary side of the transformer T1 in parallel; one end of the leakage inductance Lr2 is connected with the same-name end of the primary side of the transformer T2, the other end of the leakage inductance Lr2 is connected with the source electrode of the MOS tube S3, and the different-name end of the primary side of the transformer T2 is connected with the source electrode of the MOS tube S5; the same-name end above the secondary side of the transformer T1 is connected with the source electrode of the MOS tube Q1, the different-name end below the secondary side of the transformer T1 is connected with the source electrode of the MOS tube Q2, the drain electrode of the MOS tube Q1 is connected with the drain electrode of the MOS tube Q2, one end of the filter capacitor C1 is connected with a center tap of the transformer T1, and the other end of the filter capacitor C1 is connected with the drain electrode of the MOS tube Q1; the same-name end above the secondary side of the transformer T2 is connected with the source electrode of the MOS tube Q3, the different-name end below the secondary side of the transformer T2 is connected with the source electrode of the MOS tube Q4, the drain electrode of the MOS tube Q3 is connected with the drain electrode of the MOS tube Q4, one end of the filter capacitor C2 is connected with a center tap of the transformer T2, the other end of the filter capacitor C2 is connected with one end of the filter inductor L0, and the other end of the filter inductor L0 is connected with the drain electrode of the MOS tube Q3; one end of the output capacitor C0 is connected with the drain electrode of the MOS tube Q1, and the other end of the output capacitor C0 is connected with a secondary side center tap of the transformer T2; the drain electrode of the MOS tube Q1 is the positive electrode of the output voltage, and the center tap of the secondary side of the transformer T2 is the negative electrode of the output voltage.
The full-bridge LLC circuit and the phase-shifting full-bridge circuit share one bridge arm, the rectifier circuit on the secondary side of the transformer adopts synchronous rectification, the loss is small, and the full-bridge LLC circuit works at a fixed frequency, namely, the direct-current transformer bears most of power; the switching frequency of the phase-shifting full-bridge circuit is the same as that of the full-bridge LLC circuit, and the output voltage is regulated through phase-shifting control, so that the wide-range output is realized, and the efficiency of the power supply topological structure of the wide-range high-efficiency data center is greatly improved.
According to the power supply topological structure of the wide-range high-efficiency data center, under the condition that parasitic parameters and loss of devices are not considered, the working time sequence of the power supply topological structure is divided into 8 time periods, as shown in fig. 2, the time ranges are t0-t8, the power supply topological structure is analyzed step by step according to different time sequence diagrams, one end of an output capacitor C0 connected with the drain electrode of a MOS tube Q1 is always high level, and the other end of the output capacitor C0 is always low level.
As shown in fig. 1, a diode and a capacitor are respectively connected between the drain electrode and the source electrode of each of the MOS transistor S1, the MOS transistor S2, the MOS transistor S3, the MOS transistor S4, the MOS transistor S5 and the MOS transistor S6, and the diode and the capacitor are connected in parallel; if a diode and a capacitor are connected in parallel between the drain electrode of the MOS tube S1 and the source electrode of the MOS tube S1, the anode of the diode is connected with the source electrode of the MOS tube S1, and the cathode of the diode is connected with the drain electrode of the MOS tube S1.
As shown in fig. 3, modality one, during the period t0-t 1: the MOS tube S1, the MOS tube S4, the MOS tube S5, the MOS tube Q1 and the MOS tube Q4 are opened, the resonance current and the exciting current of the full-bridge LLC circuit are unequal, the current flow of the primary side of the transformer T1 starts from the positive pole of the direct current input power supply Vin, sequentially passes through the MOS tube S1, the resonance inductor Lr1, the exciting inductor Lm, the primary side of the transformer T1, the resonance capacitor Cr and the MOS tube S4, then returns to the negative pole of the direct current input power supply Vin, and the current flow of the secondary side of the transformer T1 starts from the same-name end from the upper part, passes through the MOS tube Q1 and the filter capacitor C1 and returns to the center tap; the current flow direction of the primary side of the phase-shifting full-bridge circuit transformer T2 starts from the positive electrode of the direct current input power supply Vin, sequentially passes through the MOS tube S5, the primary side of the transformer T2, the leakage inductance Lr2 and the MOS tube S4, then returns to the negative electrode of the direct current input power supply Vin, and the current flow direction of the secondary side of the transformer T2 starts from the lower synonym end, passes through the MOS tube Q4, the filter inductance L0 and the filter capacitance C2 and then returns to the center tap; the MOS tube S1 and the MOS tube S4 are turned off, and the mode is finished.
As shown in fig. 4, modality two, during the period t1-t 2: the MOS tube S5 and the MOS tube Q4 are switched on, the resonance current and the excitation current of the full-bridge LLC circuit are equal, the output current is zero at the moment, the primary side and the secondary side are separated, the current flow direction of the primary side resonance inductor Lr1 of the transformer T1 is still consistent with the mode, and at the moment, the capacitors of the MOS tube S2 and the MOS tube S3 are discharged to prepare for switching on the MOS tube S2 and the MOS tube S3 ZVS; the current flow direction of the primary side leakage inductance Lr2 of the phase-shifting full-bridge circuit transformer T2 is still consistent with the mode, at the moment, the capacitor connected with the MOS tube S4 is charged, the capacitor connected with the MOS tube S3 is discharged, preparation is made for opening the MOS tube S3ZVS, the current flow direction of the secondary side of the transformer T2 starts from a lower different name end, and returns to the center tap after passing through the MOS tube Q4, the filter inductor L0 and the filter capacitor C2; the MOS tube S2 and the MOS tube S3 are opened, and the second mode is finished.
As shown in fig. 5, modality three, during the period t2-t 3: the MOS tube S2, the MOS tube S3, the MOS tube S5, the MOS tube Q2, the MOS tube Q3 and the MOS tube Q4 are opened, the resonance current and the exciting current of the full-bridge LLC circuit are unequal, the current flow of the primary side of the transformer T1 starts from the positive pole of the direct current input power supply Vin, sequentially passes through the MOS tube S3, the resonance capacitor Cr, the exciting inductor Lm, the primary side of the transformer T1, the resonance inductor Lr1 and the MOS tube S2 and returns to the negative pole of the direct current input power supply Vin, and the current flow of the secondary side of the transformer T1 starts from the lower synonym end, passes through the MOS tube Q2, the filter capacitor C1 and returns to the center tap; the current flow direction of the leakage inductance Lr2 at the primary side of the phase-shifting full-bridge circuit transformer T2 is still consistent with the second mode, the MOS tube Q3 and the MOS tube Q4 at the secondary side of the transformer T2 are both conducted, the secondary side is short-circuited, only the leakage inductance Lr2 provides energy, in the state, the current directions of the full-bridge LLC circuit and the phase-shifting full-bridge circuit flowing through the MOS tube S3 are opposite, the follow current energy of the leakage inductance Lr2 can be rapidly consumed, and the MOS tube S6 of the next mode can reach the ZVS state more rapidly; the MOS tube S5 is turned off, and the third mode is finished.
As shown in fig. 6, modality four, at the period t3-t 4: MOS tube S2, MOS tube S3, MOS tube Q2, MOS tube Q3 are opened, the current flow of the full-bridge LLC circuit is same in mode III; the current flow direction of the primary side leakage inductance Lr2 of the phase-shifting full-bridge circuit transformer T2 is still consistent with the third mode, the MOS tube Q3 on the secondary side of the transformer T2 is conducted, the MOS tube Q4 is continuously conducted through a diode, the secondary side is short-circuited, only the leakage inductance Lr2 provides energy, at the moment, the capacitance of the MOS tube S5 is charged, the capacitance of the MOS tube S6 is discharged, and preparation is made for the ZVS opening of the MOS tube S6; the MOS transistor S6 is turned on, and the fourth mode is ended.
As shown in fig. 7, modality five, during the period t4-t 5: the MOS tube S2, the MOS tube S3, the MOS tube S6, the MOS tube Q2 and the MOS tube Q3 are opened, the resonance current and the exciting current of the full-bridge LLC circuit are unequal, the current flow of the primary side of the transformer T1 starts from the positive pole of the direct current input power supply Vin, sequentially passes through the MOS tube S3, the resonance capacitor Cr, the exciting inductor Lm, the primary side of the transformer T1, the resonance inductor Lr1 and the MOS tube S2, then returns to the negative pole of the direct current input power supply Vin, and the current flow of the secondary side of the transformer T1 starts from the lower different-name end, passes through the MOS tube Q2 and the filter capacitor C1 and returns to the center tap; the current flow direction of the primary side of the phase-shifting full-bridge circuit transformer T2 starts from the positive electrode of the direct current input power supply Vin, sequentially passes through the MOS tube S3, the leakage inductance Lr2, the primary side of the transformer T2 and the MOS tube S6, then returns to the negative electrode of the direct current input power supply Vin, and the current flow direction of the secondary side of the transformer T2 starts from the same-name end from the upper part, and returns to the center tap after passing through the MOS tube Q3, the filter inductance L0 and the filter capacitor C2. And the MOS tube S2 and the MOS tube S3 are turned off, and the fifth mode is finished.
As shown in fig. 8, modality six, at the period t5-t 6: the MOS tube S6 and the MOS tube Q3 are switched on, the resonance current and the excitation current of the full-bridge LLC circuit are equal, the output current is zero at the moment, the primary side and the secondary side are separated, the current flow direction of the primary side resonance inductor Lr1 of the transformer T1 is still consistent with the mode five, and at the moment, the capacitors of the MOS tubes S1 and S4 are discharged to prepare for switching on the MOS tube S1 and the MOS tube S4 ZVS; the current flow direction of the primary side leakage inductance Lr2 of the phase-shifting full-bridge circuit transformer T2 is still consistent with the mode five, at the moment, the capacitance of the MOS tube S3 is charged, the capacitance of the MOS tube S4 is discharged, preparation is made for opening the MOS tube S3ZVS, the current flow direction of the secondary side of the transformer T2 starts from the same-name end from the upper side, and the secondary side returns to the center tap after passing through the MOS tube Q4, the filter inductance L0 and the filter capacitance C2. The MOS tube S1 and the MOS tube S4 are opened, and the mode six is ended.
As shown in fig. 9, modality seven, at the period t6-t 7: the MOS tube S1, the MOS tube S4, the MOS tube S6, the MOS tube Q1, the MOS tube Q3 and the MOS tube Q4 are opened, the resonance current and the exciting current of the full-bridge LLC circuit are unequal, the current flow of the primary side of the transformer T1 starts from the positive pole of the direct current input power source Vin, sequentially passes through the MOS tube S1, the resonance inductor Lr1, the exciting inductor Lm and the primary side of the transformer T1, the resonance capacitor Cr and the MOS tube S4 and returns to the negative pole of the direct current input power source Vin, and the current flow of the secondary side of the transformer T1 starts from the upper homonymous end, passes through the filter capacitor C1 and the MOS tube Q2 and returns to the center tap; the current flow direction of the primary side leakage inductance Lr2 of the phase-shifting full-bridge circuit transformer T2 is still consistent with the mode six, the MOS tube Q3 and the MOS tube Q4 on the secondary side of the transformer T2 are both conducted, the secondary side is short-circuited, and only the leakage inductance Lr2 provides energy; in this state, the directions of currents flowing through the MOS transistor S4 by the full-bridge LLC circuit and the phase-shift full-bridge circuit are opposite, so that the follow current energy of the leakage inductance Lr2 is rapidly consumed, and the MOS transistor S5 in the next mode can reach the ZVS state more rapidly. The MOS transistor S6 is turned off, and the mode seven is ended.
As shown in fig. 10, modality eight, at time period t7-t 8: the MOS tube S1 and the MOS tube S4 are opened, and the current of the full-bridge LLC circuit flows to the same mode seven; the current flow direction of the primary side leakage inductance Lr2 of the phase-shifting full-bridge circuit transformer T2 is still consistent with the mode seven, the MOS tube Q4 on the secondary side of the transformer T2 is conducted, the MOS tube Q3 is continuously conducted through a diode, the secondary side is short-circuited, only the leakage inductance Lr2 provides energy, at the moment, the capacitance of the MOS tube S6 is charged, the capacitance of the MOS tube S5 is discharged, and preparation is made for the ZVS opening of the MOS tube S5. The MOS transistor S5 is turned on, and the mode eight is ended.
According to a wide-range high-efficiency data center power supply topological structure, a planar transformer is adopted for the transformer T1 and the transformer T2, and the planar transformer has the advantages of high power density, high efficiency, low leakage inductance, good heat dissipation, low cost and the like. Specifically, because the leakage inductance of the planar transformer is low, only in the nanohenry level, the leakage inductances of the transformer T1 and the transformer T2 are integrated into the planar transformer. The primary side of the leakage inductance integrated transformer is connected with the leakage inductance in series, and each layer of PCB board is connected with each coil of the primary side and each coil of the secondary side in parallel.
The full-bridge LLC circuit in the data center power supply provided by the utility model works at a fixed switching frequency and is equivalent to a direct-current transformer, so that the transmission loss of the full-bridge LLC circuit is reduced, and the phase-shifting full-bridge circuit adjusts the output voltage in a phase-shifting angle adjusting mode; the power supply can quickly respond to reach a given value, and meanwhile, the power supply can adapt to various working conditions and achieves higher efficiency.
The above is only for illustrating the technical idea of the present utility model, and the protection scope of the present utility model is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present utility model falls within the protection scope of the claims of the present utility model.
Claims (10)
1. The utility model provides a wide-range high efficiency data center power topological structure, its characterized in that includes full-bridge LLC circuit, phase shift full-bridge circuit, direct current input power Vin and output capacitor C0, full-bridge LLC circuit and phase shift full-bridge circuit share a bridge arm, and full-bridge LLC circuit and phase shift full-bridge circuit's input all are connected in direct current input power Vin, and full-bridge LLC circuit and phase shift full-bridge circuit's output connect output capacitor C0's one end respectively, and output capacitor C0's both ends are power topological structure's output.
2. The power supply topology of claim 1, wherein the full-bridge LLC circuit includes a MOS transistor S1, a MOS transistor S2, a resonant inductor Lr1, an excitation inductor Lm, a resonant capacitor Cr, a transformer T1, a MOS transistor Q2, and a filter capacitor C1; the phase-shifting full-bridge circuit comprises an MOS tube S5, an MOS tube S6, leakage inductance Lr2, a transformer T2, an MOS tube Q3, an MOS tube Q4, a filter inductance L0 and a filter capacitor C2; the bridge arm shared by the full-bridge LLC circuit and the phase-shifting full-bridge circuit comprises an MOS tube S3 and an MOS tube S4;
the transformer T1 and the transformer T2 are transformers with secondary sides provided with center taps; the drain electrode of the MOS tube S1, the drain electrode of the MOS tube S3 and the drain electrode of the MOS tube S5 are connected with the positive electrode of the direct current input power supply Vin; the source electrode of the MOS tube S1 is connected with the drain electrode of the MOS tube S2, the source electrode of the MOS tube S3 is connected with the drain electrode of the MOS tube S4, and the source electrode of the MOS tube S5 is connected with the drain electrode of the MOS tube S6; the source electrode of the MOS tube S2, the source electrode of the MOS tube S4 and the source electrode of the MOS tube S6 are connected with the cathode of the direct current input power supply Vin; one end of the resonant inductor Lr1 is connected with the same-name end of the primary side of the transformer T1, and the other end of the resonant inductor Lr1 is connected with the source electrode of the MOS tube S1; the resonance capacitor Cr is connected with the synonym end of the primary side of the transformer T1, and the other end of the resonance capacitor Cr is connected with the source electrode of the MOS tube S3; the excitation inductor Lm is connected with the primary side of the transformer T1 in parallel; one end of the leakage inductance Lr2 is connected with the same-name end of the primary side of the transformer T2, the other end of the leakage inductance Lr2 is connected with the source electrode of the MOS tube S3, and the different-name end of the primary side of the transformer T2 is connected with the source electrode of the MOS tube S5; the same-name end above the secondary side of the transformer T1 is connected with the source electrode of the MOS tube Q1, the different-name end below the secondary side of the transformer T1 is connected with the source electrode of the MOS tube Q2, the drain electrode of the MOS tube Q1 is connected with the drain electrode of the MOS tube Q2, one end of the filter capacitor C1 is connected with a center tap of the transformer T1, and the other end of the filter capacitor C1 is connected with the drain electrode of the MOS tube Q1; the same-name end above the secondary side of the transformer T2 is connected with the source electrode of the MOS tube Q3, the different-name end below the secondary side of the transformer T2 is connected with the source electrode of the MOS tube Q4, the drain electrode of the MOS tube Q3 is connected with the drain electrode of the MOS tube Q4, one end of the filter capacitor C2 is connected with a center tap of the transformer T2, the other end of the filter capacitor C2 is connected with one end of the filter inductor L0, and the other end of the filter inductor L0 is connected with the drain electrode of the MOS tube Q3; one end of the output capacitor C0 is connected with the drain electrode of the MOS tube Q1, and the other end of the output capacitor C0 is connected with a secondary side center tap of the transformer T2; the drain electrode of the MOS tube Q1 is the positive electrode of the output voltage, and the center tap of the secondary side of the transformer T2 is the negative electrode of the output voltage.
3. The wide range high efficiency data center power topology of claim 1, wherein the switching frequency of the phase-shifted full-bridge circuit is the same as the switching frequency of the full-bridge LLC circuit.
4. The power topology of claim 1, wherein a diode and a capacitor are respectively connected between the drain and the source of each of the MOS transistor S1, the MOS transistor S2, the MOS transistor S3, the MOS transistor S4, the MOS transistor S5, and the MOS transistor S6.
5. The wide range high efficiency data center power topology of claim 4, wherein the anode of the diode is connected to the source of the MOS transistor and the cathode of the diode is connected to the drain of the MOS transistor.
6. The wide range high efficiency data center power topology of claim 1, wherein transformer T1 and transformer T2 each employ planar transformers.
7. The wide range high efficiency data center power topology of claim 6, wherein leakage inductance of transformers T1 and T2 is integrated into a planar transformer.
8. The power topology of claim 6, wherein primary sides of the leakage inductance integrated transformers are connected in series to each other, and each layer of PCB connects the respective coils of the primary and secondary sides in parallel.
9. The wide range high efficiency data center power topology of claim 1, wherein the center power topology operational sequence is divided into 8 time periods.
10. The power topology of claim 1, wherein one end of the output capacitor C0 connected to the drain of the MOS transistor Q1 is at a high level, and the other end of the output capacitor C0 is at a low level.
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