CN220324145U - Aging test system for memory chip - Google Patents
Aging test system for memory chip Download PDFInfo
- Publication number
- CN220324145U CN220324145U CN202321520915.6U CN202321520915U CN220324145U CN 220324145 U CN220324145 U CN 220324145U CN 202321520915 U CN202321520915 U CN 202321520915U CN 220324145 U CN220324145 U CN 220324145U
- Authority
- CN
- China
- Prior art keywords
- unit
- electrically connected
- burn
- test
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 99
- 230000032683 aging Effects 0.000 title claims abstract description 13
- 238000001514 detection method Methods 0.000 claims abstract description 32
- 238000012544 monitoring process Methods 0.000 claims abstract description 27
- 238000007689 inspection Methods 0.000 claims 5
- 230000002159 abnormal effect Effects 0.000 abstract description 6
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000013102 re-test Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Abstract
The present utility model relates to the field of testing memory chips, and in particular, to a burn-in test system for memory chips. A memory chip burn-in system comprising: a test device, comprising: the mounting seat is used for mounting the chip to be tested; the aging test board is electrically connected with the chip to be tested; and a high temperature box housing the mount pad and the burn-in board; the input device is provided with a reserved interface which is electrically connected with the aging test board; the controller is electrically connected with the high-temperature box body and the input device; the detection device is electrically connected with the testing device; and the display device is electrically connected with the detection device and comprises a test monitoring interface unit and an early warning unit, the early warning unit sets an early warning threshold value to trigger an alarm signal, and the test monitoring interface unit displays the alarm signal. The utility model can timely detect the abnormal memory chip and improve the detection efficiency of the memory chip.
Description
Technical Field
The present utility model relates to the field of testing memory chips, and in particular, to a burn-in test system for memory chips.
Background
The memory chips need to be burn-in tested before being shipped in quantity to screen out chips with poor product quality. During the burn-in test of the memory chip, the test state of the LED (Light Emitting Diode ) lamp is monitored manually to determine whether the test is completed. In the prior art, a lot of memory chips are tested for burn-in by setting enough time, and then the memory chips are concentrated to enter the next testing station for screening the burn-in results. The condition of misjudgment easily appears in the mode of manual monitoring, leads to the memory chip that does not test to accomplish flows into next test station, has reduced the test yield, influences production efficiency. There is therefore a need for improvement.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present utility model is to provide a burn-in test system for a memory chip, so as to solve the problems of low test yield and low production efficiency of the burn-in test in the prior art.
To achieve the above and other related objects, the present utility model provides a memory chip burn-in system, comprising:
a test device, comprising:
the mounting seat is used for mounting the chip to be tested;
the aging test board is electrically connected with the chip to be tested; and
the high-temperature box body is used for accommodating the mounting seat and the aging test board;
the input device is provided with a reserved interface which is electrically connected with the aging test board;
the controller is electrically connected with the high-temperature box body and the input device;
the detection device is electrically connected with the testing device; and
the display device is electrically connected with the detection device and comprises a test monitoring interface unit and an early warning unit, the early warning unit sets an early warning threshold value to trigger an alarm signal, and the test monitoring interface unit displays the alarm signal.
In an embodiment of the utility model, the display device further includes a temperature monitoring interface unit, and the temperature monitoring interface unit is electrically connected to the detecting device.
In an embodiment of the utility model, the display device further includes a power output monitoring unit, and the power output monitoring unit is electrically connected to the detecting device.
In an embodiment of the utility model, the display device further includes a control operation unit, and the control operation unit is electrically connected to the control device.
In one embodiment of the present utility model, the burn-in board is provided with a plurality of mounting seats, and each mounting seat is used for mounting one chip to be tested.
In an embodiment of the utility model, each of the mounting bases is electrically connected to the detecting device to output an independent test signal.
In one embodiment of the present utility model, the input device includes a power unit and a signal unit, and the power unit and the signal unit are electrically connected to the burn-in board through the reserved interface.
In one embodiment of the present utility model, the controller includes a temperature control unit and an input control unit, the temperature control unit is electrically connected to the high temperature box, and the input control unit is electrically connected to the input device.
In an embodiment of the utility model, the detecting device includes a test state detecting unit and a temperature detecting unit, the test state detecting unit is electrically connected to the chip to be tested, and the temperature detecting unit is electrically connected to the high temperature box.
In an embodiment of the utility model, the detection device further includes a power detection unit, and the power detection unit is electrically connected to the input device.
As described above, the aging test system for the memory chip has the following beneficial effects: the abnormal memory chip can be detected in time, and the detection efficiency of the memory chip is improved.
Drawings
Fig. 1 is a schematic structural diagram of a memory chip burn-in system according to the present utility model.
FIG. 2 is a schematic diagram showing the connection of the input device and the burn-in board according to the present utility model.
Fig. 3 is a schematic diagram showing the connection between the detecting device and the mounting base in the present utility model.
Description of element reference numerals
10. A testing device; 110. a high temperature tank; 120. an aging test board; 130. a mounting base; 140. reserving an interface;
20. an input device; 210. a power supply unit; 220. a signal unit;
30. a controller; 310. a temperature control unit; 320. an input control unit;
40. a detection device; 410. a test state detection unit; 420. a power supply detection unit; 430. a temperature detection unit;
50. a display device; 510. testing the monitoring interface unit; 520. a temperature monitoring interface unit; 530. a power output monitoring unit; 540. a control operation unit; 550. an early warning unit;
60. and a chip to be tested.
Detailed Description
Other advantages and effects of the present utility model will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present utility model with reference to specific examples. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. It is also to be understood that the terminology used in the examples of the utility model is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the utility model. The test methods in the following examples, in which specific conditions are not noted, are generally conducted under conventional conditions or under conditions recommended by the respective manufacturers.
It should be understood that the structures, proportions, sizes, etc. shown in the drawings are for illustration purposes only and should not be construed as limiting the utility model to the extent that it can be practiced, since modifications, changes in the proportions, or otherwise, used in the practice of the utility model, are not intended to be critical to the essential characteristics of the utility model, but are intended to fall within the spirit and scope of the utility model. Also, the terms such as "upper," "lower," "left," "right," "middle," and "a" and the like recited in the present specification are merely for descriptive purposes and are not intended to limit the scope of the utility model, but are intended to provide relative positional changes or modifications without materially altering the technical context in which the utility model may be practiced.
Referring to fig. 1 to 3, the present utility model provides a memory chip burn-in system, which can be applied to the burn-in field of memory chips, for example, to burn-in before the eMMC (Embedded Multi Media Card ) volume production. Poor blocks are screened out by performing Erase-Program-Read processing at different temperatures. The Result Page (Result Page) of the burn-in test Result in Bad Block (Chip Enable) of each CE (Chip select) is recorded to improve and optimize the Chip processing process. The utility model can timely detect the storage chip of the bad product and improve the detection efficiency of the storage chip. The following is a detailed description of specific embodiments.
Referring to fig. 1, in some embodiments of the present utility model, a memory chip burn-in system may include a testing device 10, an input device 20, a controller 30, a detecting device 40 and a display device 50. The test apparatus 10 may include a high temperature box 110, a burn-in board 120, and a mounting base 130. The mounting base 130 may be used for mounting the chip 60 to be tested, and a circuit board may be disposed on the mounting base 130 to electrically connect with pins of the chip 60 to be tested. The burn-in board 120 is electrically connected to the chip 60 under test, and the burn-in board 120 outputs adjustable power and signals to the chip 60 under test to achieve circuit testing conditions of the chip 60 under test. The high temperature box 110 can be set with different testing temperatures to realize the temperature testing conditions of the chip 60 to be tested. The high temperature case 110 accommodates the burn-in board 120 and the mount 130, and the mount 130 is provided with the chip 60 to be tested.
Referring to fig. 1, in some embodiments of the present utility model, the input device 20 may be provided with a reserved interface 140, the reserved interface 140 is electrically connected to the burn-in board 120, the input device 20 inputs a power source and a signal to the burn-in board 120, the power source may supply power to the burn-in board 120, and the signal may drive the burn-in board 120 to test the chip 60 to be tested. The controller 30 is electrically connected with the high temperature box 110 and the input device 20, the controller 30 can control and regulate the temperature inside the high temperature box 110, and the controller 30 can control and regulate the power supply and signals output by the input device 20. The detecting device 40 is electrically connected to the testing device 10, and the detecting device 40 is used for detecting a test status signal of the chip 60 to be tested. The display device 50 is electrically connected to the detecting device 40, the display device 50 may include a test detection interface unit 510 and an early warning unit 550, the early warning unit 550 may set early warning thresholds such as a test temperature, a test voltage, a test current, and a number of continuous test failures, and when the test condition is not satisfied, the early warning unit 550 may trigger an alarm signal. After the alarm signal is triggered, the alarm can be released to continue the aging test only by human intervention. The test monitoring interface unit may be used to display an alarm signal.
Referring to fig. 1, in some embodiments of the present utility model, the input device 20 may include a power unit 210 and a signal unit 220, where the power unit 210 and the signal unit 220 are electrically connected to the burn-in board 120 through the reserved interface 140. The power supply unit 210 inputs an adjustable voltage to the burn-in board 120, and the signal unit 220 inputs an adjustable signal to the burn-in board 120 to implement the circuit test conditions of the chip 60 under test.
Referring to fig. 1, in some embodiments of the present utility model, the controller 30 may include a temperature control unit 310 and an input control unit 320. The temperature control unit 310 is electrically connected to the high temperature casing 110, and the temperature control unit 310 is used for controlling and adjusting the temperature inside the high temperature casing 110. The input control unit 320 is electrically connected to the input device 20, and the input control unit 320 is used for controlling and adjusting the power and signals output by the input device 20.
Referring to fig. 1, in some embodiments of the present utility model, the detecting device 40 may include a test status detecting unit 410, a power detecting unit 420, and a temperature detecting unit 430. The test state detection unit 410 may be electrically connected to the chip 60 to be tested, where the test state detection unit 410 is configured to detect a test state signal of the chip 60 to be tested, and is configured to detect whether the chip 60 to be tested has a fault. The temperature detection unit 430 may be electrically connected to the high temperature casing 110, and the temperature detection unit 430 is used to detect the internal temperature of the high temperature casing 110. The power detection unit 420 may be electrically connected to the input device 20, and the power detection unit 420 is used for detecting a power signal of the input device 20.
Referring to fig. 1, in some embodiments of the present utility model, the display device 50 may further include a temperature monitoring interface unit 520, a power output monitoring unit 530, and a control operation unit 540. The temperature monitoring interface unit 520 is electrically connected to the detecting device 40, and the temperature monitoring interface unit 520 is used for monitoring the temperature inside the high temperature box 110. The power output monitoring unit 530 is electrically connected to the detecting device 40, and the power output monitoring unit 530 is used for monitoring the power of the input device 20. The control operation unit 540 is electrically connected with the controller 30, and the control operation unit 540 can be used for inputting data to the controller 30 so as to realize control adjustment of the data sizes of the temperature control unit 310 and the input control unit 320.
Referring to FIG. 1, in some embodiments of the utility model, burn-in testing for memory chips 60 may include the following procedure. First, the chip 60 to be tested can be mounted on the mounting base 130, and the mounting base 130 is disposed on the burn-in board 120. The burn-in board 120 may be provided with a plurality of mounting seats 130, and each mounting seat 130 may be used to mount one chip 60 to be tested. Each mount 130 may be electrically connected to the detection device 40 to output an independent test signal. Next, the burn-in board 120 is placed into the high temperature chamber 110, and the burn-in board 120 is electrically connected to the input device 20 through the reserved interface 140. Next, by controlling the operation unit 540 to set an appropriate test temperature, the temperature detection unit 430 detects that the temperature is stable, and then the controller 30 controls the input device 20 to perform input setting of power and signals. Next, after the input device 20 inputs the power and the signal to the burn-in board 120, the detection device 40 detects the signal such as the output voltage and the current, and the output result can be monitored by the power output monitoring unit 530. After the power output monitoring unit 530 monitors normal, a burn-in stage may be entered. Next, the temperature, voltage, current, and the early warning threshold of the early warning unit 550 may be set in advance. During the burn-in test, an alarm signal of the pre-warning unit 550 is triggered if a test condition abnormality occurs. After the alarm signal is triggered, the alarm can be released to continue the test after the artificial intervention is needed. Then, the test result is checked by the test state detection unit 410. The temperature inside the high-temperature casing 110 is returned to normal temperature by the temperature control unit 310, and the burn-in board 120 is taken out of the high-temperature casing 110. Screening out the abnormal memory chips 60 according to the test result, and flowing the memory chips 60 with normal test into the next test station for testing. Finally, retests can be performed after the number of the memory chips 60 tested for abnormality reaches a certain number, so as to determine again whether the memory chips 60 are abnormal.
Referring to fig. 2 and 3, in some embodiments of the present utility model, the power unit 210 powers up the burn-in board 120, and the signal unit 220 inputs a clock signal to the burn-in board 120. During the burn-in test, the test status detection unit 410 of the detection module 40 can receive the test status signal DAT0 of the chip 60 under test. The test status detecting unit 410 reads the DAT0 signal, and when the DAT0 signal is a square wave signal, it indicates that the burn-in board 120 has started to perform the burn-in test, and when there is no output signal, it indicates that the burn-in board has started to perform the test failure. After the burn-in board 120 enters a normal test state, the DAT0 signal continues to be read. When the DAT0 signal is still a square wave signal, it indicates that the burn-in board 120 is still in the test phase. When the DAT0 signal is a high signal, the burn-in board 120 is indicated as ending the test. After the abnormal memory chips 60 are screened out, burn-in testing of the next batch of memory chips 60 may be performed.
In summary, the present utility model provides a memory chip burn-in system, which can timely detect abnormal memory chips and improve the detection efficiency of the memory chips. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present utility model and its effectiveness, and are not intended to limit the utility model. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the utility model. Accordingly, it is intended that all equivalent modifications and variations of the utility model be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A memory chip burn-in system, comprising:
a test device, comprising:
the mounting seat is used for mounting the chip to be tested;
the aging test board is electrically connected with the chip to be tested; and
the high-temperature box body is used for accommodating the mounting seat and the aging test board;
the input device is provided with a reserved interface which is electrically connected with the aging test board;
the controller is electrically connected with the high-temperature box body and the input device;
the detection device is electrically connected with the testing device; and
the display device is electrically connected with the detection device and comprises a test monitoring interface unit and an early warning unit, the early warning unit sets an early warning threshold value to trigger an alarm signal, and the test monitoring interface unit displays the alarm signal.
2. The burn-in system of claim 1 wherein said display device further comprises a temperature monitoring interface unit, said temperature monitoring interface unit being electrically connected to said detection device.
3. The burn-in system of claim 1 wherein said display device further comprises a power output monitor unit, said power output monitor unit being electrically connected to said detection device.
4. The burn-in system of claim 1 wherein said display device further comprises a control operation unit, said control operation unit being electrically connected to said control device.
5. The burn-in system of claim 1 wherein said burn-in board has a plurality of said mounts, each for mounting one of said dies under test.
6. The burn-in system of claim 5 wherein each of said mounts is electrically connected to said test device for outputting an independent test signal.
7. The burn-in system of claim 1, wherein said input device comprises a power unit and a signal unit, said power unit and signal unit being electrically connected to said burn-in board through said reserved interface.
8. The burn-in system of claim 1 wherein said controller comprises a temperature control unit and an input control unit, said temperature control unit being electrically connected to said high temperature housing, said input control unit being electrically connected to said input device.
9. The burn-in system of claim 1 wherein said inspection device comprises a test status inspection unit and a temperature inspection unit, said test status inspection unit being electrically connected to said chip under test, said temperature inspection unit being electrically connected to said high temperature enclosure.
10. The burn-in system of claim 9 wherein said sensing device further comprises a power sensing unit, said power sensing unit being electrically coupled to said input device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321520915.6U CN220324145U (en) | 2023-06-13 | 2023-06-13 | Aging test system for memory chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321520915.6U CN220324145U (en) | 2023-06-13 | 2023-06-13 | Aging test system for memory chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220324145U true CN220324145U (en) | 2024-01-09 |
Family
ID=89422852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321520915.6U Active CN220324145U (en) | 2023-06-13 | 2023-06-13 | Aging test system for memory chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220324145U (en) |
-
2023
- 2023-06-13 CN CN202321520915.6U patent/CN220324145U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100493058B1 (en) | Electrical testing method for semiconductor package detectable a socket defects by realtime operation | |
| CN110850275B (en) | Burn-in test method, apparatus and readable storage medium | |
| TWI472780B (en) | Semiconductor device test system | |
| JP5170395B2 (en) | Wafer and temperature test method thereof | |
| CN107678909B (en) | Circuit and method for monitoring chip configuration state in server | |
| KR101747710B1 (en) | Real speed high temperature aging system for semiconductor | |
| CN113866611B (en) | Automatic power-on and power-off test system and method for reliability of DSP chip circuit | |
| CN220324145U (en) | Aging test system for memory chip | |
| WO2012171531A1 (en) | Led fault diagnostic method and system | |
| JPS63274885A (en) | Method of testing semiconductor integrated circuit during burn-in and circuit substrate | |
| KR101499851B1 (en) | System for testing integrity of burn-in boards for various burn-in tests | |
| EP2312329B1 (en) | Reliability test with monitoring of the results | |
| US20090126468A1 (en) | Filter unit for conductive fluid detection apparatus and conductive fluid detection apparatus using the same | |
| CN113125938B (en) | Aging test monitoring method and system | |
| JP2013029439A (en) | Semiconductor integrated circuit device and method of testing the same | |
| CN113884833B (en) | System and method for detecting welding quality of capacitor | |
| JPH1138085A (en) | Action error inspecting method for tester | |
| US20120038367A1 (en) | Connection quality verification for integrated circuit test | |
| CN112630621A (en) | Pin short circuit detection circuit and detection method | |
| US20230384365A1 (en) | Wafer test system and operating method thereof | |
| KR100821095B1 (en) | Test device for the semiconductor and the testing method thereof | |
| KR20080002496A (en) | Test system for semiconductor device | |
| CN219179589U (en) | Detection device applied to IC tester | |
| CN218727437U (en) | Aging test system of WiFi module | |
| CN113759300B (en) | Performance test method and device of battery management unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |