CN220306969U - Intelligent door lock equalizing charge circuit - Google Patents
Intelligent door lock equalizing charge circuit Download PDFInfo
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- CN220306969U CN220306969U CN202321414316.6U CN202321414316U CN220306969U CN 220306969 U CN220306969 U CN 220306969U CN 202321414316 U CN202321414316 U CN 202321414316U CN 220306969 U CN220306969 U CN 220306969U
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- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052744 lithium Inorganic materials 0.000 claims abstract description 22
- 239000003990 capacitor Substances 0.000 claims description 59
- 238000007599 discharging Methods 0.000 claims description 33
- 230000002457 bidirectional effect Effects 0.000 claims description 9
- 101100163833 Arabidopsis thaliana ARP6 gene Proteins 0.000 claims description 6
- 101100100146 Candida albicans NTC1 gene Proteins 0.000 claims description 6
- 101100027017 Caenorhabditis elegans ntc-1 gene Proteins 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 2
- 238000001914 filtration Methods 0.000 description 3
- 238000004880 explosion Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241000282326 Felis catus Species 0.000 description 1
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000004899 c-terminal region Anatomy 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Abstract
The utility model relates to an intelligent door lock equalizing charge circuit which is used for charging a battery pack and comprises 2 batteries connected in series; the lithium battery charging device comprises a charging interface J1, a charging indicating circuit, a lithium battery protection circuit used for being connected with a battery pack and a charging management circuit used for boosting charge, balancing current and being connected with the battery pack; the charging interface J1 is connected with a charging management circuit through a charging indication circuit; the intelligent door lock battery pack can achieve the functions of boosting and charging, balancing control and electric quantity indication of the intelligent door lock battery pack, and is good in practicality.
Description
Technical Field
The utility model relates to the technical field of intelligent door lock equalizing charge circuits, in particular to an intelligent door lock equalizing charge circuit.
Background
The door lock is a device which can play a role in safety and security.
Along with the development of automation and intelligent technologies, under the surge of smart home, the intellectualization of the door lock is also a development trend, and the intelligent door lock is applied.
Because the functions such as face identification, cat eye and WIFI networking are integrated to be applied to the intelligent door lock, the power consumption of the intelligent door lock is higher than that of a traditional fingerprint identification door lock, and the intelligent door lock is not suitable for being powered by a dry battery any more.
At present, the intelligent door lock is powered by a lithium battery capable of being repeatedly charged. The existing lithium battery has the problems that the battery capacity is small or the battery cannot be fully charged due to unbalanced voltage after being charged and discharged for many times during use, so that the service life of the lithium battery is influenced.
The lithium battery of the existing intelligent door lock is difficult to intuitively know the charging state when being charged, so that the charging condition is not known by using the lithium battery.
Accordingly, in the present patent application, the applicant has studied a smart door lock equalizing charge circuit to solve the above-mentioned problems.
Disclosure of Invention
Aiming at the defects of the prior art, the utility model mainly aims to provide an intelligent door lock equalizing charge circuit which can realize the functions of boosting charge, equalizing control and electric quantity indication on a battery pack of an intelligent door lock and has good practicability.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
an intelligent door lock equalizing charge circuit is used for charging a battery pack and the battery pack comprises 2 batteries connected in series; the lithium battery charging device comprises a charging interface J1, a charging indicating circuit, a lithium battery protection circuit used for being connected with a battery pack and a charging management circuit used for boosting charge, balancing current and being connected with the battery pack; the charging interface J1 is connected with a charging management circuit through a charging indication circuit.
As a preferable scheme, the charging indication circuit includes a resistor R4, a resistor R3, a first charging state indicator LED1, a second charging state indicator LED2, and a MOS tube Q1;
the A5 pin of the charging interface J1 is grounded digitally through a resistor R6, the B5 pin of the charging interface J1 is grounded digitally through a resistor R5, the B9 pin of the charging interface J1 is simultaneously connected with one end of a resistor R4 and one end of a resistor R3, the other end of the resistor R4 is connected with the anode of a first charging state indicator LED1, the cathode of the first charging state indicator LED1 is connected with the drain electrode of a MOS tube Q1, the grid electrode of the MOS tube Q1 is respectively connected with the cathode of a second charging state indicator LED2 and a charging management circuit, the anode of the second charging state indicator LED2 is connected with the other end of the resistor R3, and the source electrode of the MOS tube Q1 is connected with the A12 pin of the charging interface J1 and grounded digitally.
As a preferable scheme, the charge management circuit includes a chip U1, a capacitor C3, an inductor L1, a diode D1, a capacitor C6, a resistor R1, a resistor R9, and a capacitor C2;
the pin 3 and the pin 2 of the chip U1 are respectively connected with a charging indicating circuit, the pin 3 of the chip U1 is connected with the pin 4 of the chip U1 through a capacitor C1 and is grounded digitally, the pin 4 of the chip U1 is connected with one end of an inductor L1 and the pin 3 of the chip U1 through the capacitor C3, the other end of the inductor L1 is connected with the pin 5 of the chip U1, the pin 5 of the chip U1 is connected with the anode of a diode D1, the cathode of the diode D1 is connected with the pin 6 of the chip U1, and the pin 6 of the chip U1 is grounded digitally through the capacitor C6;
the pin 7 of the chip U1 is used for connecting with the B+ end of the battery pack, and the pin 7 of the chip U1 is also grounded digitally through the capacitor C2; the pin 8 of the chip U1 is connected with the pin 9 of the chip U1 through the resistor R1, the pin 9 of the chip U1 is used for being connected with the VC end of the battery pack, and the pin 10 of the chip U1 is connected with the lithium battery protection circuit through the resistor R9.
As a preferred solution, the pin 1 of the chip U1 is connected to an NTC thermistor NTC1, and the pin 1 of the chip U1 is connected to the digital ground through the NTC thermistor NTC 1.
As a preferable scheme, the lithium battery protection circuit comprises a chip U2, a capacitor C4, a resistor R2, a resistor R8, a capacitor C5, a resistor R7, a capacitor C9, a capacitor C10, and a first MOS chip Q2, a second MOS chip Q3, and a third MOS chip Q4 which are connected in parallel in three phases;
pin 3 of the chip U2 is connected with digital ground through a resistor R8, pin 5 of the chip U2 is connected with analog ground through a capacitor C4, pin 5 of the chip U2 is also connected with one end of the resistor R2, and the other end of the resistor R2 is used for being connected with the B+ end of the battery pack;
the pin 4 of the chip U2 is connected with the analog ground through the capacitor C5, and the pin 6 of the chip U2 is used for connecting with the B-end of the battery pack and is connected with the analog ground; the pin 4 of the chip U2 is also connected with one end of a resistor R7, and the other end of the resistor R7 is used for being connected with the VC end of the battery pack;
the pin 4 of the first MOS chip Q2, the pin 6 of the second MOS chip Q3 and the pin 4 of the third MOS chip Q4 are all connected with the pin 2 of the chip U2, and the pin 6 of the first MOS chip Q2, the pin 4 of the second MOS chip Q3 and the pin 6 of the third MOS chip Q4 are all connected with the pin 1 of the chip U2;
the pin 3 of the first MOS chip Q2, the pin 1 of the second MOS chip Q3 and the pin 3 of the third MOS chip Q4 are all grounded digitally, the pin 3 of the third MOS chip Q4 is connected with the pin 1 of the third MOS chip Q4 through a capacitor C9 and a capacitor C10, and the pin 1 of the first MOS chip Q2, the pin 3 of the second MOS chip Q3 and the pin 1 of the third MOS chip Q4 are all grounded in an analog mode.
As a preferable scheme, the device further comprises a discharging interface J2, wherein a pin 5 of the discharging interface J2 is connected with a B9 pin of the charging interface J1, the pin 5 of the discharging interface J2 is also connected with one end of the bidirectional TVS tube ESD1, and the pin 5 of the discharging interface J2 is also connected with digital ground through a capacitor C7;
both the pin 2 and the pin 4 of the discharging interface J2 are grounded digitally, the other end of the bidirectional TVS tube ESD1 is connected with the pin 2 of the discharging interface J2, the pin 2 of the discharging interface J2 is connected with the pin 1 of the discharging interface J2 through the bidirectional TVS tube ESD2, the pin 1 of the discharging interface J2 is used for being connected with the B-end of the battery pack, and the pin of the discharging interface J1 is connected with the pin 2 of the discharging interface J2 through a capacitor C8.
Compared with the prior art, the utility model has obvious advantages and beneficial effects, in particular: the battery pack of the intelligent door lock can be subjected to boosting charging, balanced control and electric quantity indication through the cooperation of the charging interface J1, the charging indication circuit, the lithium battery protection circuit and the charging management circuit, so that the practicability is good;
secondly, through NTC thermistor NTC1, the temperature of group battery when can the real-time supervision charges, avoid overcharging and the emergence of the incident such as battery fire or explosion that the group battery temperature risees sharply or continuously and causes that the trouble caused charges.
In order to more clearly illustrate the structural features and efficacy of the present utility model, a detailed description thereof will be given below with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic block diagram of an embodiment of the present utility model;
fig. 2 is an overall circuit schematic of an embodiment of the present utility model.
Reference numerals illustrate:
11. charging management circuit
12. Lithium battery protection circuit
13. And a charge indication circuit.
Detailed Description
The utility model is further described below with reference to the drawings and detailed description.
As shown in fig. 1 and 2, an intelligent door lock equalizing charge circuit is used for charging a battery pack, and the battery pack comprises 2 batteries connected in series; the lithium battery protection circuit comprises a charging interface J1, a charging indicating circuit 13, a lithium battery protection circuit 12 used for connecting a battery pack and a charging management circuit 11 used for boosting charge, balancing current and connecting the battery pack; the charging interface J1 is connected to the charging management circuit 11 through the charging indication circuit 13.
In this embodiment, the charge indication circuit 13 includes a resistor R4, a resistor R3, a first charge state indicator LED1, a second charge state indicator LED2, and a MOS transistor Q1;
the charging interface J1 is a Type C terminal as a charging input interface, wherein the A5 pin and the B5 pin are configured to provide a power supply of 5V3A by the Type C adapter.
The A5 pin of the charging interface J1 is grounded digitally through a resistor R6, the B5 pin of the charging interface J1 is grounded digitally through a resistor R5, the B9 pin of the charging interface J1 is simultaneously connected with one end of a resistor R4 and one end of a resistor R3, the other end of the resistor R4 is connected with the anode of a first charging state indicator LED1, the cathode of the first charging state indicator LED1 is connected with the drain electrode of a MOS tube Q1, the grid electrode of the MOS tube Q1 is respectively connected with the cathode of a second charging state indicator LED2 and a charging management circuit 11, the anode of the second charging state indicator LED2 is connected with the other end of the resistor R3, and the source electrode of the MOS tube Q1 is connected with the A12 pin of the charging interface J1 and grounded digitally.
In the present embodiment, the charge management circuit 11 has a boost charge and equalization control function. The charge management circuit 11 includes a chip U1, a capacitor C3, an inductor L1, a diode D1, a capacitor C6, a resistor R1, a resistor R9, and a capacitor C2;
the pin 3 and the pin 2 of the chip U1 are respectively connected with a charging indicating circuit 13 (the pin 3 of the chip U1 is connected with one end of the resistor R3, the pin 2 of the chip U1 is connected with the grid electrode of the MOS tube Q1), and the pin 3 of the chip U1 is connected with the pin 4 of the chip U1 through the capacitor C1 and grounded digitally. The capacitor C1 is a filter capacitor of a power supply circuit of the chip U1, so that the chip works more stably.
The pin 4 of the chip U1 is connected with one end of the inductor L1 and the pin 3 of the chip U1 through the capacitor C3, the other end of the inductor L1 is connected with the pin 5 of the chip U1, the pin 5 of the chip U1 is connected with the anode of the diode D1, the cathode of the diode D1 is connected with the pin 6 of the chip U1, and the pin 6 of the chip U1 is grounded through the capacitor C6;
the pin 7 of the chip U1 is used for connecting with the B+ end of the battery pack, and the pin 7 of the chip U1 is also grounded digitally through the capacitor C2; the pin 8 of the chip U1 is connected with the pin 9 of the chip U1 through the resistor R1, the pin 9 of the chip U1 is used for being connected with the VC end of the battery pack, and the pin 10 of the chip U1 is connected with the lithium battery protection circuit 12 through the resistor R9.
The inductor L1, the diode D1, the capacitor C3, the capacitor C6 and the capacitor C2 form a boosting charging function. Wherein the capacitor C3 is input filtering, the capacitor C6 is boost filtering, the capacitor C2 is output filtering, and the diode D1 is freewheeling diode. Resistor R9 sets the charging current to a maximum of 1.2A.
The resistor R1 forms a charge equalization circuit structure. In the charging process, the chip U1 detects the battery voltage of 2 batteries in real time through pins 7, 8 and 9, when detecting that the battery voltage of any 1 battery reaches the balanced starting voltage of 4.10V, the corresponding balanced MOS inside the chip U1 is started, the charging current of the battery is reduced, and the magnitude of balanced current can be adjusted by adjusting the resistance of R1.
The pin 1 of the chip U1 is connected with an NTC thermistor NTC1, and the pin 1 of the chip U1 is grounded through the NTC thermistor NTC 1. By selecting different parameters of the NTC thermistor NTC1, different temperature control points are configured. Meanwhile, the chip U1 is internally provided with a temperature protection function, and when the temperature of the chip U1 exceeds 135 ℃, the chip can be triggered.
In this embodiment, the lithium battery protection circuit 12 includes a chip U2, a capacitor C4, a resistor R2, a resistor R8, a capacitor C5, a resistor R7, a capacitor C9, a capacitor C10, and a first MOS chip Q2, a second MOS chip Q3, and a third MOS chip Q4 connected in parallel in three phases;
pin 3 of the chip U2 is connected with digital ground through a resistor R8, pin 5 of the chip U2 is connected with analog ground through a capacitor C4, pin 5 of the chip U2 is also connected with one end of the resistor R2, and the other end of the resistor R2 is used for being connected with the B+ end of the battery pack;
the pin 4 of the chip U2 is connected with the analog ground through the capacitor C5, and the pin 6 of the chip U2 is used for connecting with the B-end of the battery pack and is connected with the analog ground; the pin 4 of the chip U2 is also connected with one end of a resistor R7, and the other end of the resistor R7 is used for being connected with the VC end of the battery pack;
the pin 4 of the first MOS chip Q2, the pin 6 of the second MOS chip Q3 and the pin 4 of the third MOS chip Q4 are all connected with the pin 2 of the chip U2, and the pin 6 of the first MOS chip Q2, the pin 4 of the second MOS chip Q3 and the pin 6 of the third MOS chip Q4 are all connected with the pin 1 of the chip U2;
the pin 3 of the first MOS chip Q2, the pin 1 of the second MOS chip Q3 and the pin 3 of the third MOS chip Q4 are all grounded digitally, the pin 3 of the third MOS chip Q4 is connected with the pin 1 of the third MOS chip Q4 through a capacitor C9 and a capacitor C10, and the pin 1 of the first MOS chip Q2, the pin 3 of the second MOS chip Q3 and the pin 1 of the third MOS chip Q4 are all grounded in an analog mode.
In this embodiment, the device further includes a discharging interface J2, a pin 5 of the discharging interface J2 is connected to a B9 pin of the charging interface J1, the pin 5 of the discharging interface J2 is further connected to one end of the bidirectional TVS tube ESD1, and the pin 5 of the discharging interface J2 is further connected to digital ground through a capacitor C7;
both the pin 2 and the pin 4 of the discharging interface J2 are grounded digitally, the other end of the bidirectional TVS tube ESD1 is connected with the pin 2 of the discharging interface J2, the pin 2 of the discharging interface J2 is connected with the pin 1 of the discharging interface J2 through the bidirectional TVS tube ESD2, the pin 1 of the discharging interface J2 is used for being connected with the B-end of the battery pack, and the pin of the discharging interface J1 is connected with the pin 2 of the discharging interface J2 through a capacitor C8.
The intelligent door lock battery pack boosting charging control device has the design key points that the intelligent door lock battery pack boosting charging control device can realize the functions of boosting charging, balancing control and electric quantity indication on the intelligent door lock battery pack through the cooperation of the charging interface J1, the charging indication circuit, the lithium battery protection circuit and the charging management circuit, and has good practicability;
secondly, through NTC thermistor NTC1, the temperature of group battery when can the real-time supervision charges, avoid overcharging and the emergence of the incident such as battery fire or explosion that the group battery temperature risees sharply or continuously and causes that the trouble caused charges.
The foregoing description is only of the preferred embodiments of the present utility model and is not intended to limit the technical scope of the present utility model, so that any minor modifications, equivalent changes and modifications made to the above embodiments according to the technical principles of the present utility model still fall within the scope of the technical solutions of the present utility model.
Claims (6)
1. An intelligent door lock equalizing charge circuit is used for charging a battery pack and the battery pack comprises 2 batteries connected in series; the method is characterized in that: the lithium battery charging device comprises a charging interface J1, a charging indicating circuit, a lithium battery protection circuit used for being connected with a battery pack and a charging management circuit used for boosting charge, balancing current and being connected with the battery pack; the charging interface J1 is connected with a charging management circuit through a charging indication circuit.
2. The intelligent door lock equalizing charge circuit according to claim 1, wherein: the charging indication circuit comprises a resistor R4, a resistor R3, a first charging state indicator light LED1, a second charging state indicator light LED2 and a MOS tube Q1;
the A5 pin of the charging interface J1 is grounded digitally through a resistor R6, the B5 pin of the charging interface J1 is grounded digitally through a resistor R5, the B9 pin of the charging interface J1 is simultaneously connected with one end of a resistor R4 and one end of a resistor R3, the other end of the resistor R4 is connected with the anode of a first charging state indicator LED1, the cathode of the first charging state indicator LED1 is connected with the drain electrode of a MOS tube Q1, the grid electrode of the MOS tube Q1 is respectively connected with the cathode of a second charging state indicator LED2 and a charging management circuit, the anode of the second charging state indicator LED2 is connected with the other end of the resistor R3, and the source electrode of the MOS tube Q1 is connected with the A12 pin of the charging interface J1 and grounded digitally.
3. The intelligent door lock equalizing charge circuit according to claim 1, wherein: the charging management circuit comprises a chip U1, a capacitor C3, an inductor L1, a diode D1, a capacitor C6, a resistor R1, a resistor R9 and a capacitor C2;
the pin 3 and the pin 2 of the chip U1 are respectively connected with a charging indicating circuit, the pin 3 of the chip U1 is connected with the pin 4 of the chip U1 through a capacitor C1 and is grounded digitally, the pin 4 of the chip U1 is connected with one end of an inductor L1 and the pin 3 of the chip U1 through the capacitor C3, the other end of the inductor L1 is connected with the pin 5 of the chip U1, the pin 5 of the chip U1 is connected with the anode of a diode D1, the cathode of the diode D1 is connected with the pin 6 of the chip U1, and the pin 6 of the chip U1 is grounded digitally through the capacitor C6;
the pin 7 of the chip U1 is used for connecting with the B+ end of the battery pack, and the pin 7 of the chip U1 is also grounded digitally through the capacitor C2; the pin 8 of the chip U1 is connected with the pin 9 of the chip U1 through the resistor R1, the pin 9 of the chip U1 is used for being connected with the VC end of the battery pack, and the pin 10 of the chip U1 is connected with the lithium battery protection circuit through the resistor R9.
4. The intelligent door lock equalizing charge circuit according to claim 3, wherein: the pin 1 of the chip U1 is connected with an NTC thermistor NTC1, and the pin 1 of the chip U1 is grounded through the NTC thermistor NTC 1.
5. The intelligent door lock equalizing charge circuit according to claim 1, wherein: the lithium battery protection circuit comprises a chip U2, a capacitor C4, a resistor R2, a resistor R8, a capacitor C5, a resistor R7, a capacitor C9, a capacitor C10, a first MOS chip Q2, a second MOS chip Q3 and a third MOS chip Q4 which are connected in parallel in three phases;
pin 3 of the chip U2 is connected with digital ground through a resistor R8, pin 5 of the chip U2 is connected with analog ground through a capacitor C4, pin 5 of the chip U2 is also connected with one end of the resistor R2, and the other end of the resistor R2 is used for being connected with the B+ end of the battery pack;
the pin 4 of the chip U2 is connected with the analog ground through the capacitor C5, and the pin 6 of the chip U2 is used for connecting with the B-end of the battery pack and is connected with the analog ground; the pin 4 of the chip U2 is also connected with one end of a resistor R7, and the other end of the resistor R7 is used for being connected with the VC end of the battery pack;
the pin 4 of the first MOS chip Q2, the pin 6 of the second MOS chip Q3 and the pin 4 of the third MOS chip Q4 are all connected with the pin 2 of the chip U2, and the pin 6 of the first MOS chip Q2, the pin 4 of the second MOS chip Q3 and the pin 6 of the third MOS chip Q4 are all connected with the pin 1 of the chip U2;
the pin 3 of the first MOS chip Q2, the pin 1 of the second MOS chip Q3 and the pin 3 of the third MOS chip Q4 are all grounded digitally, the pin 3 of the third MOS chip Q4 is connected with the pin 1 of the third MOS chip Q4 through a capacitor C9 and a capacitor C10, and the pin 1 of the first MOS chip Q2, the pin 3 of the second MOS chip Q3 and the pin 1 of the third MOS chip Q4 are all grounded in an analog mode.
6. The intelligent door lock equalizing charge circuit according to claim 1, wherein: the device further comprises a discharging interface J2, wherein a pin 5 of the discharging interface J2 is connected with a B9 pin of the charging interface J1, the pin 5 of the discharging interface J2 is also connected with one end of the bidirectional TVS tube ESD1, and the pin 5 of the discharging interface J2 is also connected with digital ground through a capacitor C7;
both the pin 2 and the pin 4 of the discharging interface J2 are grounded digitally, the other end of the bidirectional TVS tube ESD1 is connected with the pin 2 of the discharging interface J2, the pin 2 of the discharging interface J2 is connected with the pin 1 of the discharging interface J2 through the bidirectional TVS tube ESD2, the pin 1 of the discharging interface J2 is used for being connected with the B-end of the battery pack, and the pin of the discharging interface J1 is connected with the pin 2 of the discharging interface J2 through a capacitor C8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321414316.6U CN220306969U (en) | 2023-06-05 | 2023-06-05 | Intelligent door lock equalizing charge circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321414316.6U CN220306969U (en) | 2023-06-05 | 2023-06-05 | Intelligent door lock equalizing charge circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220306969U true CN220306969U (en) | 2024-01-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321414316.6U Active CN220306969U (en) | 2023-06-05 | 2023-06-05 | Intelligent door lock equalizing charge circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220306969U (en) |
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2023
- 2023-06-05 CN CN202321414316.6U patent/CN220306969U/en active Active
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