CN220290795U - Wafer packaging structure - Google Patents
Wafer packaging structure Download PDFInfo
- Publication number
- CN220290795U CN220290795U CN202321866989.5U CN202321866989U CN220290795U CN 220290795 U CN220290795 U CN 220290795U CN 202321866989 U CN202321866989 U CN 202321866989U CN 220290795 U CN220290795 U CN 220290795U
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor substrate
- passivation layer
- wafer packaging
- solder balls
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 238000002161 passivation Methods 0.000 claims abstract description 28
- 229910000679 solder Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000010410 layer Substances 0.000 claims description 62
- 239000011241 protective layer Substances 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 abstract description 4
- 230000007797 corrosion Effects 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 230000002035 prolonged effect Effects 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model relates to the technical field of wafer packaging, in particular to a wafer packaging structure which comprises a base, a semiconductor substrate and solder balls, wherein the upper end of the base is fixedly connected with the semiconductor substrate, the upper end of the semiconductor substrate is fixedly connected with a dielectric layer, the solder balls are arranged in the dielectric layer, an under-ball metal layer is arranged in the solder balls, and metal cores are arranged in the under-ball metal layer. Through the structure, the semiconductor substrate is fixedly connected to the upper end of the base, so that the semiconductor device can be effectively supported and protected, the conductivity and stability of the solder balls are improved, the mismatching of stress and thermal expansion coefficient between the solder balls and the passivation layer is reduced, and the service life of the wafer packaging structure is prolonged. The insulating adhesion layer at the lower end of the passivation layer can enhance the corrosion resistance and oxidation resistance of the passivation layer, prevent the passivation layer from being damaged due to the influence of external environment, and improve the bonding strength and reliability between the insulating adhesion layer and the substrate.
Description
Technical Field
The present disclosure relates to wafer packaging technology, and more particularly, to a wafer packaging structure.
Background
The wafer packaging structure is a semiconductor packaging technology, and utilizes a film technology and a micro-connection technology to arrange, fix and connect semiconductor components and other components on a frame or a substrate, lead out wiring terminals, and encapsulate and fix the wiring terminals through plastic insulating media to form a process of an integral main body structure. The wafer packaging structure has the main functions of protecting the circuit chip from the surrounding environment, keeping the electrical characteristics of the chip, relieving stress, adjusting size fit and the like. In the related art, the stress and the thermal expansion coefficient between the solder ball and the passivation layer of the wafer packaging structure are not matched, so that the conductivity and the stability of the solder ball are general, and the flatness and the tightness of the wafer packaging are lower due to the redundant materials between the dielectric layer and the semiconductor substrate in the packaging process;
the above information disclosed in this background section is only for the understanding of the background of the inventive concept and, therefore, it may contain information that does not form the prior art.
Disclosure of Invention
The utility model aims to provide a wafer packaging structure, which solves the problems that the stress and the thermal expansion coefficient between a solder ball and a passivation layer of the wafer packaging structure are not matched in the prior art, so that the conductivity and the stability of the solder ball are common, and the flatness and the sealing performance of the wafer packaging are lower due to redundant materials between a dielectric layer and a semiconductor substrate in the packaging process.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
the wafer packaging structure comprises a base, a semiconductor substrate and solder balls, wherein the upper end of the base is fixedly connected with the semiconductor substrate, the upper end of the semiconductor substrate is fixedly connected with a dielectric layer, the solder balls are arranged in the dielectric layer, an under-ball metal layer is arranged in the solder balls, and a metal core is arranged in the under-ball metal layer.
As a preferable technical scheme, a groove is formed on one side of the dielectric layer.
As a preferable technical scheme, the lower end of the metal core is fixedly connected with a conductive metal pad, and the conductive metal pad is embedded in the passivation layer.
As a preferable technical scheme, a protective layer is arranged at the upper end of the passivation layer.
As a preferable technical scheme, an insulating adhesion layer is arranged at the lower end of the passivation layer, and the lower end of the insulating adhesion layer is connected with the substrate.
The beneficial effects of the utility model are as follows:
through the structure, the semiconductor substrate is fixedly connected to the upper end of the base, so that the semiconductor device can be effectively supported and protected, the conductivity and stability of the solder balls are improved, the mismatching of stress and thermal expansion coefficient between the solder balls and the passivation layer is reduced, and the service life of the wafer packaging structure is prolonged. The insulating adhesion layer at the lower end of the passivation layer can enhance the corrosion resistance and oxidation resistance of the passivation layer, prevent the passivation layer from being damaged due to the influence of external environment, improve the bonding strength and reliability between the insulating adhesion layer and the substrate, and conveniently remove redundant materials between the dielectric layer and the semiconductor substrate by the groove at one side of the dielectric layer, so that a flat contact surface is formed between the dielectric layer and the semiconductor substrate, the flatness and the sealing performance of the wafer packaging structure are improved, and the practicability of the structure is improved.
Drawings
FIG. 1 is a schematic diagram of a wafer package structure according to the present utility model;
fig. 2 is a schematic structural diagram of a solder ball of a wafer package structure according to the present utility model.
In the figure: 1 base, 2 semiconductor substrate, 3 groove, 4 solder ball, 5 dielectric layer, 6 under ball metal layer, 7 conductive metal pad, 8 metal core, 9 substrate, 10 protective layer, 11 passivation layer, 12 insulating adhesive layer.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments.
In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Referring to fig. 1-2, a wafer packaging structure comprises a base 1, a semiconductor substrate 2 and solder balls 4, wherein the upper end of the base 1 is fixedly connected with the semiconductor substrate 2, the upper end of the semiconductor substrate 2 is fixedly connected with a dielectric layer 5, and the solder balls 4 are arranged in the dielectric layer 5.
Wherein, the ball under-ball metal layer 6 is arranged in the solder ball 4, the metal core 8 is arranged in the ball under-ball metal layer 6, the lower end of the metal core 8 is fixedly connected with the conductive metal pad 7, and the conductive metal pad 7 is embedded in the passivation layer 11.
Through the design, the semiconductor substrate 2 is fixedly connected to the upper end of the base 1, so that a semiconductor device can be effectively supported and protected, the conductivity and stability of the solder balls 4 are improved, the mismatch of stress and thermal expansion coefficient between the solder balls 4 and the passivation layer 11 is reduced, and the service life of the wafer packaging structure is prolonged.
In other embodiments, the passivation layer 11 is provided with a protective layer 10 at an upper end, the passivation layer 11 is provided with an insulating adhesion layer 12 at a lower end, and the lower end of the insulating adhesion layer 12 is connected to the substrate 9.
By this design, the insulating adhesive layer 12 at the lower end of the passivation layer 11 can enhance the corrosion resistance and oxidation resistance of the passivation layer 11, prevent the passivation layer 11 from being damaged by the influence of the external environment, and improve the adhesion strength and reliability between the insulating adhesive layer 12 and the substrate 9.
In other embodiments, one side of the dielectric layer 5 is provided with a recess 3.
Through the design, the groove 3 on one side of the dielectric layer 5 can conveniently remove redundant materials between the dielectric layer 5 and the semiconductor substrate 2, so that a flat contact surface is formed between the dielectric layer 5 and the semiconductor substrate 2, and the flatness and the tightness of the wafer packaging structure are improved.
In this embodiment, the semiconductor substrate 2 is fixedly connected to the upper end of the base 1, so that the semiconductor device can be effectively supported and protected, the conductivity and stability of the solder balls 4 are improved, the mismatch of stress and thermal expansion coefficient between the solder balls 4 and the passivation layer 11 is reduced, and the service life of the wafer packaging structure is prolonged. The insulating adhesion layer 12 at the lower end of the passivation layer 11 can enhance the corrosion resistance and oxidation resistance of the passivation layer 11, prevent the passivation layer 11 from being damaged due to the influence of external environment, improve the bonding strength and reliability between the insulating adhesion layer 12 and the substrate 9, and conveniently remove redundant materials between the dielectric layer 5 and the semiconductor substrate 2 by the groove 3 at one side of the dielectric layer 5, so that a flat contact surface is formed between the dielectric layer 5 and the semiconductor substrate 2, the flatness and the sealing performance of the wafer packaging structure are improved, and the practicability of the structure is improved.
The foregoing is only a preferred embodiment of the present utility model, but the scope of the present utility model is not limited thereto, and any person skilled in the art, who is within the scope of the present utility model, should make equivalent substitutions or modifications according to the technical scheme of the present utility model and the inventive concept thereof, and should be covered by the scope of the present utility model.
Claims (5)
1. The utility model provides a wafer packaging structure, includes base (1), semiconductor substrate (2) and solder ball (4), its characterized in that, the upper end fixed connection semiconductor substrate (2) of base (1), the upper end fixed connection dielectric layer (5) of semiconductor substrate (2), the inside of dielectric layer (5) is provided with solder ball (4), the inside of solder ball (4) is provided with ball under metal layer (6), the inside of ball under metal layer (6) is provided with metal core (8).
2. A wafer package according to claim 1, characterized in that a recess (3) is provided in one side of the dielectric layer (5).
3. The wafer packaging structure according to claim 1, wherein the lower end of the metal core (8) is fixedly connected with a conductive metal pad (7), and the conductive metal pad (7) is embedded in the passivation layer (11).
4. A wafer package according to claim 3, wherein the passivation layer (11) is provided with a protective layer (10) at its upper end.
5. A wafer packaging structure according to claim 3, characterized in that the passivation layer (11) is provided at its lower end with an insulating adhesion layer (12), the lower end of the insulating adhesion layer (12) being connected to the substrate (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321866989.5U CN220290795U (en) | 2023-07-17 | 2023-07-17 | Wafer packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321866989.5U CN220290795U (en) | 2023-07-17 | 2023-07-17 | Wafer packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220290795U true CN220290795U (en) | 2024-01-02 |
Family
ID=89325859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321866989.5U Active CN220290795U (en) | 2023-07-17 | 2023-07-17 | Wafer packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220290795U (en) |
-
2023
- 2023-07-17 CN CN202321866989.5U patent/CN220290795U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3907461B2 (en) | Manufacturing method of semiconductor module | |
| JP3967133B2 (en) | Manufacturing method of semiconductor device and electronic device | |
| TW302528B (en) | ||
| US8916958B2 (en) | Semiconductor package with multiple chips and substrate in metal cap | |
| US20030034490A1 (en) | Technique for attaching die to leads | |
| US20070096265A1 (en) | Multiple die integrated circuit package | |
| KR100514023B1 (en) | Semiconductor device | |
| WO1992000605A1 (en) | Metal electronic package having improved resistance to electromagnetic interference | |
| KR20020072145A (en) | Stacking structure of semiconductor chip and semiconductor package using it | |
| JPH0974115A (en) | Tape carrier package | |
| US9230937B2 (en) | Semiconductor device and a manufacturing method thereof | |
| US20070096308A1 (en) | Semiconductor device | |
| CN103367265A (en) | Multilayered semiconductor device, printed circuit board, and method of manufacturing multilayered semiconductor device | |
| US6573608B2 (en) | Semiconductor device with layered semiconductor chips | |
| CN220290795U (en) | Wafer packaging structure | |
| US20080087995A1 (en) | Flexible film semiconductor package and method for manufacturing the same | |
| CN101866889B (en) | Substrate-free chip packaging and manufacturing method thereof | |
| CN221262363U (en) | Wafer encapsulation cooling mechanism | |
| US7521778B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN210805734U (en) | Ultra-thin small volume packaging structure of chip | |
| JPS61287254A (en) | Semiconductor device | |
| JP3906233B2 (en) | Semiconductor device | |
| CN113851449A (en) | Packaging substrate with fault tolerance and semiconductor device | |
| CN112490209A (en) | Semiconductor packaging device | |
| JPH0917910A (en) | Semiconductor device and its manufacture, inspection method and mounting board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |