CN220189228U

CN220189228U - Liquid crystal drive odd-even scanning line opening sequence adjusting circuit

Info

Publication number: CN220189228U
Application number: CN202320480224.1U
Authority: CN
Inventors: 刘家朝; 马刚峰
Original assignee: Xi'an Xinyuan Micro Technology Co ltd
Current assignee: Xi'an Xinyuan Micro Technology Co ltd
Priority date: 2023-03-14
Filing date: 2023-03-14
Publication date: 2023-12-15
Anticipated expiration: 2033-03-14

Abstract

The utility model provides a liquid crystal drive odd-even scanning line opening sequence adjusting circuit, which belongs to the technical field of liquid crystal drive circuits, and is used for integrating clock scanning signals and comprises two diodes; the anodes of the two diodes are respectively connected with two groups of clock scanning signals generated by 1 chip, the two groups of clock scanning signals are integrated into one group of clock scanning signals, the high and low levels of 2 clock signals are generated in the original 1 clock signal period, and the integrated and overlapped clock scanning signals are used as the input of the LSIC. The liquid crystal driving odd-even scanning line opening sequence adjusting circuit provided by the utility model achieves the effect of 2 Levelshift under the condition that 1 Levelshift IC is used for the first time in the industry, and realizes hybrid charging.

Description

Liquid crystal drive odd-even scanning line opening sequence adjusting circuit

Technical Field

The utility model belongs to the technical field of liquid crystal driving circuits, and particularly relates to a liquid crystal driving odd-even scanning line opening sequence adjusting circuit.

Background

As shown in fig. 1, the design of the liquid crystal driving odd-even scanning line opening sequence adjusting circuit in the current panel industry is realized by using 2 Level shift (LS for short, potential translation chip), the opening time of the even-numbered line and the odd-numbered line scanning lines are different, the opening time of the even-numbered line scanning lines partially overlaps the data of the next odd-numbered line, and the charge charging of the pixels of the even-numbered line and the pixels of the two odd-numbered lines is realized, at this time, the pixel signal of the data line is the time of 2 scanning lines.

How to realize the odd-even scanning line opening sequence adjustment under the condition of saving the Level shift resource is a problem to be solved.

Disclosure of Invention

In order to overcome the defects in the prior art, the utility model provides a liquid crystal driving odd-even scanning line opening sequence adjusting circuit.

In order to achieve the above object, the present utility model provides the following technical solutions:

the liquid crystal driving odd-even scanning line opening sequence adjusting circuit comprises two diodes, wherein the anodes of the two diodes are connected with a clock chip, and the cathodes of the two diodes are connected with an LS chip;

the clock chip generates two groups of clock scanning signals, the two groups of clock scanning signals are overlapped into one group of clock scanning signals by the two diodes, and the overlapped clock scanning signals are used as the output of the LS chip.

Preferably, the duty cycle of the clock signal is less than 50%.

Preferably, the clock chip is a display timing controller, and 2 groups of clock scanning signals are generated by the display timing controller.

Preferably, the clock chip is a display television main chip, and 2 groups of clock scanning signals are generated by the display television main chip.

Preferably, the time positions of the even clock high levels of the set of clock scan signals formed by superimposing the two diodes can be arbitrarily adjusted among the 2 odd clock high levels, wherein roles of the odd and even can be exchanged.

Preferably, a group of clock scanning signals formed by overlapping two diodes is used as an input end of the LS chip, and the time position of the falling edge of the even clock signal of the LS output end can be randomly adjusted among the falling edges of the 2 odd clock signals, wherein the roles of the odd and even numbers can be exchanged.

Preferably, the diode adopts a diode with a conduction voltage characteristic of 0.6V.

The liquid crystal driving odd-even scanning line opening sequence adjusting circuit provided by the utility model is used for overlapping two groups of clock scanning signals into one group of clock scanning signals through the two diodes, and integrating the overlapped clock scanning signals as the input of the LS chip, so that the effect of 2 Level shift ICs is achieved under the condition that 1 Level shift IC is used for the first time in the industry, the resources are saved, the mixed charging is realized, and the aim of adjusting the opening sequence of the liquid crystal driving odd-even scanning line is realized.

Drawings

In order to more clearly illustrate the embodiments of the present utility model and the design thereof, the drawings required for the embodiments will be briefly described below. The drawings in the following description are only some of the embodiments of the present utility model and other drawings may be made by those skilled in the art without the exercise of inventive faculty.

FIG. 1 is a timing diagram of a conventional 2 Level shift chip implementing a liquid crystal driving odd-even scan line turn-on sequence adjustment circuit;

FIG. 2 is a schematic diagram showing the structure of the liquid crystal driving odd-even scanning line turn-on sequence adjusting circuit according to embodiment 1 of the present utility model;

FIG. 3 is a timing chart comparing 1 Level shift IC of the embodiment 1 of the present utility model with 2 Level shift IC circuits for odd-even scan line opening sequence adjustment;

fig. 4 is a scanning schematic diagram of clock signals ck1_tcon/CK2, TCON/ls_ckin before and after integration.

Detailed Description

The present utility model will be described in detail below with reference to the drawings and the embodiments, so that those skilled in the art can better understand the technical scheme of the present utility model and can implement the same. The following examples are only for more clearly illustrating the technical aspects of the present utility model, and are not intended to limit the scope of the present utility model.

Example 1

In the design of the liquid crystal driving circuit, clock scanning signals generated by original digital chips or television main chips are in one-to-one correspondence with data materials, after 2 clock scanning signals generated by 1 digital chip or television main chips are integrated through diodes, namely, the integrated and overlapped clock scanning signals are twice of the original clock scanning signals, and meanwhile, the integrated and overlapped clock scanning signals are twice of the original data materials, odd-even row clock scanning lines are generated, the phase of the integrated and overlapped clock scanning signals is still controllable, and the integrated and overlapped clock scanning signals are used as the input of LS chips, so that the adjustment of the opening sequence of the liquid crystal driving odd-even scanning lines is realized.

Based on this, the utility model provides a liquid crystal driving odd-even scanning line opening sequence adjusting circuit, which is used for integrating clock scanning signals and comprises two diodes; the anodes of the two diodes are connected with the clock chip. Specifically, a diode having a turn-on voltage characteristic of 0.6V is employed in the present embodiment.

The clock chip generates two groups of clock scanning signals, the two groups of clock scanning signals are overlapped into one group of clock scanning signals by the two diodes, the high and low levels of 2 clock signals are generated in the original 1 clock signal period, the overlapped clock scanning signals are integrated to serve as the input of the LS chip, and the adjustment of the starting sequence of the liquid crystal driving odd-even scanning lines is realized. Or the digital chip directly outputs a group of clock scanning signals which are overlapped with the external circuit and have the same effect; at this time, the pixel signal of one data line is at the high level of 2 clock signals, and the duty ratio of the clock signals is required to be less than 50%.

Specifically, in the present embodiment, 2 sets of clock scan signals are generated by the display timing controller, and the relative positions of 2 scan clocks in one data line pixel signal can be controlled.

Alternatively, in this embodiment, 2 sets of clock scan signals are generated by the display television main chip, and the relative positions of 2 scan clocks in one data line pixel signal can be controlled.

Further, in this embodiment, the time positions of the even-numbered clock high levels of the superimposed clock scan signal can be arbitrarily adjusted among the 2 odd-numbered clock high levels, wherein the roles of the odd-numbered and even-numbered can be exchanged.

Further, in this embodiment, the superimposed clock scan signal is used as the input terminal of the LS chip, and the time position of the falling edge of the even clock signal of the LS output terminal can be arbitrarily adjusted in the middle of the falling edges of the 2 odd clock signals, where the roles of the odd and even clock signals can be exchanged.

As shown in fig. 2, taking GM2592 as an example, the LS IC requires a digital chip or a television main chip to input 1 clock signal of ls_ckin to control the generation of the output liquid crystal driving scan line.

As shown in fig. 2 and 3, the present embodiment uses a digital chip to generate 2 clock signal inputs of ck1_tcon and ck2_tcon, and the clock signal inputs are integrated into 1 ls_ckin through 2 diodes, so that the high and low levels of 2 clock signals can be generated in 1 clock signal period.

The scanning lines and the data line periods output by the LS IC are in one-to-one correspondence in the normal 60Hz 4K2K mode.

In the original single LS IC,120Hz 4K1K mode, the scanning lines of the LS IC are twice as many as the scanning lines of the data, namely, 2 rows of scanning lines exist in 1 row of data.

Originally, under the mode of using 2 LS ICs and 120Hz 4K1K, 2 LS ICs generate 2 groups of independent scanning lines, namely, the opening sequence adjustment of odd-even scanning lines is realized, and the color mixing of even-numbered rows of pixels to the data of the next row is achieved.

In this embodiment, under a single LS, the digital chip generates 2 clock signals of ck1_tcon and ck2_tcon, which are input and integrated and superimposed into 1 ls_ckin in a 120Hz 4k1k mode, so that the high and low levels of 2 clock signals can be generated in the original 1 clock signal period, one of the 2 clock signals controls the odd scan lines, and the other controls the even scan lines, i.e. the opening sequence adjustment of the odd scan lines is realized, so that the even row or the odd row of pixels are mixed into the data of the next row.

As shown in fig. 4, the scan lines 1-8, the data signal and the TP of the data are outputted by the clock signals ck1_tcon/ck2_tcon/ls_ckin, LS IC before and after integration in the embodiment.

Since LS_CKIN is a superimposed clock signal, 2 Hpulses are provided in the 1-line data, i.e. the on and off times of the odd-numbered scan lines and the even-numbered scan lines are controlled respectively.

As shown in fig. 4, the pixel color mixing of the row can be controlled to the data of the next row by controlling the off time of the LS out scan line 2.

The above embodiments are merely preferred embodiments of the present utility model, the protection scope of the present utility model is not limited thereto, and any simple changes or equivalent substitutions of technical solutions that can be obviously obtained by those skilled in the art within the technical scope of the present utility model disclosed in the present utility model belong to the protection scope of the present utility model.

Claims

1. The liquid crystal driving odd-even scanning line opening sequence adjusting circuit is characterized by comprising two diodes, wherein the anodes of the two diodes are connected with a clock chip, and the cathodes of the two diodes are connected with an LS chip;

the clock chip generates two groups of clock scanning signals, the two groups of clock scanning signals are overlapped into one group of clock scanning signals by the two diodes, and the overlapped clock scanning signals are used as the input of the LS chip.

2. The liquid crystal driving odd-even scanning line on-order adjustment circuit according to claim 1, wherein a duty ratio of the clock scanning signal is less than 50%.

3. The liquid crystal driving odd-even scanning line opening sequence adjusting circuit according to claim 1, wherein the clock chip is a display timing controller, and 2 sets of the clock scanning signals are generated by the display timing controller.

4. The liquid crystal driving odd-even scanning line opening sequence adjusting circuit according to claim 1, wherein the clock chip is a display television main chip, and 2 groups of the clock scanning signals are generated by the display television main chip.

5. The liquid crystal driving odd-even scanning line turn-on sequence adjusting circuit according to claim 1, wherein the time positions of the even clock high levels of a group of clock scanning signals formed by superimposing two of the diodes can be arbitrarily adjusted among the 2 odd clock high levels, wherein roles of the odd and even can be exchanged.

6. The circuit according to claim 1, wherein a set of clock scan signals formed by superimposing two of the diodes is used as an input terminal of the LS chip, and a time position of a falling edge of an even clock signal of an output terminal of the LS is arbitrarily adjustable among falling edges of 2 odd clock signals, wherein roles of the odd and even are exchanged.

7. The liquid crystal driving odd-even scanning line turn-on sequence adjusting circuit according to claim 1, wherein the diode adopts a diode having an on-voltage characteristic of 0.6V.