CN220139421U - Gate driving chip with built-in positive temperature coefficient temperature sensing circuit - Google Patents

Abstract

A grid driving chip with a built-in positive temperature coefficient temperature sensing circuit comprises a low-side circuit and a high-side circuit; the low-side circuit consists of a high-side signal input port HIN, a low-side signal input port LIN, a corresponding filter circuit, a positive temperature coefficient sensing circuit, a dead time control circuit, a pulse generation circuit, a low-voltage locking circuit, a delay circuit, output logic, a PMOS driving tube P2, an NMOS driving tube N2, output resistors XR3 and XR4 and an output port LO; the high-side circuit is composed of a bootstrap diode, a level shift circuit, low-voltage locking, output logic, a PMOS driving tube P1, an NMOS driving tube N1, output resistors XR1 and XR2 and an output port HO. The utility model adopts the single-chip integrated positive temperature coefficient temperature sensing circuit, and the positive temperature coefficient temperature sensing circuit and the grid driving circuit are integrated in a single chip, so that the flexibility of monitoring the temperature by the terminal application is improved, the temperature sensing precision is improved, and the cost of the terminal application is reduced.

Description

Gate driving chip with built-in positive temperature coefficient temperature sensing circuit

Technical Field

The utility model relates to a gate driving chip, in particular to a gate driving chip with a built-in positive temperature coefficient temperature sensing circuit.

Background

The grid driving chip is used for receiving control signals of external digital chips such as a CPU (Central processing Unit) or an MCU (micro control Unit) and providing grid signals required by controlling and driving the power device, and is widely applied. The grid driving chip is used as a switch of a power device to cause power loss and conduction loss, so that the chip heats; in addition, the operating environment of the gate drive chip and the power device may contain extremely high heat, which may cause the junction temperature of the gate drive chip or the power device to exceed a maximum value, resulting in damage. In general, a thermistor or a thermal diode is used alone to monitor the temperature of the system, when the temperature of the system reaches a set limit value, the power is reduced, and when the temperature exceeds a maximum threshold value, the power device is completely turned off, so that the safety of the system is ensured.

In the conventional gate driving scheme, a thermistor or a thermal diode is adopted to monitor the temperature of the system, and a device is required to be separately configured to process the temperature sensing signal, so that the hardware cost is increased. In addition, temperature measurement accuracy is a critical factor, and in cases where it is not necessary, it is not preferable to reduce power. If the accuracy is poor, the power device may still be subject to excessive heat and degrade over time.

Disclosure of Invention

In order to solve the above problems, an object of the present utility model is to provide a gate driving chip with a built-in positive temperature coefficient temperature sensing circuit, which monolithically integrates a positive temperature coefficient temperature sensing circuit and a gate driving circuit.

In order to achieve the above purpose, the technical scheme of the utility model is as follows: a grid driving chip with a built-in positive temperature coefficient temperature sensing circuit comprises a low-side circuit and a high-side circuit; the low-side circuit consists of a high-side signal input port HIN, a low-side signal input port LIN, a corresponding filter circuit, a positive temperature coefficient sensing circuit, a dead time control circuit, a pulse generation circuit, a low-voltage locking circuit, a delay circuit, output logic, a PMOS driving tube P2, an NMOS driving tube N2, output resistors XR3 and XR4 and an output port LO; the high-side circuit consists of a bootstrap diode, a level shift circuit, low-voltage locking, output logic, a PMOS driving tube P1, an NMOS driving tube N1, output resistors XR1 and XR2 and an output port HO; the high-side signal input port HIN and the low-side signal input port LIN are connected with the corresponding filter circuits and then connected with the dead time control circuit; the dead time control circuit is respectively connected with the pulse generating circuit and the low-voltage locking and delaying circuit in the low-side circuit; a low-voltage lock-in connection voltage VCC in the low-side circuit; the pulse generating circuit is connected with the level shifting circuit; the delay circuit is connected with the grid electrode of the PMOS driving tube P2 and the grid electrode of the NMOS driving tube N2 after being connected with output logic in the low-side circuit, the drain electrode of the PMOS driving tube P2 is connected with the output port LO after being connected with the output resistor XR3, and the source electrode of the PMOS driving tube P2 is connected with the voltage VCC; the drain electrode of the NMOS driving tube N2 is connected with the output port LO after being connected with the output resistor XR4, and the source electrode is connected with the voltage VSS; one end of the bootstrap diode is connected with voltage VCC, and the other end of the bootstrap diode is connected with voltage VB; one end of the low-voltage lock in the high-side circuit is connected with voltage VB, and the other end is connected with output logic in the high-side circuit; the level shift circuit is connected with output logic in the high-side circuit and then connected with the grid electrode of the PMOS driving tube P1 and the grid electrode of the NMOS driving tube N1, the drain electrode of the PMOS driving tube P1 is connected with the output resistor XR1 and then connected with an output port HO, and the source electrode of the PMOS driving tube P1 is connected with a voltage VB; the drain electrode of the NMOS driving tube N1 is connected with the output port HO after being connected with the output resistor XR2, and the source electrode is connected with the voltage VS.

Further, the positive temperature coefficient sensing circuit comprises a starting circuit, a positive temperature coefficient voltage generating circuit and a voltage following circuit I0; the starting circuit comprises P-type field effect transistors MP1 and MP2, N-type field effect transistors MN1 and MN2 and a diode D1; the positive temperature coefficient voltage generating circuit comprises P-type field effect transistors MP3, MP4 and MP5, triodes Q1 and Q2 and resistors R1 and R2; the sources of the P-type field effect transistors MP1, MP2, MP3, MP4 and MP5 are connected with a voltage VDD; the grid electrode of the P-type field effect transistor MP1 and the source electrodes of the N-type field effect transistors MN1 and MN2 are grounded; the drain electrode of the N-type field effect transistor MN1 is connected with the drain electrode of the P-type field effect transistor MP1, and the grid electrode of the N-type field effect transistor MN2 is connected with the grid electrode; the grid electrode of the N-type field effect transistor MN2 is connected with the drain electrode, and the drain electrode is connected with the drain electrode of the P-type field effect transistor MP 2; the grid electrode of the P-type field effect tube MP2 is connected with the grid electrode of the P-type field effect tube MP3 and the grid electrode of the P-type field effect tube MP 4; the drain electrode of the P-type field effect transistor MP3 is connected with the collector electrode of the triode Q1; the base electrode of the triode Q1 is connected with the collector electrode, and the emitter electrode is grounded; the anode of the diode D1 is connected with the drain electrode of the P-type field effect transistor MP1, and the cathode is connected with the drain electrode of the P-type field effect transistor MP 3; the grid electrode of the P-type field effect transistor MP4 is connected with the drain electrode, and the drain electrode is connected with the collector electrode of the triode Q2; the base electrode of the triode Q2 is connected with the base electrode of the triode Q1, and the emitter is connected with the resistor R1 in series and then grounded; the grid electrode of the P-type field effect tube MP5 is connected with the drain electrode of the P-type field effect tube MP4, and the drain electrode is connected with the resistor R2 in series and then grounded; the positive input end of the voltage follower circuit I0 is connected with the drain electrode of the P-type field effect transistor MP5, and the negative input end is connected with the output end.

Furthermore, the positive and negative input ends of the voltage follower circuit I0 are made of P-type field effect transistors, and the input and output currents are approximately zero.

Further, the resistors R1 and R2 are of the same type and are closely matched.

The utility model has the beneficial effects that (1) the adopted positive temperature coefficient sensing technology adopts the positive temperature coefficient temperature sensing circuit which can be monolithically integrated, the positive temperature coefficient temperature sensing circuit and the grid driving circuit are monolithically integrated, the flexibility of monitoring the temperature by the terminal application is improved, the accuracy of temperature sensing is improved, and the cost of the terminal application is reduced. (2) Compared with other traditional temperature sensors such as the existing thermistor, thermocouple, RTDS and the like, the positive temperature coefficient sensing circuit has the advantages of small volume, good reproducibility, easy operation and high integration. (3) The whole circuit is designed for micro power consumption, the temperature rise of consumed current generated by a chip is negligible, the influence of the circuit on the temperature test of the temperature sensing circuit is reduced, and the accuracy of the temperature test is improved.

Drawings

FIG. 1 is a block diagram of the gate driver chip of the present utility model; FIG. 2 shows a positive temperature coefficient sensor circuit according to the present utility model.

Description of the embodiments

Specific embodiments of the present utility model are described in detail below with reference to the accompanying drawings.

As shown in fig. 1: a grid driving chip with a built-in positive temperature coefficient temperature sensing circuit comprises a low-side circuit and a high-side circuit; the low-side circuit consists of a high-side signal input port HIN, a low-side signal input port LIN, a corresponding filter circuit, a positive temperature coefficient sensing circuit, a dead time control circuit, a pulse generation circuit, a low-voltage locking circuit, a delay circuit, output logic, a PMOS driving tube P2, an NMOS driving tube N2, output resistors XR3 and XR4 and an output port LO; the high-side circuit consists of a bootstrap diode, a level shift circuit, low-voltage locking, output logic, a PMOS driving tube P1, an NMOS driving tube N1, output resistors XR1 and XR2 and an output port HO; the high-side signal input port HIN and the low-side signal input port LIN are connected with the corresponding filter circuits and then connected with the dead time control circuit; the dead time control circuit is respectively connected with the pulse generating circuit and the low-voltage locking and delaying circuit in the low-side circuit; a low-voltage lock-in connection voltage VCC in the low-side circuit; the pulse generating circuit is connected with the level shifting circuit; the delay circuit is connected with the grid electrode of the PMOS driving tube P2 and the grid electrode of the NMOS driving tube N2 after being connected with output logic in the low-side circuit, the drain electrode of the PMOS driving tube P2 is connected with the output port LO after being connected with the output resistor XR3, and the source electrode of the PMOS driving tube P2 is connected with the voltage VCC; the drain electrode of the NMOS driving tube N2 is connected with the output port LO after being connected with the output resistor XR4, and the source electrode is connected with the voltage VSS; one end of the bootstrap diode is connected with voltage VCC, and the other end of the bootstrap diode is connected with voltage VB; one end of the low-voltage lock in the high-side circuit is connected with voltage VB, and the other end is connected with output logic in the high-side circuit; the level shift circuit is connected with output logic in the high-side circuit and then connected with the grid electrode of the PMOS driving tube P1 and the grid electrode of the NMOS driving tube N1, the drain electrode of the PMOS driving tube P1 is connected with the output resistor XR1 and then connected with an output port HO, and the source electrode of the PMOS driving tube P1 is connected with a voltage VB; the drain electrode of the NMOS driving tube N1 is connected with the output port HO after being connected with the output resistor XR2, and the source electrode is connected with the voltage VS.

As shown in fig. 2: the positive temperature coefficient sensing circuit comprises a starting circuit, a positive temperature coefficient voltage generating circuit and a voltage following circuit I0; the starting circuit comprises P-type field effect transistors MP1 and MP2, N-type field effect transistors MN1 and MN2 and a diode D1; the positive temperature coefficient voltage generating circuit comprises P-type field effect transistors MP3, MP4 and MP5, triodes Q1 and Q2 and resistors R1 and R2; the sources of the P-type field effect transistors MP1, MP2, MP3, MP4 and MP5 are connected with a voltage VDD; the grid electrode of the P-type field effect transistor MP1 and the source electrodes of the N-type field effect transistors MN1 and MN2 are grounded; the drain electrode of the N-type field effect transistor MN1 is connected with the drain electrode of the P-type field effect transistor MP1, and the grid electrode of the N-type field effect transistor MN2 is connected with the grid electrode; the grid electrode of the N-type field effect transistor MN2 is connected with the drain electrode, and the drain electrode is connected with the drain electrode of the P-type field effect transistor MP 2; the grid electrode of the P-type field effect tube MP2 is connected with the grid electrode of the P-type field effect tube MP3 and the grid electrode of the P-type field effect tube MP 4; the drain electrode of the P-type field effect transistor MP3 is connected with the collector electrode of the triode Q1; the base electrode of the triode Q1 is connected with the collector electrode, and the emitter electrode is grounded; the anode of the diode D1 is connected with the drain electrode of the P-type field effect transistor MP1, and the cathode is connected with the drain electrode of the P-type field effect transistor MP 3; the grid electrode of the P-type field effect transistor MP4 is connected with the drain electrode, and the drain electrode is connected with the collector electrode of the triode Q2; the base electrode of the triode Q2 is connected with the base electrode of the triode Q1, and the emitter is connected with the resistor R1 in series and then grounded; the grid electrode of the P-type field effect tube MP5 is connected with the drain electrode of the P-type field effect tube MP4, and the drain electrode is connected with the resistor R2 in series and then grounded; the positive input end of the voltage follower circuit I0 is connected with the drain electrode of the P-type field effect transistor MP5, and the negative input end is connected with the output end.

A start circuit part: when the power-on process of the power supply voltage VDD is finished, the P-type field effect tube MP4 provides stable bias current, the P-type field effect tube MP2 and the MP4 form a relation of a current mirror, the N-type field effect tube MN1 and the N-type field effect tube MN2 also form a relation of a current mirror, and the width-to-length ratio of the P-type field effect tube is far smaller than that of the N-type field effect tube, so that the drain end potential of the N-type field effect tube MN1, namely the anode potential of the diode D1, is pulled down to a level close to GND, and the diode D1 is cut off, so that the starting circuit is separated from a main circuit of the positive temperature coefficient temperature sensing circuit, and the starting process of the circuit is completed.

The current of the P-type field effect transistor MP4 in the ptc voltage generating circuit, which is the main circuit of the ptc temperature sensing circuit, is determined by the following equation:

……………………（1）

in the formula, vbeQ1 and VbeQ2 are respectively forward conduction voltages of bases and emitters of the triodes Q1 and Q2;is thermal voltage, physical quantity; />And->Collector currents of transistors Q1 and Q2, respectively, +.>；/>And->The physical quantity is related to the base-emitter junction area of the transistors Q1 and Q2, and in this example, the base-emitter junction area of transistor Q2 is set to N times Q1, i.e. & lt & gt>。

Formula (1) can be simplified as: ………………………………（2）

the P-type field effect transistors MP4 and MP5 form a current mirror, so that the drain currents of the P-type field effect transistors MP4 and MP5 are in proportional relation:

………………………………………………（3）

the positive and negative input ends of the voltage follower circuit I0 are made of P-type field effect transistors, and the input and output currents are approximately zero, so that the current flowing through the resistor R2 is the current at the drain end of the P-type field effect transistor MP 5. The voltage at the positive input of the voltage follower circuit I0 is:

…………………………………………………（4）

the voltage is output by the voltage follower circuit I0, so that the driving load capacity of the voltage follower circuit is enhanced:

…………………………………………………（5）

wherein R1 and R2 are the same type of resistance and are strictly matched, the temperature coefficients of the R1 and R2 cancel each other,is a positive temperature coefficient voltage, so the output Vout of the final circuit is a positive temperature coefficient. The whole circuit is designed for micro power consumption, the temperature rise of consumed current generated by a chip is negligible, the influence of the circuit on the temperature test of the temperature sensing circuit is reduced, and the accuracy of the temperature test is improved.

While the preferred embodiment of the present utility model has been described in detail, the utility model is not limited to the embodiment, and one skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the utility model, and the equivalent modifications or substitutions are included in the scope of the present utility model as defined in the appended claims.

Claims (4)

1. A grid driving chip with a built-in positive temperature coefficient temperature sensing circuit is characterized in that: the circuit comprises a low-side circuit and a high-side circuit; the low-side circuit consists of a high-side signal input port HIN, a low-side signal input port LIN, a corresponding filter circuit, a positive temperature coefficient sensing circuit, a dead time control circuit, a pulse generation circuit, a low-voltage locking circuit, a delay circuit, output logic, a PMOS driving tube P2, an NMOS driving tube N2, output resistors XR3 and XR4 and an output port LO; the high-side circuit consists of a bootstrap diode, a level shift circuit, low-voltage locking, output logic, a PMOS driving tube P1, an NMOS driving tube N1, output resistors XR1 and XR2 and an output port HO; the high-side signal input port HIN and the low-side signal input port LIN are connected with the corresponding filter circuits and then connected with the dead time control circuit; the dead time control circuit is respectively connected with the pulse generating circuit and the low-voltage locking and delaying circuit in the low-side circuit; a low-voltage lock-in connection voltage VCC in the low-side circuit; the pulse generating circuit is connected with the level shifting circuit; the delay circuit is connected with the grid electrode of the PMOS driving tube P2 and the grid electrode of the NMOS driving tube N2 after being connected with output logic in the low-side circuit, the drain electrode of the PMOS driving tube P2 is connected with the output port LO after being connected with the output resistor XR3, and the source electrode of the PMOS driving tube P2 is connected with the voltage VCC; the drain electrode of the NMOS driving tube N2 is connected with the output port LO after being connected with the output resistor XR4, and the source electrode is connected with the voltage VSS; one end of the bootstrap diode is connected with voltage VCC, and the other end of the bootstrap diode is connected with voltage VB; one end of the low-voltage lock in the high-side circuit is connected with voltage VB, and the other end is connected with output logic in the high-side circuit; the level shift circuit is connected with output logic in the high-side circuit and then connected with the grid electrode of the PMOS driving tube P1 and the grid electrode of the NMOS driving tube N1, the drain electrode of the PMOS driving tube P1 is connected with the output resistor XR1 and then connected with an output port HO, and the source electrode of the PMOS driving tube P1 is connected with a voltage VB; the drain electrode of the NMOS driving tube N1 is connected with the output port HO after being connected with the output resistor XR2, and the source electrode is connected with the voltage VS.

2. The gate drive chip with built-in positive temperature coefficient temperature sensing circuit according to claim 1, wherein: the positive temperature coefficient sensing circuit comprises a starting circuit, a positive temperature coefficient voltage generating circuit and a voltage following circuit I0; the starting circuit comprises P-type field effect transistors MP1 and MP2, N-type field effect transistors MN1 and MN2 and a diode D1; the positive temperature coefficient voltage generating circuit comprises P-type field effect transistors MP3, MP4 and MP5, triodes Q1 and Q2 and resistors R1 and R2; the sources of the P-type field effect transistors MP1, MP2, MP3, MP4 and MP5 are connected with a voltage VDD; the grid electrode of the P-type field effect transistor MP1 and the source electrodes of the N-type field effect transistors MN1 and MN2 are grounded; the drain electrode of the N-type field effect transistor MN1 is connected with the drain electrode of the P-type field effect transistor MP1, and the grid electrode of the N-type field effect transistor MN2 is connected with the grid electrode; the grid electrode of the N-type field effect transistor MN2 is connected with the drain electrode, and the drain electrode is connected with the drain electrode of the P-type field effect transistor MP 2; the grid electrode of the P-type field effect tube MP2 is connected with the grid electrode of the P-type field effect tube MP3 and the grid electrode of the P-type field effect tube MP 4; the drain electrode of the P-type field effect transistor MP3 is connected with the collector electrode of the triode Q1; the base electrode of the triode Q1 is connected with the collector electrode, and the emitter electrode is grounded; the anode of the diode D1 is connected with the drain electrode of the P-type field effect transistor MP1, and the cathode is connected with the drain electrode of the P-type field effect transistor MP 3; the grid electrode of the P-type field effect transistor MP4 is connected with the drain electrode, and the drain electrode is connected with the collector electrode of the triode Q2; the base electrode of the triode Q2 is connected with the base electrode of the triode Q1, and the emitter is connected with the resistor R1 in series and then grounded; the grid electrode of the P-type field effect tube MP5 is connected with the drain electrode of the P-type field effect tube MP4, and the drain electrode is connected with the resistor R2 in series and then grounded; the positive input end of the voltage follower circuit I0 is connected with the drain electrode of the P-type field effect transistor MP5, and the negative input end is connected with the output end.

3. The gate drive chip with built-in positive temperature coefficient temperature sensing circuit according to claim 2, wherein: the positive and negative input ends of the voltage follower circuit I0 are made of P-type field effect transistors, and the input and output currents of the P-type field effect transistors are approximately zero.

4. The gate drive chip with built-in positive temperature coefficient temperature sensing circuit according to claim 2, wherein: the resistors R1 and R2 are of the same type and are strictly matched.