CN217404784U - Over-temperature protection circuit based on CMOS chip - Google Patents
Over-temperature protection circuit based on CMOS chip Download PDFInfo
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- CN217404784U CN217404784U CN202123215852.7U CN202123215852U CN217404784U CN 217404784 U CN217404784 U CN 217404784U CN 202123215852 U CN202123215852 U CN 202123215852U CN 217404784 U CN217404784 U CN 217404784U
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Abstract
The utility model discloses an excess temperature protection circuit based on CMOS chip contains: the starting circuit is connected with an external input signal Vref and an external VDD input end and is used for outputting starting current; the bias current generating circuit is connected with the starting circuit and is used for generating bias current; the temperature detection circuit is connected with the starting circuit, the bias current generation circuit and the VDD input end; and the voltage comparison circuit is connected with the temperature detection circuit, the bias current generation circuit and the VDD input end. The utility model has the advantages of low-power consumption, the precision is high, utilizes biasing circuit to sample the operating temperature of chip system, when comparing the threshold temperature that the circuit set for to sampling temperature voltage and system through the voltage, excess temperature protection circuit output low level and then turn-offs chip system, prevents because high temperature causes irreversible damage to the chip.
Description
Technical Field
The utility model relates to an excess temperature protection technical field of chip, in particular to excess temperature protection circuit based on CMOS chip.
Background
The over-temperature protection circuit is an important protection circuit in a CMOS chip. When the CMOS chip generates power consumption increase under the conditions of power supply short circuit, internal short circuit or heavy load and the like to cause the internal temperature of the chip to rise, the over-temperature protection circuit can detect the working temperature of the system and timely turn off the chip system, thereby preventing the transistors and other integrated modules in the chip from causing irreversible permanent failure due to high temperature. Therefore, the over-temperature protection circuit is widely applied to modules such as a bandgap reference voltage source, a low voltage drop circuit, an oscillator, and the like in a CMOS chip.
Disclosure of Invention
According to the embodiment of the utility model provides an excess temperature protection circuit based on CMOS chip contains:
the starting circuit is connected with an external input signal Vref and an external VDD input end and used for outputting starting current;
the bias current generating circuit is connected with the starting circuit and is used for generating bias current;
the temperature detection circuit is connected with the starting circuit, the bias current generation circuit and the VDD input end;
and the voltage comparison circuit is connected with the temperature detection circuit, the bias current generation circuit and the VDD input end.
Further, the start-up circuit includes: the circuit comprises a first operational amplifier, a first MOS (metal oxide semiconductor) tube, a first resistor and a first current mirror;
the same-direction input end of the first operational amplifier is connected with an input signal Vref, the output end of the first operational amplifier is connected with the grid electrode of the first MOS tube, the reverse input end of the first operational amplifier and the source electrode of the first MOS tube are grounded through a first resistor, the drain electrode of the first MOS tube is connected with a first current mirror, and the first current mirror is connected with the VDD input end, the bias current generating circuit and the temperature detection circuit.
Further, the first current mirror includes: a second MOS transistor and a third MOS transistor;
the grid electrodes of the second MOS tube and the third MOS tube are connected and then connected with the drain electrode of the second MOS tube, the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, the source electrode of the second MOS tube and the source electrode of the third MOS tube are connected with the VDD input end, and the drain electrode of the third MOS tube is connected with the bias current generating circuit and the temperature detection circuit.
Further, the bias current generating circuit includes: the first triode, the second triode and the second resistor;
the base electrode of the first triode is connected with the base electrode of the second triode and then connected with the collector electrode of the first triode, the collector electrode of the first triode is connected with the starting circuit and the temperature detection current, the emitting electrode of the first triode is grounded, the emitting electrode of the second triode is grounded through the second resistor, and the collector electrode of the second triode is connected with the temperature detection circuit.
Further, the temperature detection circuit includes: the second current mirror, the third resistor and the feedback control circuit;
the second current mirror is connected with the bias current generating circuit, the VDD input end, the voltage comparison circuit and one end of the third resistor;
the other end of the third resistor is connected with the feedback control circuit;
the feedback control circuit is connected with the starting circuit, the bias current generating circuit and the voltage comparison circuit.
Further, the second current mirror includes: a fourth MOS transistor and a fifth MOS transistor;
the grid electrode of the fourth MOS tube is connected with the grid electrode of the fifth MOS tube and is connected with the drain electrode of the fourth MOS tube and the voltage comparison circuit, the drain electrode of the fourth MOS tube is connected with the bias current generation circuit, the source electrodes of the fourth MOS tube and the fifth MOS tube are connected with the VDD input end, and the drain electrode of the fifth MOS tube is connected with one end of the third resistor.
Further, the feedback control circuit includes: a sixth MOS transistor and a seventh MOS transistor;
the source electrodes of the sixth MOS tube and the seventh MOS tube are grounded, the grid electrode of the sixth MOS tube is connected with the starting circuit and the bias current generating circuit, the drain electrodes of the sixth MOS tube and the seventh MOS tube are connected with the other end of the third resistor, and the grid electrode of the seventh MOS tube is connected with the voltage comparison circuit.
Further, the voltage comparison circuit includes: the second operational amplifier, the third triode, the capacitor, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube and the OTP output end;
the reverse input end of the second operational amplifier is connected with the temperature detection circuit, the direction input end of the second operational amplifier, the drain electrode of the ninth MOS tube and the collector electrode of the third triode are connected, the output end of the second operational amplifier, one end of the capacitor and the grid electrode of the eighth MOS tube are connected, the base electrode of the third triode and the emitter electrode of the third triode are connected and arranged in a grounding mode, the source electrode of the eighth MOS tube is grounded, the grid electrode of the ninth MOS tube is connected with the grid electrode of the tenth MOS tube and then connected with the temperature detection circuit and the bias current generation circuit, the source electrode of the ninth MOS tube and the source electrode of the tenth MOS tube are both connected with the VDD input end, and the OTP output end is connected with the temperature detection circuit, the other end of the capacitor, the drain electrode of the eighth MOS tube and the drain electrode of the tenth MOS tube.
According to the utility model discloses excess temperature protection circuit based on CMOS chip has designed a low-power consumption, excess temperature protection circuit of high accuracy, utilizes biasing circuit to sample the operating temperature of chip system, and when comparing the threshold temperature of circuit to sampling temperature voltage and system setting through the voltage, excess temperature protection circuit output low level and then turn-off chip system prevents because high temperature causes irreversible damage to the chip. When the sampling temperature is lower than the threshold temperature set by the system again, the over-temperature protection circuit outputs high level, and the chip system works normally again. And the over-temperature protection circuit is provided with a feedback control loop, and the generated hysteresis temperature can prevent the repeated turn-off of the chip system caused by the fluctuation of the working temperature.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the claimed technology.
Drawings
Fig. 1 is a circuit diagram of an over-temperature protection circuit based on a CMOS chip according to an embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the following detailed description of preferred embodiments thereof, which is to be read in connection with the accompanying drawings.
First, an over-temperature protection circuit based on a CMOS chip according to an embodiment of the present invention will be described with reference to fig. 1, for over-temperature protection of the chip, which has a wide application range.
As shown in fig. 1, the over-temperature protection circuit based on the CMOS chip according to the embodiment of the present invention includes a start circuit, a bias current generating circuit, a temperature detecting circuit, and a voltage comparing circuit.
Specifically, as shown in fig. 1, in this embodiment, the start circuit is connected to an external input signal Vref and an external VDD input terminal for outputting a start current, the bias current generating circuit is connected to the start circuit for generating a bias current, the temperature detecting circuit is connected to the start circuit, the bias current generating circuit and the VDD input terminal, the temperature detecting circuit is used for detecting a temperature detection voltage, the voltage comparing circuit is connected to the temperature detecting circuit, the bias current generating circuit and the VDD input terminal, and the voltage comparing circuit can compare the detected voltage with a system preset voltage to obtain a comparison result, and perform over-temperature protection according to the comparison result.
Further, as shown in fig. 1, in the present embodiment, the start-up circuit includes: the circuit comprises a first operational amplifier I0, a first MOS transistor M15, a first resistor R1 and a first current mirror. The same-direction input end of the first operational amplifier I0 is connected with an input signal Vref, the output end of the first operational amplifier I0 is connected with the gate of the first MOS tube M15, the reverse input end of the first operational amplifier I0 and the source of the first MOS tube M15 are grounded through a first resistor R1, the drain of the first MOS tube M15 is connected with a first current mirror, and the first current mirror is connected with the VDD input end, the bias current generating circuit and the temperature detecting circuit, wherein the first MOS tube M15 is a PMOS tube and is used for copying the starting current transmitted by the starting circuit to the bias current generating circuit.
Further, as shown in fig. 1, in the present embodiment, the first current mirror includes: a second MOS transistor M16 and a third MOS transistor M6. The gates of the second MOS transistor M16 and the third MOS transistor M6 are connected and then connected to the drain of the second MOS transistor M16, the drain of the second MOS transistor M16 is connected to the drain of the first MOS transistor M15, the source of the second MOS transistor M16 and the source of the third MOS transistor M6 are both connected to the VDD input terminal, and the drain of the third MOS transistor M6 is connected to the bias current generating circuit and the temperature detecting circuit, wherein the second MOS transistor M16 and the third MOS transistor M6 are NMOS transistors, and the second MOS transistor M16 and the third MOS transistor M6 interact with each other to copy the electromotive current to the bias current generating circuit.
Further, as shown in fig. 1, in the present embodiment, the bias current generating circuit includes: the circuit comprises a first triode Q0, a second triode Q1 and a second resistor R3. The base electrode of the first triode Q0 is connected with the base electrode of the second triode Q1 and then connected with the collector electrode of the first triode Q0, the collector electrode of the first triode Q0 is connected with the starting circuit and the temperature detection current, the emitter electrode of the first triode Q0 is grounded, the emitter electrode of the second triode Q1 is grounded through the second resistor R3, and the collector electrode of the second triode Q1 is connected with the temperature detection circuit.
Further, as shown in fig. 1, in the present embodiment, the temperature detection circuit includes: a second current mirror, a third resistor R2, and a feedback control circuit. The second current mirror is connected with the bias current generating circuit, the VDD input end, the voltage comparison circuit and one end of a third resistor R2, the other end of the third resistor R2 is connected with the feedback control circuit, and the feedback control circuit is connected with the starting circuit, the bias current generating circuit and the voltage comparison circuit.
Further, as shown in fig. 1, in the present embodiment, the second current mirror includes: a fourth MOS transistor M7 and a fifth MOS transistor M8. The grid of the fourth MOS transistor M7 is connected to the grid of the fifth MOS transistor M8, the drain of the fourth MOS transistor M7 and the voltage comparison circuit, the drain of the fourth MOS transistor M7 is connected to the bias current generation circuit, the sources of the fourth MOS transistor M7 and the fifth MOS transistor M8 are both connected to the VDD input terminal, the drain of the fifth MOS transistor M8 is connected to one end of the third resistor R2, and the fourth MOS transistor M7 and the fifth MOS transistor M8 are NMOS transistors.
Further, as shown in fig. 1, in the present embodiment, the feedback control circuit includes: a sixth MOS transistor 17 and a seventh MOS transistor 18. The source electrodes of the sixth MOS transistor 17 and the seventh MOS transistor 18 are both grounded, the gate electrode of the sixth MOS transistor 17 is connected to the start circuit and the bias current generating circuit, the drain electrodes of the sixth MOS transistor 17 and the seventh MOS transistor 18 are connected to the other end of the third resistor R2, the gate electrode of the seventh MOS transistor 18 is connected to the voltage comparing circuit, and the sixth MOS transistor 17 and the seventh MOS transistor 18 are PMOS transistors.
Further, as shown in fig. 1, in the present embodiment, the voltage comparison circuit includes: the circuit comprises a second operational amplifier I1, a third triode Q2, a capacitor C1, an eighth MOS tube M3, a ninth MOS tube M9, a tenth MOS tube M13 and an OTP output end. The same-direction input end of a second operational amplifier I1 is connected with a temperature detection circuit, the reverse input end of a second operational amplifier I1, the drain electrode of a ninth MOS tube M9 and the collector electrode of a third triode Q2 are connected, the output end of the second operational amplifier I1, one end of a capacitor C1 and the gate electrode of an eighth MOS tube M3 are connected, the base electrode of the third triode Q2 and the emitter electrode of the third triode Q2 are connected and grounded, the source electrode of the eighth MOS tube M3 is grounded, the gate electrode of the ninth MOS tube M9 and the gate electrode of the tenth MOS tube M13 are connected and then connected with the temperature detection circuit and a bias current generation circuit, the source electrode of the ninth MOS tube M9 and the source electrode of the tenth MOS tube M13 are both connected with a VDD input end, and the OTP output end is connected with the temperature detection circuit, the other end of the capacitor C1, the drain electrode of the eighth MOS tube M3 and the drain electrode of the tenth MOS tube M13.
When the over-temperature protection circuit is used, the over-temperature protection circuit is connected with an external chip system, the starting current provided by the chip system is a design value, the over-temperature protection circuit is normally started, at normal temperature, when the preset voltage of the chip system is greater than the temperature detection voltage, the OTP output end of the voltage comparison circuit is at a high level, the system normally works, if the working temperature of the system is higher than the preset temperature, the preset voltage of the chip system is less than the temperature detection voltage, the OTP output end of the voltage comparison circuit is at a low level, the chip system stops working, and other modules of a chip are prevented from being damaged due to high temperature. And when the working temperature of the chip system is reduced from high to low, the electrical level of the OTP output end of the voltage comparison circuit is low and then high, and at this time, the seventh MOS transistor 18 is turned off.
Above, having described according to the utility model discloses an according to the overtemperature protection circuit based on CMOS chip with reference to fig. 1, having designed a low-power consumption, the overtemperature protection circuit of high accuracy, utilize the biasing circuit to sample the operating temperature of chip system, when comparing the threshold temperature that the circuit set for to sampling temperature voltage and system through the voltage, the overtemperature protection circuit outputs the low level and then shuts off chip system, prevents to cause irreversible damage to the chip because high temperature. When the sampling temperature is lower than the threshold temperature set by the system again, the over-temperature protection circuit outputs high level, and the chip system works normally again. And the over-temperature protection circuit is provided with a feedback control loop, and the generated hysteresis temperature can prevent the repeated turn-off of the chip system caused by the fluctuation of the working temperature.
It should be noted that, in the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described in detail with reference to the preferred embodiments thereof, it should be understood that the above description should not be taken as limiting the present invention. Numerous modifications and alterations to the present invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (8)
1. An over-temperature protection circuit based on a CMOS chip is characterized by comprising:
the starting circuit is connected with an external input signal Vref and an external VDD input end;
the bias current generating circuit is connected with the starting circuit and is used for generating bias current;
the temperature detection circuit is connected with the starting circuit, the bias current generation circuit and the VDD input end;
and the voltage comparison circuit is connected with the temperature detection circuit, the bias current generation circuit and the VDD input end.
2. The CMOS chip-based over-temperature protection circuit of claim 1, wherein the start-up circuit comprises: the circuit comprises a first operational amplifier, a first MOS (metal oxide semiconductor) tube, a first resistor and a first current mirror;
the same-direction input end of the first operational amplifier is connected with an input signal Vref, the output end of the first operational amplifier is connected with the grid electrode of the first MOS tube, the reverse input end of the first operational amplifier and the source electrode of the first MOS tube are grounded through the first resistor, the drain electrode of the first MOS tube is connected with the first current mirror, and the first current mirror is connected with the VDD input end, the bias current generating circuit and the temperature detecting circuit.
3. The CMOS chip-based over-temperature protection circuit of claim 2, wherein the first current mirror comprises: a second MOS transistor and a third MOS transistor;
the grid electrode of the second MOS tube is connected with the grid electrode of the third MOS tube and then is connected with the drain electrode of the second MOS tube, the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, the source electrode of the second MOS tube and the source electrode of the third MOS tube are both connected with the VDD input end, and the drain electrode of the third MOS tube is connected with the bias current generating circuit and the temperature detecting circuit.
4. The CMOS chip-based over-temperature protection circuit of claim 1, wherein the bias current generating circuit comprises: the first triode, the second triode and the second resistor;
the base electrode of the first triode is connected with the base electrode of the second triode and then is connected with the collector electrode of the first triode, the collector electrode of the first triode is connected with the starting circuit and the temperature detection current, the emitting electrode of the first triode is grounded, the emitting electrode of the second triode is grounded through the second resistor, and the collector electrode of the second triode is connected with the temperature detection circuit.
5. The CMOS chip-based over-temperature protection circuit of claim 1, wherein the temperature detection circuit comprises: the second current mirror, the third resistor and the feedback control circuit;
the second current mirror is connected with the bias current generating circuit, a VDD input end, the voltage comparison circuit and one end of the third resistor;
the other end of the third resistor is connected with the feedback control circuit;
the feedback control circuit is connected with the starting circuit, the bias current generating circuit and the voltage comparison circuit.
6. The CMOS chip based over-temperature protection circuit of claim 5, wherein the second current mirror comprises: a fourth MOS transistor and a fifth MOS transistor;
the grid electrode of the fourth MOS tube is connected with the grid electrode of the fifth MOS tube, the drain electrode of the fourth MOS tube is connected with the voltage comparison circuit, the drain electrode of the fourth MOS tube is connected with the bias current generation circuit, the source electrodes of the fourth MOS tube and the fifth MOS tube are connected with the VDD input end, and the drain electrode of the fifth MOS tube is connected with one end of the third resistor.
7. The CMOS chip-based over-temperature protection circuit of claim 6, wherein the feedback control circuit comprises: a sixth MOS transistor and a seventh MOS transistor;
the source electrodes of the sixth MOS tube and the seventh MOS tube are grounded, the grid electrode of the sixth MOS tube is connected with the starting circuit and the bias current generating circuit, the drain electrodes of the sixth MOS tube and the seventh MOS tube are connected with the other end of the third resistor, and the grid electrode of the seventh MOS tube is connected with the voltage comparison circuit.
8. The CMOS chip-based over-temperature protection circuit of claim 1, wherein the voltage comparison circuit comprises: the second operational amplifier, the third triode, the capacitor, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube and the OTP output end;
the same-direction input end of the second operational amplifier is connected with the temperature detection circuit, the reverse-direction input end of the second operational amplifier, the drain electrode of the ninth MOS tube and the collector electrode of the third triode are connected, the output end of the second operational amplifier, one end of the capacitor and the grid electrode of the eighth MOS tube are connected, the base electrode of the third triode and the emitter electrode of the third triode are connected and grounded, the source electrode of the eighth MOS tube is grounded, after the grid electrode of the ninth MOS tube is connected with the grid electrode of the tenth MOS tube, the grid electrode of the ninth MOS tube is connected with the temperature detection circuit and the bias current generation current, the source electrode of the ninth MOS tube and the source electrode of the tenth MOS tube are both connected with the VDD input end, the OTP output end is connected with the temperature detection circuit, the other end of the capacitor, the drain electrode of the eighth MOS tube and the drain electrode of the tenth MOS tube.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202123215852.7U CN217404784U (en) | 2021-12-21 | 2021-12-21 | Over-temperature protection circuit based on CMOS chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202123215852.7U CN217404784U (en) | 2021-12-21 | 2021-12-21 | Over-temperature protection circuit based on CMOS chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230108765A1 (en) * | 2021-10-01 | 2023-04-06 | Nxp B.V. | Self-Turn-On Temperature Detector Circuit |
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2021
- 2021-12-21 CN CN202123215852.7U patent/CN217404784U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230108765A1 (en) * | 2021-10-01 | 2023-04-06 | Nxp B.V. | Self-Turn-On Temperature Detector Circuit |
| US11867571B2 (en) * | 2021-10-01 | 2024-01-09 | Nxp B.V. | Self-turn-on temperature detector circuit |
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