CN220065697U - Transient suppression diode chip - Google Patents
Transient suppression diode chip Download PDFInfo
- Publication number
- CN220065697U CN220065697U CN202321283736.5U CN202321283736U CN220065697U CN 220065697 U CN220065697 U CN 220065697U CN 202321283736 U CN202321283736 U CN 202321283736U CN 220065697 U CN220065697 U CN 220065697U
- Authority
- CN
- China
- Prior art keywords
- type
- region
- heavily doped
- type heavily
- doped region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001629 suppression Effects 0.000 title claims abstract description 19
- 230000001052 transient effect Effects 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 230000005669 field effect Effects 0.000 claims abstract description 13
- 230000002093 peripheral effect Effects 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000010521 absorption reaction Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses a transient suppression diode chip, which is formed with a new device structure, wherein PN junction strings are connected in parallel between a grid electrode and a drain electrode, the new device structure comprises an N-type heavily doped silicon substrate and an N-type lightly doped epitaxial layer formed on the surface of the N-type heavily doped silicon substrate, two P-type heavily doped regions are arranged in the N-type lightly doped epitaxial layer of a MOS cell region at intervals left and right, each P-type heavily doped region is internally provided with an N-type heavily doped region, and an N-type heavily doped region is arranged in the N-type lightly doped epitaxial layer of a peripheral connection region of the chip; the junction capacitance of the device is reduced in a capacitance series connection mode, and the energy discharge capacity of the device is obviously enhanced through the channel of the metal-oxide-semiconductor field effect transistor, so that the double-best capacity of low capacitance and high surge absorption capacity is realized on the same chip.
Description
Technical Field
The utility model relates to a diode chip, in particular to a transient suppression diode chip, and belongs to the technical field of semiconductor devices.
Background
A transient voltage suppression diode (TVS) is also called a TVS diode, and is an electronic component for protection, which can protect electrical equipment from voltage spikes induced by wires. For the protection of high frequency circuits, low or ultra-low capacitance is required to reduce the interference of parasitic capacitance to the circuit and reduce the attenuation of the high frequency circuit signal. In the conventional engineering field, a method for reducing junction capacitance is to reduce the area of a PN junction or adopt a mode of connecting small resistors in series. When the PN junction area is reduced, the absorption capacity of the diode to surge current is reduced; and when connected in series with a small capacitor, the cost is significantly increased in addition to increasing the circuit board area.
In conventional device designs, engineering personnel often introduce transistors into the device structure in order to enhance the surge relief capability of the TVS diode. As shown in fig. 3-4 together, after the latch-up benefit is started, the device exhibits negative resistance characteristics by using NPN type transistor and PNP type transistor, thereby improving surge discharging capability of TVS diode, but the structure cannot realize low capacitance absorption capability.
Disclosure of Invention
In order to solve the defects of the technology, the utility model provides a transient suppression diode chip.
In order to solve the technical problems, the utility model adopts the following technical scheme: the new device structure is that PN junction group strings are connected in parallel between the grid electrode and the drain electrode of the metal-oxide-semiconductor field effect transistor, the grid electrode is positioned in a MOS cell area, the drain electrode is positioned in a peripheral connection area of the chip, and PN junction group strings are formed into PN junction group string areas;
the new device structure comprises an N-type heavily doped silicon substrate and an N-type lightly doped epitaxial layer formed on the surface of the N-type heavily doped silicon substrate;
two P-type heavily doped regions are arranged in the N-type lightly doped epitaxial layer of the MOS cell region at left and right intervals, and each P-type heavily doped region is internally provided with an N-type heavily doped region;
an N-type heavily doped region is arranged in the N-type lightly doped epitaxial layer positioned in the peripheral connection region of the chip.
Further, a gate oxide layer is formed on the surface of the N-type lightly doped epitaxial layer of the MOS cell region, and the gate oxide layer is located between the N-type heavily doped regions at the left and right positions and spans across a single end of the P-type heavily doped regions close to each other.
Further, a gate polysilicon layer is formed on the surface of the gate oxide layer, and the gate polysilicon layer is an N-type doped region.
Further, a field oxide layer is formed on the N-type lightly doped epitaxial layer of the peripheral connection region of the chip, and the field oxide layer is arranged avoiding the N-type heavily doped region.
Further, a field oxide layer is formed on the N-type lightly doped epitaxial layer of the PN junction string region, an N-type doped region and a P-type doped region of the grid polycrystalline silicon layer are formed on the surface of the field oxide layer, and the N-type doped region and the P-type doped region are alternately arranged from left to right in sequence and are provided with N-type doped regions at two ends.
Further, the grid electrode and the PN junction group string are connected through the polycrystalline silicon film formed by the N-type doped region and the N-type heavily doped region of the grid electrode polycrystalline silicon layer.
Further, the drain electrode is connected with the N-type doped region at the other end of the PN junction string through the N-type heavily doped region.
Further, the MOS cell region, the PN junction string region and the chip peripheral connection region are sequentially arranged from left to right, and channels are formed among the three.
The utility model discloses a transient suppression diode chip, which is characterized in that a device with a voltage transient suppression function is actually formed between a source electrode and a drain electrode of a metal-oxide-semiconductor field effect tube, the junction capacitance of the device is obviously reduced in a capacitor series connection mode, and meanwhile, the energy release capacity of the device is obviously enhanced through a channel of the metal-oxide-semiconductor field effect tube, so that the double excellent capacities of low capacitance and high surge absorption capacity are realized on the same chip, and besides, the compatibility of the innovative novel device structure and the metal-oxide-semiconductor field effect tube is strong, and the tolerance of cost control is high.
Drawings
Fig. 1 is an equivalent circuit diagram of a new device structure of the present utility model.
Fig. 2 is a schematic diagram of the overall construction of the novel device structure of the present utility model.
Fig. 3 is a schematic diagram of a TVS diode with negative resistance characteristics in the prior art.
Fig. 4 is an equivalent circuit diagram of a TVS diode structure with negative resistance characteristics in the prior art.
In the figure: 101. an N-type heavily doped silicon substrate; 102. an N-type lightly doped epitaxial layer; 103. a P-type heavily doped region; 104. an N-type heavily doped region; 105. a gate oxide layer; 106. a gate polysilicon layer; 201. a field oxide layer; 202. a P-type doped region;
n-sub, namely an N-type heavily doped silicon substrate;
N-EPI, an N-type lightly doped epitaxial layer;
drain, drain;
source, i.e., source;
gate, i.e., gate;
n+, i.e., an N-type more heavily doped region;
p+, i.e., a P-type more heavily doped region;
PWELL, P-type doped region;
zn+, i.e., some other N-type more heavily doped region that is distinct from n+;
zp+, i.e., some other P-type more heavily doped region that is distinct from p+.
Detailed Description
The utility model will be described in further detail with reference to the drawings and the detailed description.
Referring to fig. 1-2 together, the present embodiment relates to a transient suppression diode chip, which is formed with a new device structure, wherein a PN junction string is connected in parallel between a gate and a drain of a metal-oxide-semiconductor field effect transistor, the gate is located in a MOS cell region, the drain is located in a peripheral connection region of the chip, and the PN junction string is formed with a PN junction string region, which is not explained, of the metal-oxide-semiconductor field effect transistor, i.e., a MOSFET;
preferably, the MOS cell region, the PN junction string region and the chip peripheral connection region are sequentially arranged from left to right, and channels are formed among the three, so that the energy discharge capacity of the metal-oxide-semiconductor field effect transistor is remarkably improved.
The conventional method of forming PN junctions by using a silicon substrate (including an epitaxial layer) is omitted, PN junctions are formed on a polycrystalline silicon film, the number of the PN junctions and the area of a single PN junction can be adjusted through the change of a photomask, the method is flexible to change, the compatibility is high, the applicability is strong, and besides, the breakdown voltage and the characteristics of the PN junctions can be controlled by controlling the doping concentration and doping elements of different areas.
In this embodiment, the new device structure includes an N-type heavily doped silicon substrate and an N-type lightly doped epitaxial layer formed on the surface of the N-type heavily doped silicon substrate; two P-type heavily doped regions are arranged in the N-type lightly doped epitaxial layer of the MOS cell region at left and right intervals, and each P-type heavily doped region is internally provided with an N-type heavily doped region; and an N-type heavily doped region is arranged in the N-type lightly doped epitaxial layer positioned in the peripheral connection region of the chip.
Preferably, a gate oxide layer is formed on the surface of the N-type lightly doped epitaxial layer of the MOS cell region, and the gate oxide layer is located between the N-type heavily doped regions at the left and right positions and spans across a single end of the P-type heavily doped regions close to each other.
Further, a gate polysilicon layer is formed on the surface of the gate oxide layer, and the gate polysilicon layer is an N-type doped region.
As shown in fig. 2, a field oxide layer is formed on the N-type lightly doped epitaxial layer in the peripheral connection region of the chip, and the field oxide layer is disposed away from the N-type heavily doped region.
In this embodiment, a field oxide layer is formed on the N-type lightly doped epitaxial layer of the PN junction string region, an N-type doped region and a P-type doped region of the gate polysilicon layer are formed on the surface of the field oxide layer, and the N-type doped region and the P-type doped region are alternately arranged from left to right in sequence and are N-type doped regions at both ends.
Preferably, the gate and the PN junction string are connected through a polysilicon thin film formed by combining an N-type doped region of the gate polysilicon layer with an N-type heavily doped region, and the drain is connected through an N-type heavily doped region thereof communicating with an N-type doped region at the other end of the PN junction string, or can be connected through a metal layer and a contact hole, as shown in fig. 1, both the two modes are for adjusting the rgs between the PN junction and the source directly, and further adjusting the proportional relationship between rgs and rgd, and it is to be explained that rgs, namely the resistance between the gate and the source, and rgd, namely the resistance between the gate and the drain.
In this embodiment, the breakdown voltage BVdss between the drain and the source of the new device structure is greater than the breakdown voltage of the PN junction string, which varies positively with the number of PN junctions applied to the new device structure, and the electrical parameter capability.
It should be noted that, the dielectric layer, the contact hole, the front metal layer and the back metal layer required in the new device structure belong to the prior art, and are not technical contents to be protected in the utility model, so the above structures and components are not shown in the drawings, and detailed descriptions thereof are omitted;
the metal-oxide-semiconductor field effect transistor mentioned above not only refers to an N-type, but also can realize the effect of the utility model by doping the P-type in opposite directions as a whole, and the novel device structure is also applicable to not only the planar structure shown in fig. 2, but also the trench structure.
Therefore, the utility model discloses a transient suppression diode chip, a device with a voltage transient suppression function is actually formed between the source electrode and the drain electrode of a metal-oxide-semiconductor field effect tube, the junction capacitance of the device is obviously reduced in a capacitor series connection mode, and meanwhile, the energy release capacity of the device is obviously enhanced through the channel of the metal-oxide-semiconductor field effect tube, so that the double excellent capacities of low capacitance and high surge absorption capacity are realized on the same chip, and besides, the compatibility of the innovative novel device structure and the metal-oxide-semiconductor field effect tube is strong, and the latitude of cost control is high.
The above embodiments are not intended to limit the present utility model, and the present utility model is not limited to the above examples, but is also intended to be limited to the following claims.
Claims (8)
1. A transient suppression diode chip formed with a new device structure, characterized by: the novel device structure is that PN junction group strings are connected in parallel between a grid electrode and a drain electrode of a metal-oxide-semiconductor field effect transistor, the grid electrode is positioned in a MOS cell area, the drain electrode is positioned in a peripheral connection area of a chip, and PN junction group strings are formed into PN junction group string areas;
the new device structure comprises an N-type heavily doped silicon substrate and an N-type lightly doped epitaxial layer formed on the surface of the N-type heavily doped silicon substrate;
two P-type heavily doped regions are arranged in the N-type lightly doped epitaxial layer of the MOS cell region at left and right intervals, and each P-type heavily doped region is internally provided with an N-type heavily doped region;
and an N-type heavily doped region is arranged in the N-type lightly doped epitaxial layer positioned in the peripheral connection region of the chip.
2. The transient suppression diode chip of claim 1, wherein: and a gate oxide layer is formed on the surface of the N-type lightly doped epitaxial layer of the MOS cell region, and the gate oxide layer is positioned between the left N-type heavily doped region and the right N-type heavily doped region and is bridged on a single end of the two P-type heavily doped regions, which are close to each other.
3. The transient suppression diode chip of claim 2, wherein: and a gate polysilicon layer is formed on the surface of the gate oxide layer, and the gate polysilicon layer is an N-type doped region.
4. The transient suppression diode chip of claim 1, wherein: and a field oxide layer is formed on the N-type lightly doped epitaxial layer of the peripheral connection region of the chip, and the field oxide layer is arranged avoiding the N-type heavily doped region.
5. The transient suppression diode chip of claim 1, wherein: the N-type lightly doped epitaxial layer of the PN junction string region is provided with a field oxide layer, the surface of the field oxide layer is provided with N-type doped regions and P-type doped regions of a grid polycrystalline silicon layer, and the N-type doped regions and the P-type doped regions are alternately arranged from left to right in sequence and are provided with N-type doped regions at two ends.
6. The transient suppression diode chip of claim 5, wherein: the grid electrode and the PN junction group string are connected through a polycrystalline silicon film formed by combining an N-type doped region and an N-type heavily doped region of the grid electrode polycrystalline silicon layer.
7. The transient suppression diode chip of claim 5, wherein: the drain electrode is connected with the N-type doped region at the other end of the PN junction group string through the N-type heavily doped region.
8. The transient suppression diode chip of claim 1, wherein: the MOS cell region, the PN junction string region and the chip peripheral connection region are sequentially arranged from left to right, and channels are formed among the three.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321283736.5U CN220065697U (en) | 2023-05-25 | 2023-05-25 | Transient suppression diode chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321283736.5U CN220065697U (en) | 2023-05-25 | 2023-05-25 | Transient suppression diode chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220065697U true CN220065697U (en) | 2023-11-21 |
Family
ID=88751784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321283736.5U Active CN220065697U (en) | 2023-05-25 | 2023-05-25 | Transient suppression diode chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220065697U (en) |
-
2023
- 2023-05-25 CN CN202321283736.5U patent/CN220065697U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101517727B (en) | Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch | |
| JP3191747B2 (en) | MOS type semiconductor device | |
| US20140332846A1 (en) | Transistor-type protection device, semiconductor integrated circuit, and manufacturing method of the same | |
| EP1879229A1 (en) | Improved ESD protection circuit | |
| US6570229B1 (en) | Semiconductor device | |
| US5903032A (en) | Power device integration for built-in ESD robustness | |
| CN102969312A (en) | High-voltage ESD (electro-static discharge) protective device triggered by bidirectional substrate | |
| CN112151620B (en) | Junction field effect transistor with ESD protection structure | |
| CN102790048B (en) | Semiconductor structure of bipolar junction transistor embedded with Schottky diode | |
| CN110459539A (en) | The shield grid groove MOSFET and manufacturing method of integrated ESD protection | |
| US11227949B2 (en) | Power semiconductor devices with low specific on-resistance | |
| CN203071072U (en) | High-voltage ESD (electro-static discharge) protective device triggered by bidirectional substrate | |
| CN110739303B (en) | Trench VDMOS device integrated with ESD protection and manufacturing method | |
| CN103715233A (en) | ESD protection component of LDMOS structure and with high maintaining voltage | |
| CN220065697U (en) | Transient suppression diode chip | |
| CN101714553B (en) | Unit transistor, integrated circuit and display system | |
| CN116435303A (en) | Transient suppression diode chip | |
| CN211017088U (en) | ESD integrated VDMOS device | |
| CN203659868U (en) | High-maintenance-voltage ESD protection device of LDMOS structure | |
| KR100936644B1 (en) | Semiconductor device and method for manufacturing thereof | |
| CN111129002B (en) | Electrostatic protection circuit | |
| CN108565259B (en) | Semiconductor device and method for manufacturing the same | |
| KR101407273B1 (en) | Semiconductor Device for Surge Protection and Method for Manufacturing Thereof | |
| CN111403382A (en) | Bidirectional silicon controlled rectifier and preparation method thereof | |
| Vogt et al. | Smart power with 1200 V DMOS |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |