CN220040613U - Testing device of PD equipment - Google Patents

Abstract

The utility model discloses a testing device of PD equipment, comprising: the system comprises a network port, a network transformer, a rectifying unit, a first switch, a PD protocol unit, a load adjustable unit, a detecting unit, a first grading unit, a second grading unit, a driving unit, a voltage control unit, a processing unit and a display unit; according to the technical scheme provided by the embodiment, the load is simulated by the load adjustable unit, the power of the load of the PD equipment is dynamically adjusted, and the function measurement of the PD equipment is realized; three standards are supported, and the processing unit measures voltage and current in real time and calculates power; the display unit displays the voltage and the current measured by the processing unit and the calculated power in real time; the method can realize detection of a plurality of ports of the PD equipment, has high test speed in production test, high test integration level and high test result visualization degree, saves a great amount of time, and ensures that the whole test process is more efficient.

Description

Testing device of PD equipment

Technical Field

The utility model relates to the technical field of equipment power supply test, in particular to a test device of PD equipment.

Background

A complete POE system in the prior art includes two parts, a power sourcing equipment (PSE, power Sourcing Equipment) and a Powered equipment (PD). The PD powered end equipment is connected with the PSE switch through a network cable, and power is supplied to the equipment through PSE of the switch. The POE power supply technology is to supply power through the network transmission cable while transmitting network signals, and a special power supply line is omitted through POE power supply, so that the use is more convenient. Meanwhile, the POE power supply circuit is lower in voltage, and compared with the traditional AC and DC power supply modes, the low-voltage power supply mode is safer. The PD load tester that does not sell on the market at present has the following problem: in terms of power and classification, most of the testers developed by various factories only support 802.3af (PoE) and 802.3at (poe+) protocols, namely maximum PSE30W output, in terms of detection content and detection result: at present, only power detection is achieved, current and voltage detection and grading detection are not achieved, and the problems that test results are not output directly, mass production is inconvenient, intelligent recording is achieved and the like are solved.

Disclosure of Invention

The embodiment of the utility model provides a testing device of PD equipment, which aims to solve the problems that the supporting protocol is less, current and voltage detection cannot be carried out and output is not visual in the prior art.

A first aspect of an embodiment of the present utility model provides a testing apparatus for a PD device, including: the system comprises a network port, a network transformer, a rectifying unit, a first switch, a PD protocol unit, a load adjustable unit, a detecting unit, a first grading unit, a second grading unit, a driving unit, a voltage control unit, a processing unit and a display unit;

the input end of the network transformer is connected with the network port, the output end of the network transformer is connected with the input end of the rectifying unit, the output end of the rectifying unit is respectively connected with the first end of the first switch and the input end of the detecting unit, the second end of the first switch is connected with the input end of the PD protocol unit and one end of the load adjustable unit, the output end of the PD protocol unit is connected with the other end of the load adjustable unit, the first grading end of the PD protocol unit is connected with the input end of the first grading unit, the second grading end of the PD protocol unit is connected with the input end of the second grading unit, the two ends of the load adjustable unit are connected with the two ends of the voltage control unit, the driving unit is respectively connected with the control end of the first switch, the control end of the first grading unit, the control end of the load adjustable unit and the control end of the load adjustable unit, the output end of the detecting unit is connected with the input end of the processing unit, and the processing unit, the voltage control unit and the driving unit are connected with the display unit.

Preferably, the PD protocol unit is a chip TPS2373-4, the CLSA pin of the chip TPS2373-4 is a first grading terminal, and the CLSB pin of the chip TPS2373-4 is a second grading terminal.

Preferably, the first grading unit includes a switch K2, a switch K3, a resistor R2, and a resistor R3, where a first end of the switch K2 is commonly connected with a first end of the switch K3 and is connected to a CLSA pin of the chip TPS2373-4, a second end of the switch K2 is connected to the first end of the resistor R2, a second end of the switch K3 is connected to the first end of the resistor R3, and a second end of the resistor R2 is commonly connected with a second end of the resistor R3 and is connected to a VSS pin of the chip TPS 2373-4.

Preferably, the second classification unit includes a switch K4, a switch K5, a resistor R4, and a resistor R5, where a first end of the switch K4 is commonly connected with a first end of the switch K5 and is connected to a CLSB pin of the chip TPS2373-4, a second end of the switch K4 is connected to the first end of the resistor R4, a second end of the switch K5 is connected to the first end of the resistor R5, and a second end of the resistor R4 is commonly connected with a second end of the resistor R5 and is connected to a VSS pin of the chip TPS 2373-4.

Preferably, the voltage control unit comprises an isolation module, a digital-to-analog converter and a voltage output unit which are sequentially connected, wherein the input end of the isolation module is connected with the processing unit, and the output end of the voltage output unit is connected with the two ends of the load adjustable unit.

Preferably, the voltage output unit includes a resistor R6, a resistor R7, a resistor R8, a resistor Rs, a capacitor C1, an operational amplifier U1 and a MOS transistor Q1, where a first end of the resistor R6 is an input end of the voltage output unit, a second end of the resistor R6 is connected to a non-inverting input end of the operational amplifier U1, an output end of the operational amplifier U1 is connected to the first end of the capacitor C1 and the first end of the resistor R7, a second end of the resistor R7 is connected to a gate of the MOS transistor, a drain of the MOS transistor is the first output end of the voltage output unit, a source of the MOS transistor is connected to the second end of the resistor R8 and the first end of the resistor Rs, a first end of the resistor R8 is connected to the second end of the capacitor C1 and an inverting input end of the operational amplifier U1, and a second end of the resistor Rs is the second output end of the voltage output unit.

Preferably, the driving unit includes a first driving unit and a second driving unit, an input end of the first driving unit is connected with an output end of the processing unit, an output end of the first driving unit is connected with a control end of the first grading unit and a control end of the second grading unit, an input end of the second driving unit is connected with an output end of the processing unit, and an output end of the second driving unit is connected with a control end of the first switch and a control end of the load adjustable unit.

Preferably, the first driving unit and the second driving unit are chips MAX4280.

Preferably, the detection unit comprises a plurality of chips LMA5056.

Preferably, the load adjustable unit comprises a switch K6, a switch K7, a switch K8, a resistor R11, a resistor R12 and a resistor R13, wherein a first end of the switch K6 is connected with a first end of the switch K7 and a first end of the switch K8, a second end of the switch K6 is connected with a first end of the resistor R11, a second end of the switch K7 is connected with a first end of the resistor R12, a second end of the switch K8 is connected with a first end of the resistor R13, and a second end of the resistor R11, a second end of the resistor R12 and a second end of the resistor R13 are connected together to form a second end of the load adjustable unit.

The technical effects of the embodiment of the utility model are as follows: according to the technical scheme provided by the embodiment, the load is simulated by the load adjustable unit, the power of the load of the PD equipment is dynamically adjusted, and the function measurement of the PD equipment is realized; three standards of 802.3af (PoE), 802.3at (PoE+), 802.3bt (PoE++) are supported, and the processing unit measures voltage and current and calculates power in real time; the display unit displays the voltage and the current measured by the processing unit and the calculated power in real time; the detection of a plurality of ports of the PD equipment can be realized, a large amount of time is saved, the whole testing process is more efficient, and the use of a large number of different power equipment is avoided; the multi-port test device solves the problems that in the prior art, equipment with different powers needs to be replaced continuously, the test process is complex, the efficiency is low, the test parameters cannot be displayed in real time, and the like; the test speed is high in production test, the test integration level is high, the visualization degree of the test result is high, and the test data is convenient to reserve; the production level can be improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments of the present utility model will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a testing device of a PD device according to an embodiment of the present utility model;

fig. 2 is a block diagram of a testing apparatus of a PD device provided in an embodiment of the present utility model;

fig. 3 is a schematic connection diagram of a PD protocol unit in a test apparatus of a PD device according to an embodiment of the present utility model, with a first classification unit and a second classification unit;

fig. 4 is an eight-level classification table in a test apparatus of a PD device according to an embodiment of the present utility model;

fig. 5 is a three-level classification table in a test device of a PD device according to an embodiment of the present utility model;

fig. 6 is a schematic structural diagram of a voltage control unit in a testing apparatus of a PD device according to an embodiment of the present utility model;

fig. 7 is another schematic structural diagram of a voltage control unit in a testing apparatus of a PD device according to an embodiment of the present utility model;

fig. 8 is a circuit diagram of a voltage output unit in a test apparatus of a PD device according to an embodiment of the present utility model;

fig. 9 is a schematic structural diagram of a driving unit in a testing apparatus of a PD device according to an embodiment of the present utility model;

fig. 10 is a circuit diagram of a driving unit in a test apparatus of a PD device provided in an embodiment of the present utility model;

fig. 11 is a circuit diagram of a load adjustable unit in a test apparatus of a PD device according to an embodiment of the present utility model;

fig. 12 is a circuit diagram of a detection unit in a test apparatus of a PD device according to an embodiment of the present utility model;

fig. 13 is a schematic diagram of a part of a structure in a testing apparatus of a PD device according to an embodiment of the present utility model;

in the figure: 101. a net opening; 102. a network transformer; 103. a rectifying unit; 104. a first switch; 105. a PD protocol unit; 106. a load adjustable unit; 107. a current detection unit; 108. a first classification unit; 109. a second classification unit; 110. a driving unit; 111. a voltage control unit; 112. a processing unit; 113. a display unit; 121. an isolation module; 122. a digital-to-analog converter; 123. a voltage output unit; 131. a first driving unit; 132. and a second driving unit.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be understood that the present utility model may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the utility model to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for the same elements throughout for clarity.

It will be understood that when an element or layer is referred to as being "on" …, "" adjacent to "…," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" …, "" directly adjacent to "…," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present utility model.

Spatially relative terms, such as "under …," "under …," "below," "under …," "above …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under …" and "under …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for the purpose of providing a thorough understanding of the present utility model, detailed structures and steps are presented in order to illustrate the technical solution presented by the present utility model. Preferred embodiments of the present utility model are described in detail below, however, the present utility model may have other embodiments in addition to these detailed descriptions.

The embodiment of the utility model provides a testing device of PD equipment, which aims to solve the problems that the supporting protocol is less, current and voltage detection cannot be carried out and output is not visual in the prior art.

The technical solution provided by the embodiment of the present utility model, as shown in fig. 1, relates to a testing device for PD equipment, including: the power grid interface device comprises a grid interface 101, a network transformer 102, a rectifying unit 103, a first switch 104, a PD protocol unit 105, a load adjustable unit 106, a detection unit 107, a first grading unit 108, a second grading unit 109, a driving unit 110, a voltage control unit 111, a processing unit 112 and a display unit 113;

the input end of the network transformer 102 is connected with the network port 101, the output end of the network transformer 102 is connected with the input end of the rectifying unit 103, the output end of the rectifying unit 103 is respectively connected with the first end of the first switch 104 and the input end of the detecting unit 107, the second end of the first switch 104 is connected with the input end of the PD protocol unit 105 and one end of the load adjustable unit 106, the output end of the PD protocol unit 105 is connected with the other end of the load adjustable unit 106, the first grading end of the PD protocol unit 105 is connected with the input end of the first grading unit 108, the second grading end of the PD protocol unit 105 is connected with the input end of the second grading unit 109, the load adjustable unit 106 is connected with the two ends of the voltage control unit 111 in parallel, the driving unit 110 is respectively connected with the control end of the first switch 104, the control end of the first grading unit 108, the control end of the second grading unit 109 and the control end of the load adjustable unit 106, the output end of the detecting unit 107 is connected with the input end of the processing unit 112, and the processing unit 112 is connected with the driving unit 110, the voltage control unit 111 and the display unit 113.

As shown in fig. 2, the testing device has a plurality of interfaces 151, when each interface 151 performs testing, the interfaces 151 can be connected with the network port 101 by using a network cable, so that data transmission and power supply can be performed, the network port 101 is connected with the network transformer 102, and the network transformer 102 is mainly used for signal transmission, impedance matching, waveform repairing, signal clutter suppression and high voltage isolation. The network transformer 102 may isolate different levels between different network devices connected by the network cable to prevent different voltages from damaging the devices by transmission through the network cable. The network transformer 102 is further electrically connected with the rectifying unit 103, the rectifying unit 103 comprises a rectifying diode, the rectifying unit 103 is connected with the PD protocol unit 105, the PD protocol unit 105 realizes POE protocol negotiation, and class level is determined. As an example, the whole machine is designed to be 12 PD test PORTs in total, the size 440mm x 360mm x 44mm, the connection is made by adopting a connector of 2*1, and one more con connector and reset button, and a dial switch are added.

As shown in fig. 3, the PD protocol unit 105 is a chip TPS2373-4, the CLSA pin of the chip TPS2373-4 is a first grading terminal, and the CLSB pin of the chip TPS2373-4 is a second grading terminal.

Specifically, the chip TPS2373-4 is an integrated POE controller, which can be used in Power Sourcing Equipment (PSE) conforming to IEEE 802.3af, IEEE 802.3at and IEEE 802.3bt standards, and is mainly used for managing and controlling a power sourcing process of the power sourcing equipment to a power sourcing equipment (PD). Setting up TPS2373-4 in the PD test apparatus may help the user test the performance and reliability of the PSE device to ensure compliance with the relevant PoE standard and may provide power and data transmission to the PD device with stability and reliability. Specifically, setting TPS2373-4 in the PD TEST system may implement the following functions: the power supply process of the power supply device to the power supply device is managed and controlled to ensure compliance with the IEEE 802.3af, IEEE 802.3at and IEEE 802.3bt standards, and power and data transmission can be provided to the PD device stably and reliably. Parameters such as output current, voltage and power of the PSE device are monitored and controlled to ensure that it is able to operate reliably and stably under a variety of different load conditions. Through the TPS2373 self-adaptive power control function, the PSE device can automatically identify PD devices with different powers and control power supply, so that the power utilization rate and efficiency are improved to the greatest extent.

Further, the first grading unit 108 includes a switch K2, a switch K3, a resistor R2 and a resistor R3, wherein a first end of the switch K2 is connected to a first end of the switch K3, a second end of the switch K2 is commonly connected to a first end of the resistor R2 and is connected to a CLSA pin of the chip TPS2373-4, a second end of the switch K3 is connected to a first end of the resistor R3, and a second end of the resistor R2 is commonly connected to a second end of the resistor R3 and is connected to a VSS pin of the chip TPS 2373-4. The second grading unit 109 comprises a switch K4, a switch K5, a resistor R4 and a resistor R5, wherein a first end of the switch K4 is commonly connected with a first end of the switch K5 and is connected with a CLSB pin of the chip TPS2373-4, a second end of the switch K4 is connected with a first end of the resistor R4, a second end of the switch K5 is connected with a first end of the resistor R5, and a second end of the resistor R4 is commonly connected with a second end of the resistor R5 and is connected with a VSS pin of the chip TPS 2373-4.

Wherein, as shown in fig. 3-5, two external resistors are connected between CLSA and CLSB pins and VSS of the TPS2373-4 chip, each pin and VSS providing a different class for the PSE and used to define the power class requested by the PD. TPS2373-4 chips specify that when the voltage difference between VDD and VSS is about 10.9V to 22V, the controller places a voltage of about 2.5V on the CLSA or CLSB external resistor. The current level is determined by the current determined by each resistor, the internal leakage current of the controller and the leakage current through the MOS inside the chip.

Wherein, support the classification of BT protocol needs two classification pins of CLSA and CLAB, different PD classification needs to set up the resistance of CLSA and CLAB pin. The CLSA pin and the CLSB pin are connected with two grading resistors with different resistance values separately. The automatic control configuration in turn gets 4 IO models from the relay switch driver to complete the control.

As shown in fig. 6 and fig. 7, the voltage control unit 111 includes an isolation module 121, a digital-to-analog converter 122, and a voltage output unit 123 that are sequentially connected, where the isolation module 121 is connected to the processing unit 112, and an output end of the voltage output unit 123 is connected to two ends of the load adjustable unit 106.

Specifically, the isolation module 121 is a chip SI8600AB-B-ISR, the digital-to-analog converter 122 is a PCF8591DAC chip, and the PCF8591DAC chip is used to output a VREF voltage, and then the VGS voltage of the control MOS is output through the operational amplifier. And meanwhile, a negative feedback circuit is adopted for control. After each re-classification according to the POE protocol, if a re-classification is required, a power down is required to complete the new classification. A first switch 104 must be added to the input of TPS2373-4 to control one turn of on/off after the re-classification.

The PCF8591DAC chip needs to be connected with CPLD for control, and is connected through I2C, but is not directly connected, and is isolated by SI8600 AB-B-ISR. Because different load power consumption is needed, the control of the current is completed by adopting a constant current electronic load principle, so that the power is controlled. According to the constant current load principle: the magnitude of the ID current is controlled by controlling the magnitude of the VGS voltage in a state where the MOS is guaranteed to be fully on. Thereby completing the control of the current and meeting the control requirement of the power. In the scheme, PCF8591DAC chips are adopted to output VREF voltage, and then VGS voltage of an output control MOS is carried out through an operational amplifier. And meanwhile, a negative feedback circuit is adopted for control.

Specifically, PCF8591 is an integrated 8-bit analog-to-digital/digital converter 122 (ADC/DAC) that can be used to TEST the performance of PoE devices in PD TEST systems. Setting PCF8591 in a PD TEST system may implement the following functions: parameters such as current, voltage and power of the PD device are monitored to ensure compliance with the IEEE 802.3af, IEEE 802.3at and IEEE 802.3bt standards and to operate reliably and stably under a variety of different load conditions. The analog signal of the PD device is converted into a digital signal by the analog-to-digital conversion function of PCF8591, and is transmitted to the PD TEST system for analysis and processing to verify the performance and reliability of the PD device. Digital signals in the PD TEST system are converted into analog signals through the digital-to-analog conversion function of the PCF8591 and are transmitted to the PD equipment for testing, so that the performance and the reliability of the PD equipment are verified.

Further, as shown in fig. 8, the voltage output unit 123 includes a resistor R6, a resistor R7, a resistor R8, a resistor Rs, a capacitor C1, an operational amplifier U1, and a MOS transistor Q1, where a first end of the resistor R6 is an input end of the voltage output unit 123, a second end of the resistor R6 is connected to a non-inverting input end of the operational amplifier U1, an output end of the operational amplifier U1 is connected to a first end of the capacitor C1 and a first end of the resistor R7, a second end of the resistor R7 is connected to a gate of the MOS transistor, a drain of the MOS transistor is a first output end of the voltage output unit 123, a source of the MOS transistor is connected to a second end of the resistor R8 and a first end of the resistor Rs, and a first end of the resistor R8 is connected to a second end of the capacitor C1 and an inverting input end of the operational amplifier U1.

As shown in fig. 9 to 11, the driving unit 110 includes a first driving unit 131 and a second driving unit 132, an input end of the first driving unit 131 is connected to an output end of the processing unit 112, an output end of the first driving unit 131 is connected to a control end of the first classifying unit 108 and a control end of the second classifying unit 109, an input end of the second driving unit 132 is connected to an output end of the processing unit 112, and an output end of the second driving unit 132 is connected to a control end of the first switch 104 and a control end of the load adjustable unit 106.

The load adjustable unit 106 includes a switch K6, a switch K7, a switch K8, a resistor R11, a resistor R12, and a resistor R13, where a first end of the switch K6 is connected to a first end of the switch K7 and a first end of the switch K8, a second end of the switch K6 is connected to a first end of the resistor R11, a second end of the switch K7 is connected to a first end of the resistor R12, a second end of the switch K8 is connected to a first end of the resistor R13, and a second end of the resistor R11, a second end of the resistor R12, and a second end of the resistor R13 are connected together to form a second end of the load adjustable unit 106.

The first driving unit 131 is connected to the control ends of the switch K2, the switch K3, the switch K4 and the switch K5, and the second driving unit 132 is connected to the control end of the first switch 104, the control end of the switch K6, the control end of the switch K7 and the control end of the switch K8.

The first driving unit 131 and the second driving unit 132 are chips MAX4280.

Specifically, the chip MAX4280 is a high-speed, low-noise, precision differential amplifier. An SPI interface is provided to control external switching circuitry. When MAX4280 is used, the clock, chip select, data and clock signals need to be connected to the CPLD or other controller to control the state of the switching circuit via the SPI interface protocol. The switching circuit may be formed of a plurality of switch combinations, each of which is formed of a gradation resistance combination and a load control circuit. When MAX4280 is used, the switching circuit needs to be designed and selected according to the specific application scenario and requirements. The CPLD or other controller is then used to control the state of the switching circuit to achieve the desired function. To control 8 switches, an external digital switch matrix may be controlled using the SPI interface of MAX4280. The digital switch matrix is a switch matrix in which each switch is controlled by a digital controller. In this example, the CPLD may act as a digital controller. In the switch matrix, each switch is connected by a pin to the input of MAX4280. The CPLD is connected to the SPI interface of MAX4280 to control the state of the switch. By sending appropriate instructions to the CPLD, the state of any one of the switches in the switch matrix can be controlled.

Wherein, as shown in fig. 12, the detection unit 107 includes a plurality of chips LMA5056. Each port requires detection of voltage and current. The LM5056A is adopted to detect power input voltage, input current and input power, supports the SMBus bus protocol, has three address pins and can manage 27 devices.

Wherein, as shown in fig. 13, after the PD power supply is successful, the display of the LED display lamp 141 is confirmed by reading the status of the gradation register of each power supply port. Different hierarchical modes require different colored lights for display, so three lights are required for each port. And the test system feeds back the power states of the ports through power management, confirms whether the load power of all the ports is in a normal range, polls the power condition of each port and finally judges whether the test is passed. And displaying pass and fail through test results of the LED and the upper computer of the device. Console143 displays CPLD startup configuration information, corresponding configuration is carried out by assigning values to the designated registers through Console143 and RS142, and the corresponding registers are read through Console ports.

According to the technical scheme provided by the embodiment, the load is simulated by the load adjustable unit, the power of the load of the PD equipment is dynamically adjusted, and the function measurement of the PD equipment is realized; three standards of 802.3af (PoE), 802.3at (PoE+), 802.3bt (PoE++) are supported, and the processing unit measures voltage and current and calculates power in real time; the display unit displays the voltage and the current measured by the processing unit and the calculated power in real time; the detection of a plurality of ports of the PD equipment can be realized, a large amount of time is saved, the whole testing process is more efficient, and the use of a large number of different power equipment is avoided; the multi-port test device solves the problems that in the prior art, equipment with different powers needs to be replaced continuously, the test process is complex, the efficiency is low, the test parameters cannot be displayed in real time, and the like; the test speed is high in production test, the test integration level is high, the visualization degree of the test result is high, and the test data is convenient to reserve; the production level can be improved.

The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model, and are intended to be included in the scope of the present utility model.

Claims (10)

1. A test apparatus for a PD device, comprising: the system comprises a network port, a network transformer, a rectifying unit, a first switch, a PD protocol unit, a load adjustable unit, a detecting unit, a first grading unit, a second grading unit, a driving unit, a voltage control unit, a processing unit and a display unit;

the input end of the network transformer is connected with the network port, the output end of the network transformer is connected with the input end of the rectifying unit, the output end of the rectifying unit is respectively connected with the first end of the first switch and the input end of the detecting unit, the second end of the first switch is connected with the input end of the PD protocol unit and one end of the load adjustable unit, the output end of the PD protocol unit is connected with the other end of the load adjustable unit, the first grading end of the PD protocol unit is connected with the input end of the first grading unit, the second grading end of the PD protocol unit is connected with the input end of the second grading unit, the two ends of the load adjustable unit are connected with the two ends of the voltage control unit, the driving unit is respectively connected with the control end of the first switch, the control end of the first grading unit, the control end of the load adjustable unit and the control end of the load adjustable unit, the output end of the detecting unit is connected with the input end of the processing unit, and the processing unit, the voltage control unit and the driving unit are connected with the display unit.

2. The test apparatus of claim 1, wherein the PD protocol unit is a chip TPS2373-4, a CLSA pin of the chip TPS2373-4 is a first classification terminal, and a CLSB pin of the chip TPS2373-4 is a second classification terminal.

3. The test device of claim 2, wherein the first grading unit comprises a switch K2, a switch K3, a resistor R2, and a resistor R3, wherein a first end of the switch K2 is commonly connected with a first end of the switch K3 and is connected to a CLSA pin of the chip TPS2373-4, a second end of the switch K2 is connected with a first end of the resistor R2, a second end of the switch K3 is connected with a first end of the resistor R3, and a second end of the resistor R2 is commonly connected with a second end of the resistor R3 and is connected to a VSS pin of the chip TPS 2373-4.

4. The test apparatus of claim 2, wherein the second classification unit comprises a switch K4, a switch K5, a resistor R4, and a resistor R5, wherein a first end of the switch K4 is commonly connected with a first end of the switch K5 and is connected to a CLSB pin of the chip TPS2373-4, a second end of the switch K4 is connected with a first end of the resistor R4, a second end of the switch K5 is connected with a first end of the resistor R5, and a second end of the resistor R4 is commonly connected with a second end of the resistor R5 and is connected to a VSS pin of the chip TPS 2373-4.

5. The test device of claim 1, wherein the voltage control unit comprises an isolation module, a digital-to-analog converter and a voltage output unit which are sequentially connected, wherein an input end of the isolation module is connected with the processing unit, and an output end of the voltage output unit is connected with two ends of the load adjustable unit.

6. The test device of claim 5, wherein the voltage output unit comprises a resistor R6, a resistor R7, a resistor R8, a resistor Rs, a capacitor C1, an operational amplifier U1 and a MOS transistor Q1, wherein a first end of the resistor R6 is an input end of the voltage output unit, a second end of the resistor R6 is connected to a non-inverting input end of the operational amplifier U1, an output end of the operational amplifier U1 is connected to the first end of the capacitor C1 and the first end of the resistor R7, a second end of the resistor R7 is connected to a gate of the MOS transistor, a drain of the MOS transistor is the first output end of the voltage output unit, a source of the MOS transistor is connected to the second end of the resistor R8 and the first end of the resistor Rs, a first end of the resistor R8 is connected to the second end of the capacitor C1 and an inverting input end of the operational amplifier U1, and a second end of the resistor Rs is the second output end of the voltage output unit.

7. The test device of claim 1, wherein the driving unit comprises a first driving unit and a second driving unit, an input end of the first driving unit is connected with an output end of the processing unit, an output end of the first driving unit is connected with a control end of the first grading unit and a control end of the second grading unit, an input end of the second driving unit is connected with an output end of the processing unit, and an output end of the second driving unit is connected with a control end of the first switch and a control end of the load adjustable unit.

8. The test apparatus of claim 7, wherein the first drive unit and the second drive unit are chips MAX4280.

9. The test device of claim 1, wherein the detection unit comprises a plurality of chips LMA5056.

10. The test device of claim 1, wherein the load adjustable unit comprises a switch K6, a switch K7, a switch K8, a resistor R11, a resistor R12, and a resistor R13, wherein a first end of the switch K6 is connected to the first end of the switch K7 and the first end of the switch K8, a second end of the switch K6 is connected to the first end of the resistor R11, a second end of the switch K7 is connected to the first end of the resistor R12, a second end of the switch K8 is connected to the first end of the resistor R13, and the second end of the resistor R11, the second end of the resistor R12, and the second end of the resistor R13 are commonly connected as the second end of the load adjustable unit.