CN220023501U - Crystalline silicon/perovskite laminated solar cell - Google Patents

Crystalline silicon/perovskite laminated solar cell Download PDF

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CN220023501U
CN220023501U CN202321683194.0U CN202321683194U CN220023501U CN 220023501 U CN220023501 U CN 220023501U CN 202321683194 U CN202321683194 U CN 202321683194U CN 220023501 U CN220023501 U CN 220023501U
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Shenzhen Heijing Optoelectronic Technology Co ltd
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Abstract

The utility model provides a crystalline silicon/perovskite laminated solar cell which comprises a crystalline silicon cell and a perovskite cell, wherein an N-type substrate doping layer is arranged at the top of the crystalline silicon cell, and a P-type perovskite absorption layer is arranged at the bottom of the perovskite cell. The P-type perovskite absorption layer is arranged at the bottom of the perovskite cell, namely the intrinsic perovskite absorption layer is subjected to P-type doping. The energy level of the doped P-type perovskite absorption layer is bent on the lower surface, so that the energy level barrier for hole transmission is eliminated, and the P-type perovskite absorption layer has higher hole selective transmission property, namely has higher photoelectric conversion efficiency without a hole transmission layer. The P-type perovskite absorption layer and the N-type substrate doped layer have lower contact resistance, can generate ohmic contact, can also efficiently work without an intermediate tunneling layer, and have high photoelectric conversion efficiency. The crystalline silicon/perovskite laminated solar cell provided by the embodiment of the utility model has higher stability due to the removal of the tunneling layer and the hole transport layer.

Description

Crystalline silicon/perovskite laminated solar cell
Technical Field
The utility model belongs to the technical field of solar cells, and particularly relates to a crystalline silicon/perovskite laminated solar cell.
Background
Solar energy is a new clean energy source which is attractive and has the advantages of a large amount of resources and low cost. At present, photovoltaic cells are one of the most effective ways to convert solar energy into electric energy, and solar cells such as monocrystalline silicon and polycrystalline silicon have already been industrialized. In recent years, the crystal silicon/perovskite lamination technology has become one of the research hotspots in the photovoltaic technology field, and is in great attention. The development of the technology has important significance for improving the photoelectric conversion efficiency of the solar cell and reducing the manufacturing cost, thereby promoting the further development and application of the solar power generation technology. The theoretical effective photoelectric conversion efficiency of the crystalline silicon/perovskite laminated solar cell is up to more than 40%, and is far higher than that of the crystalline silicon solar cell. The basic principle of the crystalline silicon/perovskite lamination technology is that perovskite materials and crystalline silicon materials are stacked together to form a heterojunction, and the photoelectric conversion efficiency of the solar cell is improved by utilizing the wide band gap, high absorption coefficient and high carrier mobility of the perovskite materials, the stability and good electron transmission performance of the crystalline silicon materials.
Currently, in the existing crystalline silicon/perovskite stacked solar cell, in order to connect the perovskite top cell and the crystalline silicon bottom cell together, a transparent oxide conductive layer is generally used as an intermediate tunneling layer in the stacked structure; in addition, in perovskite top cells, a hole transport layer is typically fabricated on top of the intermediate tunneling layer for better hole extraction selectivity. However, the tunneling layer and the hole transport layer have the following disadvantages: 1. the two film layers are prepared on the crystalline silicon bottom cell, so that certain optical loss is caused to the crystalline silicon bottom cell, and the photoelectric conversion current of the laminated solar cell is reduced; 2. the instability problems of the two layers of film layers, such as unstable materials, unstable interface contact of the film layers and the like, can finally cause the stability problem of the laminated solar cell; 3. the two film layers increase the manufacturing process of the laminated solar cell, thereby increasing the production cost of the laminated solar cell and being unfavorable for large-scale commercial production and application.
Disclosure of Invention
The embodiment of the utility model aims to provide a crystalline silicon/perovskite laminated solar cell for solving the problems existing in the related art: due to the existence of the tunneling layer and the hole transport layer, the crystalline silicon/perovskite laminated solar cell has the problems of low photoelectric conversion efficiency and poor stability.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the utility model is as follows:
the crystal silicon/perovskite laminated solar cell comprises a crystal silicon cell and a perovskite cell positioned above the crystal silicon cell, wherein an N-type substrate doping layer is arranged at the top of the crystal silicon cell, a P-type perovskite absorption layer is arranged at the bottom of the perovskite cell, and the surface of the N-type substrate doping layer is attached to the bottom surface of the P-type perovskite absorption layer.
In one embodiment, the crystalline silicon cell includes a base layer, the N-type base doped layer, and a base electrode layer; the N-type substrate doping layer is arranged on the surface of the substrate layer, and the substrate electrode layer is arranged on the bottom surface of the substrate layer.
In one embodiment, the base layer comprises a substrate, a base surface passivation layer arranged on the surface of the substrate, a base bottom passivation layer arranged on the bottom surface of the substrate and a P-type base doping layer arranged on the bottom surface of the base bottom passivation layer; the N-type substrate doping layer is arranged on the surface of the passivation layer on the substrate surface, and the substrate electrode layer is arranged on the bottom surface of the P-type substrate doping layer.
In one embodiment, the base electrode layer includes a first transparent electrode layer disposed on a bottom surface of the P-type base doped layer and a first metal electrode layer disposed on a bottom surface of the first transparent electrode layer.
In one embodiment, the perovskite battery includes the P-type perovskite absorber layer, a top passivation layer disposed on a surface of the P-type perovskite absorber layer, an electron transport layer disposed on a surface of the top passivation layer, and a top electrode layer disposed on a surface of the electron transport layer.
In one embodiment, the top electrode layer includes a second transparent electrode layer disposed on a surface of the electron transport layer and a second metal electrode layer disposed on a surface of the second transparent electrode layer.
In one embodiment, the perovskite battery further comprises a buffer layer disposed between the electron transport layer and the top electrode layer.
In one embodiment, the buffer layer has a thickness in the range of 1nm to 30nm.
In one embodiment, the perovskite cell further comprises an anti-reflection layer provided on a surface of the top electrode layer.
In one embodiment, the crystalline silicon cell is disposed in series with the perovskite cell.
The crystalline silicon/perovskite laminated solar cell provided by the embodiment of the utility model has at least the following beneficial effects: the P-type perovskite absorption layer is arranged at the bottom of the perovskite cell, namely the intrinsic perovskite absorption layer is subjected to P-type doping. The energy level of the doped P-type perovskite absorption layer is bent on the lower surface, so that the energy level barrier for hole transmission is eliminated, and the perovskite absorption layer has higher hole selective transmission property, so that a perovskite battery has higher photoelectric conversion efficiency without a hole transmission layer. And the P-type perovskite absorption layer and the N-type substrate doped layer have lower contact resistance, can generate ohmic contact, can also efficiently work without an intermediate tunneling layer, and have high photoelectric conversion efficiency. The crystalline silicon/perovskite laminated solar cell provided by the embodiment of the utility model is not influenced by the instability of the two film layers because the tunneling layer and the hole transport layer are removed, and has higher stability.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments or exemplary technical descriptions will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and other drawings can be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a crystalline silicon/perovskite stacked solar cell according to an embodiment of the present utility model;
fig. 2 is a schematic structural diagram of a crystalline silicon/perovskite stacked solar cell with a tunneling layer and without a hole transport layer according to a comparative example of the present utility model;
fig. 3 is a schematic structural diagram of a crystalline silicon/perovskite stacked solar cell with a hole transport layer based on no tunneling layer according to a second comparative example of the present utility model;
fig. 4 is a schematic structural diagram of a crystalline silicon/perovskite stacked solar cell with a tunneling layer and a hole transport layer according to a third embodiment of the present utility model.
Wherein, each reference numeral in the figure mainly marks:
1. a crystalline silicon cell; 10. an N-type substrate doping layer; 11. a base layer; 111. a substrate; 112. a passivation layer on the surface of the substrate; 113. a passivation layer on the bottom surface of the substrate; 114. a P-type substrate doping layer; 12. a base electrode layer; 121. a first transparent electrode layer; 122. a first metal electrode layer;
2. a perovskite battery; 20. a P-type perovskite absorption layer; 21. a top passivation layer; 22. an electron transport layer; 23. a top electrode layer; 231. a second transparent electrode layer; 232. a second metal electrode layer; 24. a buffer layer; 25. an anti-reflection layer;
30. a tunneling layer; 40. and a hole transport layer.
Description of the embodiments
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.
In the description of the present utility model, it should be understood that the terms "center," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, are merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model.
In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present utility model. Thus, the appearances of the phrase "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Currently, as shown in fig. 4, in the conventional crystalline silicon/perovskite stacked solar cell, a transparent oxide conductive layer is generally used as the intermediate tunneling layer 30 in order to connect the perovskite cell 2 and the crystalline silicon cell 1 together. In addition, in perovskite cell 2, a hole transport layer 40 is typically formed over intermediate tunneling layer 30 for better hole extraction. In a general structure, a stacked solar cell having a tunneling layer 30 and a hole transport layer 40 has the following disadvantages: 1. the two film layers are prepared on the crystalline silicon bottom cell, so that certain optical loss is caused to the crystalline silicon bottom cell, and the photoelectric conversion current of the laminated solar cell is reduced; 2. the instability problems of the two layers of film layers, such as unstable materials, unstable interface contact of the film layers and the like, can finally cause the stability problem of the laminated solar cell; 3. the two film layers increase the manufacturing process of the laminated solar cell, thereby increasing the production cost of the laminated solar cell and being unfavorable for large-scale commercial production and application.
If the tunneling layer 30 is directly removed, the hole transport layer 40 of the perovskite cell 2 is in direct contact with the N-type substrate doped layer 10 of the crystalline silicon cell 1. In this case, most of the hole transport layer 40, such as nickel oxide, generates a large contact resistance with the N-type base doping layer 10 of the crystalline silicon cell 1 depending on the material properties of the hole transport layer 40, thereby impeding current conduction of the stacked solar cell and reducing efficiency of the stacked solar cell.
If the hole transport layer 40 is directly removed, holes generated by the perovskite absorption layer cannot be selectively extracted, resulting in low photoelectric conversion efficiency of the perovskite cell 2 and thus low efficiency of the stacked solar cell.
In order to solve the above problems, the embodiment of the utility model provides a crystalline silicon/perovskite stacked solar cell, which can well solve the problems of low photoelectric conversion efficiency and poor stability of the crystalline silicon/perovskite stacked solar cell caused by the existence of a tunneling layer 30 and a hole transport layer 40.
Referring to fig. 1, a crystalline silicon/perovskite stacked solar cell according to an embodiment of the present utility model will now be described. The crystalline silicon/perovskite laminated solar cell comprises a crystalline silicon cell 1 and a perovskite cell 2. The perovskite battery 2 may be disposed above the crystalline silicon battery 1. The top of the crystalline silicon cell 1 is provided with an N-type substrate doping layer 10, and the bottom of the perovskite cell 2 is provided with a P-type perovskite absorption layer 20; the surface of the N-type base doped layer 10 is bonded to the bottom surface of the P-type perovskite absorption layer 20.
In this structure, the P-type perovskite light absorbing layer 20 is provided at the bottom of the perovskite cell 2, i.e., the intrinsic perovskite light absorbing layer is P-doped. The energy level of the doped P-type perovskite absorption layer 20 is bent on the lower surface, so that the energy level barrier for hole transport is eliminated, and the perovskite battery 2 has higher hole selective transport property, so that the perovskite battery 2 has higher photoelectric conversion efficiency without the hole transport layer 40. In addition, the P-type perovskite absorption layer 20 and the N-type substrate doping layer 10 have lower contact resistance, can generate ohmic contact, can efficiently work without the intermediate tunneling layer 30, and have high photoelectric conversion efficiency. The crystalline silicon/perovskite stacked solar cell provided by the embodiment of the utility model is not affected by the instability of the two film layers and has higher stability due to the removal of the tunneling layer 30 and the hole transport layer 40.
In one embodiment, referring to fig. 1, as a specific implementation of the crystalline silicon/perovskite stacked solar cell provided in the embodiment of the present utility model, a crystalline silicon cell 1 includes a substrate layer 11, an N-type substrate doping layer 10, and a substrate electrode layer 12. Optionally, the N-type substrate doping layer 10 is disposed on the surface of the substrate layer 11, and the substrate electrode layer 12 is disposed on the bottom surface of the substrate layer 11. In this structure, the substrate layer 11 can play a role of supporting and isolating, and can isolate the N-type substrate doping layer 10 from the substrate electrode layer 12, so as to avoid mutual influence. The base electrode layer 12 has a conductive function and can be electrically connected to other components.
In one embodiment, referring to fig. 1, as a specific implementation of the crystalline silicon/perovskite stacked solar cell provided in the embodiment of the present utility model, the base layer 11 includes a substrate 111, a base surface passivation layer 112, a base bottom passivation layer 113 and a P-type base doping layer 114. Alternatively, the base surface passivation layer 112 may be disposed on the surface of the substrate 111, and the N-type base doped layer 10 may be disposed on the surface of the base surface passivation layer 112; the base bottom passivation layer 113 may be disposed on the bottom surface of the substrate 111; the P-type substrate doping layer 114 may be disposed on the bottom surface of the substrate bottom passivation layer 113; the bottom electrode layer 12 may be disposed on the bottom surface of the P-type doped substrate 114. Wherein the substrate 111 may be made of a silicon material. With this structure, the substrate 111, the base surface passivation layer 112, the base bottom passivation layer 113, and the P-type base doped layer 114 are stacked, which contributes to improvement of photoelectric conversion efficiency and stability of the crystalline silicon/perovskite stacked solar cell.
In one embodiment, referring to fig. 1, as a specific implementation of the crystalline silicon/perovskite stacked solar cell provided in the embodiment of the present utility model, the base electrode layer 12 includes a first transparent electrode layer 121 and a first metal electrode layer 122. Alternatively, the first transparent electrode layer 121 may be disposed on the bottom surface of the P-type doped substrate layer 114, and the first metal electrode layer 122 may be disposed on the bottom surface of the first transparent electrode layer 121. With this structure, the charge collection efficiency can be improved by the first transparent electrode layer 121 and the first metal electrode layer 122, which contributes to improvement of the filling factor and stability of the crystalline silicon/perovskite stacked solar cell.
In one embodiment, referring to fig. 1, as a specific implementation of the crystalline silicon/perovskite stacked solar cell provided in the embodiment of the present utility model, the perovskite cell 2 includes a P-type perovskite absorption layer 20, a top passivation layer 21, an electron transport layer 22, and a top electrode layer 23. Alternatively, the top passivation layer 21 may be provided on the surface of the P-type perovskite absorption layer 20, the electron transport layer 22 may be provided on the surface of the top passivation layer 21, and the top electrode layer 23 may be provided on the surface of the electron transport layer 22. In this structure, the top passivation layer 21 separates the P-type perovskite absorption layer 20 from the electron transport layer 22, avoiding interactions. The electron transport layer 22 plays an important role in transporting electrons, blocking electron-hole recombination, and the like. The top electrode layer 23 has a conductive effect to make electrical connection with other components.
In one embodiment, referring to fig. 1, as a specific implementation of the crystalline silicon/perovskite stacked solar cell provided in the embodiment of the present utility model, the top electrode layer 23 includes a second transparent electrode layer 231 and a second metal electrode layer 232. Alternatively, the second transparent electrode layer 231 may be disposed on the surface of the electron transport layer 22, and the second metal electrode layer 232 may be disposed on the surface of the second transparent electrode layer 231. With this structure, the charge collection efficiency can be improved by the second transparent electrode layer 231 and the second metal electrode layer 232, which contributes to improvement of the filling factor and stability of the crystalline silicon/perovskite stacked solar cell.
In one embodiment, referring to fig. 1, as a specific implementation of the crystalline silicon/perovskite stacked solar cell provided in the embodiment of the present utility model, the perovskite cell 2 further includes a buffer layer 24, where the buffer layer 24 may be disposed between the electron transport layer 22 and the top electrode layer 23, specifically, between the electron transport layer 22 and the second transparent electrode layer 231. In this structure, the buffer layer 24 separates the electron transport layer 22 from the top electrode layer 23, so as to avoid interference between the two layers.
In one embodiment, as a specific implementation of the crystalline silicon/perovskite stacked solar cell provided in the embodiment of the present utility model, the thickness of the buffer layer 24 ranges from 1nm to 30nm. This structure contributes to improvement of photoelectric conversion efficiency and stability of the crystalline silicon/perovskite stacked solar cell.
In an embodiment, referring to fig. 1, as a specific implementation of the crystalline silicon/perovskite stacked solar cell provided in the embodiment of the present utility model, the perovskite cell 2 further includes an anti-reflection layer 25, where the anti-reflection layer 25 may be disposed on a surface of the top electrode layer 23, specifically on a surface of the second metal electrode layer 232. In this structure, the antireflection layer 25 can enhance the absorptivity of the crystalline silicon/perovskite stacked solar cell to sunlight, and the operational stability.
In one embodiment, referring to fig. 1, as a specific implementation of the crystalline silicon/perovskite stacked solar cell provided in the embodiment of the present utility model, a crystalline silicon cell 1 is disposed in series with a perovskite cell 2. With the structure, the crystalline silicon cell 1 can absorb the infrared light which cannot be utilized by the perovskite cell 2, so that the conversion from ultraviolet light to visible light or near infrared light is realized, the light absorption performance of the crystalline silicon/perovskite laminated solar cell is improved, and the photoelectric conversion efficiency is further improved.
Referring to fig. 1, the specific structure of the crystalline silicon/perovskite stacked solar cell provided in the embodiment of the utility model is as follows: the substrate comprises a first metal electrode layer 122, a first transparent electrode layer 121, a P-type substrate doping layer 114, a substrate bottom surface passivation layer 113, a substrate 111, a substrate surface passivation layer 112, an N-type substrate doping layer 10, a P-type perovskite absorption layer 20, a top passivation layer 21, an electron transport layer 22, a buffer layer 24, a second transparent electrode layer 231, a second metal electrode layer 232 and an antireflection layer 25. The manufacturing steps of the crystalline silicon/perovskite laminated solar cell provided by the embodiment are as follows:
step one: a base bottom passivation layer 113 and a P-type base doping layer 114 are sequentially prepared on the bottom surface of the substrate 111, and a base surface passivation layer 112 and an N-type base doping layer 10 are sequentially prepared on the surface of the substrate 111.
Step two: the first transparent electrode layer 121 is prepared. Optionally, the sample wafer is placed in a magnetron sputtering device by using a magnetron sputtering method, and the power is controlled between 50W and 200W. Specifically, the control power was 60W, the running time was 1.5h, and the film thickness was 10nm.
Step three: the first metal electrode layer 122 is prepared. Optionally, the prepared substrate sample is placed on a mask plate by an evaporation method, and is placed in a chamber of an evaporator, wherein the evaporation vacuum degree is 5 multiplied by 10 -5 -2×10 -4 Pa, evaporating temperature at 500-2000 deg.C, evaporating rate at 0.1-5A/S. Specifically, the vapor deposition vacuum degree was 2×10 -4 And (3) performing evaporation in Pa, adjusting the evaporation voltage to the evaporation temperature, controlling the evaporation rate to be 2.5A/S, and evaporating silver on the layer film with the thickness of 200nm.
Step four: the P-type perovskite absorber layer 20 is prepared.
Optionally, preparing perovskite precursor liquid by using a spin coating method, uniformly coating the perovskite precursor liquid on the surface of the N-type substrate doping layer 10, and then using an antisolvent for dynamic spin coating, wherein the spin coating rotating speed is 1200-6000rpm, the spin coating time is 20-120s, and the antisolvent titration time is 10-50s after the starting rotating speed. And after spin coating, carrying out annealing operation, wherein the annealing temperature is 50-150 ℃ and the annealing time is 5-40min. Wherein, the dissolving solvent of the perovskite precursor solution comprises at least one of Dimethylformamide (DMF), G-butyrolactone (GBL), dimethyl sulfoxide (DMSO) and N, N-Dimethylacetamide (DMA), and the solvent ratio is 0-3: between 10 and 7. The antisolvent comprises at least one of toluene (Tol), chlorobenzene (CB), and Ethyl Acetate (EA).
Alternatively, a flash evaporation method can be used to prepare the perovskite precursor solution, and the perovskite precursor solution is uniformly coated on the surface of the N-type substrate doped layer 10, wherein the spin coating speed is 1000-6000rpm, and the spin coating time is 20-120s. And (3) after spin coating, performing flash evaporation operation, wherein the flash evaporation time is 10-60s, the flash evaporation temperature is 0-100 ℃, and after the flash evaporation is finished, performing annealing treatment, the annealing temperature is 50-150 ℃ and the annealing time is 5-40min.
Alternatively, perovskite precursor powder can be prepared by vapor deposition method, and the perovskite precursor powder is evaporated onto the surface of the N-type substrate doped layer 10, with vapor deposition vacuum degree of 1-3×10 -4 The evaporation temperature is 200-700 ℃ between Pa. The P-type perovskite precursor liquid is ABX 3 The structural perovskite is regulated by stoichiometric ratio and dissolved with organic solvent, the concentration is between 1.5 and 2M, and 0 to 30mol percent of P-type doping material is added according to the proportion. Wherein ABX 3 In the structural perovskite, the A position is an organic cation, including CH 3 NH 3 + (MA + )、NH 2 CH=NH 2 + (FA + )、CH 3 CH 2 NH 3 + Or Cs + At least one of them. The B position is a metal cation including Pb 2+ 、Sn 2+ At least one of them. X is a halogen anion including F - 、Cl - 、Br - 、I - At least one of them. P-type dopant materials include, but are not limited to, SAM (styrene-acrylonitrile-maleic anhydride) materials (e.g., 2PACz, meo-4PACz, etc.), small molecule P-type materials (e.g., cu (Tu) Cl, cu (Tu) I, etc.), and conjugated polymer materials (e.g., PPPDE, PBDB-T, etc.)。
The P-type perovskite absorber layer 20 may be prepared by a flash evaporation process in accordance with embodiments of the present utility model. Specifically, a perovskite precursor solution was prepared, 1M perovskite powder was weighed and dissolved in 1ml DMF (N, N-Dimethylformamide, N, N-Dimethylformamide) and DMSO (Dimethyl sulfoxide ) solvent, and 1mol% Meo-4PACz ([ 4- (3, 6-dimethoxy-9H-carbazol-9-yl) butyl ] phosphonic acid) powder was doped, the solvent ratio was 8:2, magnetically stirring for 30min, then placing the sample on a spin Tu Yi base, setting the spin speed to 3500rpm, the spin time to 30s, and the perovskite precursor solution amount to 120ul to coat the surface of the sample. After spin coating, placing the sample on a flash evaporation table, setting the flash evaporation time to be 30s, setting the flash evaporation temperature to be 30 ℃, carrying out annealing treatment after the flash evaporation is finished, setting the annealing temperature to be 100 ℃, setting the annealing time to be 15min, and setting the thickness to be about 500 nm.
Step five: a top passivation layer 21 is prepared. Wherein the top passivation layer 21 is propylenediamine iodine, including but not limited to at least one of propylenediamine bromine (PDADBr), butylmonoamine chloride (BACl), butylmonoamine bromide (BABr), butylamine iodide (BAI), N-dimethyl-1, 3-propylenediamine hydrochloride (DMePDADCl), dodecylenediamine bromine (DDDADBr); but may also be magnesium fluoride including, but not limited to, at least one of lithium fluoride (LiF), sodium fluoride (NaF).
Optionally, the propylenediamine iodine is evaporated onto the surface of the P-type perovskite absorption layer 20 by an evaporation method, wherein the evaporation vacuum degree is 1-5×10 -4 Pa, evaporating temperature at 50-400 deg.C, evaporating rate at 0.05-1A/S. And after evaporation, carrying out annealing operation, wherein the annealing temperature is 0-150 ℃ and the annealing time is 0-30min.
Alternatively, a passivation layer dispersion may be prepared and uniformly coated on the surface of the P-type perovskite absorption layer 20 by spin coating, and propylenediamine iodine is dissolved in an organic solvent including, but not limited to, methanol, ethanol or isopropanol, and subjected to ultrasonic dissolution and spin coating, wherein the propylenediamine iodine concentration is 0.1-6mg/ml, the ultrasonic time is 0-30min, the spin coating rotation speed is 1000-7000rpm, and the spin coating time is 20-120s. And after spin coating, carrying out annealing operation, wherein the annealing temperature is 40-160 ℃, and the annealing time is 5-40min.
Alternatively, the passivation layer dispersion may be sprayed on the surface of the P-type perovskite absorption layer 20 by a spraying method at a spraying rate of 0-100cm/s, and after the spraying is completed, an annealing operation is performed at 20-170 ℃ for 0-30min.
Embodiments of the present utility model may employ vapor deposition to fabricate the top passivation layer 21. Specifically, 3mg of propylenediamine iodine is weighed and placed in a crucible, a substrate sample wafer is placed on a mask plate and placed in a chamber of an evaporator, and the vacuum degree of evaporation is 2 multiplied by 10 -4 And (3) performing evaporation in Pa, adjusting the evaporation voltage to the evaporation temperature, controlling the evaporation rate to be 0.1A/S, evaporating the propylenediamine iodine on the layer film to a thickness of 4nm, setting the temperature of an annealing table to be 100 ℃ after the completion of evaporation, and performing annealing operation for 8 min.
Step six: an electron transport layer 22 is prepared. The electron transport layer 22 is zinc oxide (ZnO), tin dioxide (SnO) 2 ) Titanium dioxide (TiO) 2 )、[6,6]Phenyl C61 methyl butyrate (PC) 61 BM), carbon 60 (C 60 ) At least one of 2, 9-dimethyl-4, 7-diphenyl-1, 10-phenanthroline (BCP).
Alternatively, the electron transport layer 22 dispersion may be uniformly coated on the surface of the top passivation layer 21 using a spin coating method at 500 to 4000rpm for 10 to 80 seconds.
Alternatively, the electron transport layer 22 material may be evaporated onto the surface of the top passivation layer 21 by evaporation with a vacuum of 5×10 -5 -5×10 -4 Pa, evaporating temperature at 100-400 deg.C, evaporating rate at 0.05-1A/S.
Embodiments of the present utility model may employ vapor deposition to fabricate electron transport layer 22. Specifically, a substrate sample is placed on a mask plate, and is placed in a chamber of an evaporator until the vacuum degree of evaporation is 1 multiplied by 10 -4 Evaporating at Pa, adjusting evaporating voltage to evaporating temperature, controlling evaporating rate to 0.1A/S, and adding C 60 Evaporating to a thickness of 20nm on the layer film.
Step seven: buffer layer 24 is prepared. Wherein the buffer layer 24 is zinc oxide (ZnO) or tin dioxide (SnO 2 ) Titanium dioxide (TiO) 2 ) At least one of them. The thickness of the buffer layer 24 may range from 0 to 30nm。
Alternatively, the electron transport layer 22 material may be deposited onto the surface of the electron transport layer 22 using an atomic deposition apparatus with a deposition vacuum of 0-1×10 4 Pa, the temperature of the deposition pipeline is between 50 and 150 ℃, and the temperature of the deposition chamber is between 40 and 150 ℃.
Alternatively, the electron transport layer 22 modifying layer material may be evaporated onto the surface of the electron transport layer 22 by evaporation with a vacuum degree of 6×10 -5 -4×10 -4 Pa, evaporating temperature at 100-500 deg.C, evaporating rate at 0.05-1A/S.
The embodiment of the utility model can adopt an atomic deposition method, and the vacuum degree of atomic deposition equipment is set to be 0.5x10 4 Pa, the temperature of a deposition pipeline is between 60 ℃, the temperature of a deposition chamber is 70 ℃, snO is obtained 2 Evaporating to a thickness of 15nm on the layer film.
Step eight: the second transparent electrode layer 231 is prepared.
Alternatively, the transparent electrode material may be sputtered onto the surface of the electron transport layer 22 finish layer by using a magnetron sputtering method, with a power of 30-200W.
Alternatively, the transparent electrode material may be evaporated onto the surface of the electron transport layer 22 modified layer by vapor deposition with a vacuum degree of 1×10 -5 -5×10 -4 Pa, evaporating temperature at 1000-2000 deg.C, evaporating rate at 0.05-3A/S.
The embodiment of the utility model can adopt a magnetron sputtering method, and similar to the preparation method for preparing the first transparent electrode layer 121 in the second step, the power is controlled to be 50W, the running time is 1h, and the thickness of the layer film is 10nm.
Step nine: the second metal electrode layer 232 is prepared. Specifically, similar to the preparation of the first metal electrode layer 122, the mask is not uniform and has a thickness of 100nm.
Step ten: an antireflection layer 25 is prepared. Alternatively, the preparation can be performed by a magnetron sputtering method and an evaporation method. Specifically, the method for preparing the anti-reflection layer 25 according to the embodiment of the present utility model is similar to the method for preparing the top passivation layer 21, the evaporation rate is controlled to be 2 a/S, and magnesium fluoride is evaporated onto the layer film, and the thickness is 100nm. Wherein,the antireflection layer 25 is magnesium fluoride, lithium fluoride (LiF), sodium fluoride (NaF), silicon oxide (SiO) 2 ) At least one of them.
The first transparent electrode layer 121 and the second transparent electrode layer 231 are at least one of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), and zinc aluminum oxide (AZO).
The second metal electrode layer 232 is at least one of silver (Ag), gold (Au), copper (Cu), aluminum (Al), and carbon (C).
The thicknesses of the P-type perovskite absorption layer 20, the electron transport layer 22, the second transparent electrode layer 231, the second metal electrode layer 232, and the anti-reflection layer 25 range from 1 to 600nm.
In order to verify the performance of the crystalline silicon/perovskite stacked solar cell provided by the examples of the present utility model, four comparative examples were provided for demonstration. Comparative example one provides a crystalline silicon/perovskite tandem solar cell with tunneling layer 30, without hole transport layer 40; comparative example two provides a crystalline silicon/perovskite tandem solar cell without tunneling layer 30, with hole transport layer 40; comparative example three provides a crystalline silicon/perovskite tandem solar cell with tunneling layer 30, with hole transport layer 40; comparative example four provides a crystalline silicon/perovskite tandem solar cell without tunneling layer 30, without hole transport layer 40, without perovskite doping.
Referring to fig. 2, the specific structure of the crystalline silicon/perovskite stacked solar cell with the tunneling layer 30 and the hole transport layer 40 provided in the first comparative example is as follows: the substrate comprises a first metal electrode layer 122, a first transparent electrode layer 121, a P-type substrate doping layer 114, a substrate bottom passivation layer 113, a substrate 111, a substrate surface passivation layer 112, an N-type substrate doping layer 10, a tunneling layer 30, a P-type perovskite absorption layer 20, a top passivation layer 21, an electron transport layer 22, a buffer layer 24, a second transparent electrode layer 231, a second metal electrode layer 232 and an anti-reflection layer 25. The preparation method of the first comparative example is basically identical to the preparation method of the embodiment of the present utility model, and the preparation steps of the tunneling layer 30 are added between the second step and the third step of the present utility model: preparing a tunneling layer 30 on the surface of the N-type base doping layer 10; and (3) placing the sample wafer in a magnetron sputtering device after placing the sample wafer in a mask plate by using a magnetron sputtering method, controlling the power to be 60W, and controlling the running time to be 1h, wherein the thickness of the layer film is 40nm.
Referring to fig. 3, the specific structure of the crystalline silicon/perovskite stacked solar cell without the tunneling layer 30 and with the hole transport layer 40 provided in the second comparative example is as follows: the substrate comprises a first metal electrode layer 122, a first transparent electrode layer 121, a P-type substrate doping layer 114, a substrate bottom passivation layer 113, a substrate 111, a substrate surface passivation layer 112, an N-type substrate doping layer 10, a hole transport layer 40, a P-type perovskite absorption layer 20, a top passivation layer 21, an electron transport layer 22, a buffer layer 24, a second transparent electrode layer 231, a second metal electrode layer 232 and an antireflection layer 25. The preparation method of the second comparative example is basically identical to the preparation method of the embodiment of the present utility model, and the preparation steps of the hole transport layer 40 are added between the second and third steps of the present utility model: the sample wafer was treated with UV-Ozone for 15min, a dispersion of the hole transporting layer 40 was prepared by spin coating, 0.05mol of NiOx powder was weighed and dissolved in 1ml of ultra pure water, and sonicated for 20min. The hole transport layer 40 dispersion was uniformly applied to the surface of the sample, the spin-coating speed was set at 2000rpm, the spin-coating time was 40 seconds, and the solution amount was 100ul. And after spin coating, carrying out annealing operation, wherein the annealing temperature is 450 ℃, the annealing time is 30min, and the thickness is about 20nm.
Referring to fig. 4, the specific structure of the crystalline silicon/perovskite stacked solar cell with the tunneling layer 30 and the hole transport layer 40 provided in the third comparative example is as follows: the first metal electrode layer 122, the first transparent electrode layer 121, the P-type base doped layer 114, the base bottom passivation layer 113, the substrate 111, the base surface passivation layer 112, the N-type base doped layer 10, the tunneling layer 30, the hole transport layer 40, the P-type perovskite absorption layer 20, the top passivation layer 21, the electron transport layer 22, the buffer layer 24, the second transparent electrode layer 231, the second metal electrode layer 232, the anti-reflection layer 25. The preparation method of the third comparative example is basically identical to the preparation method of the embodiment of the present utility model, and the preparation steps of the tunneling layer 30 and the hole transport layer 40 are added between the second and third steps of the present utility model: preparing a tunneling layer 30 on the surface of the N-type substrate doping layer 10; placing a sample wafer in a mask plate by utilizing a magnetron sputtering method, and then placing the sample wafer in a magnetron sputtering device, wherein the power is controlled to be 60W, the running time is 1h, and the thickness of a layer film is 40nm; the sample wafer was treated with UV-Ozone for 15min, a dispersion of the hole transporting layer 40 was prepared by spin coating, 0.05mol of NiOx powder was weighed and dissolved in 1ml of ultra pure water, and sonicated for 20min. The hole transport layer 40 dispersion was uniformly applied to the surface of the sample, the spin-coating speed was set at 2000rpm, the spin-coating time was 40 seconds, and the solution amount was 100ul. After spin coating, annealing operation is performed, the annealing temperature is 450 ℃, the annealing time is 30min, and the thickness is about 20nm.
Referring to fig. 1, the specific structure of the crystalline silicon/perovskite stacked solar cell based on the non-tunneling layer 30, the non-hole transporting layer 40 and the non-perovskite doping provided in the fourth comparative example is the same as that provided in the embodiment of the present utility model, and the intrinsic non-doped perovskite is used instead in the third step: preparing perovskite precursor liquid by a flash evaporation method, weighing 1M perovskite powder, and dissolving in 1ml DMF and DMSO solvent, wherein the solvent ratio is 8:2, magnetically stirring for 30min, then placing the sample on a spin Tu Yi base, setting the spin speed to 3500rpm, the spin time to 30s, the perovskite precursor solution amount to 120ul, coating the surface of the sample, placing the sample on a flash evaporation table after spin coating, setting the flash evaporation time to 30s, the flash evaporation temperature to 30 ℃, carrying out annealing treatment after flash evaporation, setting the annealing temperature to 100 ℃, the annealing time to 15min, and the thickness to about 500 nm.
The comparative experiments of the present utility model were conducted with one to four comparative examples, and a standard solar light intensity calibration was conducted using a solar simulator, and the area was 1.0cm 2 The example device of (2) was subjected to an IV test for a long period of time, with an initial voltage of 1.95V, a cut-off voltage of 0V, and a range of 100mA, and the test results are shown in the following table.
From the comparison of the above tables, it can be seen that:
1. in the embodiment of the utility model, the doped P-type perovskite is used, and compared with the comparative example IV using the intrinsic perovskite, the embodiment of the utility model has high photoelectric conversion efficiency of 31.25% under the same device structure without the tunneling layer 30 and without the hole transport layer 40. And the fourth comparative example cannot work normally, and the photoelectric conversion efficiency is as low as 15.23%.
2. The doped P-type perovskite used in the embodiments of the present utility model may produce good contact conduction with the N-type base doped layer 10. In comparative example two, nickel oxide was used as the hole transport layer 40, and the film layer thereof was not in good contact with the N-type base doping layer 10, so that the device could not operate efficiently without the tunneling layer 30, and the photoelectric conversion efficiency was as low as 21.11%.
3. The embodiment of the present utility model reduces the optical loss of the device because the tunneling layer 30 and the hole transport layer 40 are removed, and thus has higher short-circuit current and photoelectric conversion efficiency compared to the comparative examples one and three, which operate normally.
4. The embodiment of the utility model reduces the instability caused by the two film layers because the tunneling layer 30 and the hole transport layer 40 are removed. The inventive examples have a decay rate as low as 0.2%, which is much lower than the comparative examples one to four.
5. Compared with the first to third comparative examples, the embodiment of the utility model has simpler procedures, lower manufacturing cost and more suitability for large-scale commercial application.
The above description is illustrative of the various embodiments of the utility model and is not intended to be limiting, but is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model.

Claims (10)

1. A crystalline silicon/perovskite stacked solar cell characterized by: the solar cell comprises a crystalline silicon cell and a perovskite cell positioned above the crystalline silicon cell, wherein an N-type substrate doping layer is arranged at the top of the crystalline silicon cell, a P-type perovskite absorbing layer is arranged at the bottom of the perovskite cell, and the surface of the N-type substrate doping layer is attached to the bottom surface of the P-type perovskite absorbing layer.
2. The crystalline silicon/perovskite stacked solar cell of claim 1, wherein: the crystalline silicon cell comprises a substrate layer, the N-type substrate doping layer and a substrate electrode layer; the N-type substrate doping layer is arranged on the surface of the substrate layer, and the substrate electrode layer is arranged on the bottom surface of the substrate layer.
3. The crystalline silicon/perovskite stacked solar cell as defined in claim 2 wherein: the base layer comprises a substrate, a base surface passivation layer arranged on the surface of the substrate, a base bottom passivation layer arranged on the bottom surface of the substrate and a P-type base doping layer arranged on the bottom surface of the base bottom passivation layer; the N-type substrate doping layer is arranged on the surface of the passivation layer on the substrate surface, and the substrate electrode layer is arranged on the bottom surface of the P-type substrate doping layer.
4. A crystalline silicon/perovskite stacked solar cell as claimed in claim 3 wherein: the substrate electrode layer comprises a first transparent electrode layer arranged on the bottom surface of the P-type substrate doping layer and a first metal electrode layer arranged on the bottom surface of the first transparent electrode layer.
5. The crystalline silicon/perovskite stacked solar cell of claim 1, wherein: the perovskite battery comprises the P-type perovskite absorption layer, a top passivation layer arranged on the surface of the P-type perovskite absorption layer, an electron transport layer arranged on the surface of the top passivation layer and a top electrode layer arranged on the surface of the electron transport layer.
6. The crystalline silicon/perovskite stacked solar cell of claim 5, wherein: the top electrode layer comprises a second transparent electrode layer arranged on the surface of the electron transport layer and a second metal electrode layer arranged on the surface of the second transparent electrode layer.
7. The crystalline silicon/perovskite stacked solar cell of claim 5, wherein: the perovskite battery also includes a buffer layer disposed between the electron transport layer and the top electrode layer.
8. The crystalline silicon/perovskite stacked solar cell of claim 7, wherein: the thickness of the buffer layer ranges from 1nm to 30nm.
9. The crystalline silicon/perovskite stacked solar cell of claim 5, wherein: the perovskite battery also includes an anti-reflection layer disposed on a surface of the top electrode layer.
10. The crystalline silicon/perovskite stacked solar cell according to any one of claims 1 to 9, wherein: the crystalline silicon battery is connected with the perovskite battery in series.
CN202321683194.0U 2023-06-29 2023-06-29 Crystalline silicon/perovskite laminated solar cell Active CN220023501U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117500294A (en) * 2023-12-29 2024-02-02 临沂力诚新能源有限公司 Perovskite crystalline silicon HJT laminated battery

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117500294A (en) * 2023-12-29 2024-02-02 临沂力诚新能源有限公司 Perovskite crystalline silicon HJT laminated battery
CN117500294B (en) * 2023-12-29 2024-03-26 临沂力诚新能源有限公司 Perovskite crystalline silicon HJT laminated battery

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