CN219999390U - Broadband carrier module detects frock - Google Patents

Abstract

The utility model discloses a broadband carrier module detection tool which comprises a target board to be detected, a display panel, a communication test auxiliary transponder, a fixed attenuator and a tool main board, wherein the communication test auxiliary transponder is connected with the fixed attenuator through a shielding wire, the fixed attenuator is connected with the target board to be detected through the shielding wire, the tool main board is connected with the target board to be detected, the tool main board is also connected with the display panel and performs data interaction with the display panel, the signal output of the tool main board is connected with a tool logo output serial port, the voltage output of the target board to be detected is connected with a discharge relay, and the control signal output of the tool main board is connected with the discharge relay and controls the discharge relay to work. The utility model has the beneficial effects that the disassembly and assembly are convenient, the residual electric quantity is ensured not to exist before and after the test of the target board to be tested, and the tested module is protected; the test can be carried out one-to-many, and the yield is improved.

Description

Broadband carrier module detects frock

Technical Field

The utility model relates to the technical field of PCB detection, in particular to a broadband carrier module detection tool.

Background

At present, a plurality of detection tools for broadband carrier modules in the market adopt a full-welding process to fix probes between a tool plate and a module to be detected, and the mode is time-consuming and labor-consuming in disassembly and assembly, and in addition, a plurality of detection tools are only burnt or only tested, the test content is not comprehensive enough, the speed is low, one-to-many testing cannot be performed, the fault condition of the abnormal module to be detected cannot be simply and timely positioned, and particularly, the module with the super capacitor is not strict in testing, and the risk that the residual electric quantity damages the module to be detected exists.

Disclosure of Invention

The utility model aims to solve the problems and designs a broadband carrier module detection tool.

The technical scheme includes that the broadband carrier module detection tool comprises a target board to be tested, a display panel, a communication test auxiliary transponder, a fixed attenuator and a tool main board, and is characterized in that the communication test auxiliary transponder is connected with the fixed attenuator through a shielding wire, the fixed attenuator is connected with the target board to be tested through the shielding wire, the tool main board is connected with the target board to be tested and performs data interaction with the target board to be tested, the tool main board is also connected with the display panel and performs data interaction with the display panel, a signal output of the tool main board is connected with a tool logo output serial port, a voltage output of the target board to be tested is connected with a discharge relay, and a control signal output of the tool main board is connected with the discharge relay and controls the discharge relay to work.

The tool main board is connected with the target board to be tested through a debug serial port, a control and status interface, an SPI interface, an IO interface, a serial port and a power control interface respectively, and performs data interaction.

The target board to be tested comprises a single-phase module, a three-phase module and a CCO module.

And the discharge relay starts discharging when the voltage output by the target plate to be tested is more than 0.3v and less than 12 v.

And the target plate to be tested is subjected to program burning before testing.

Advantageous effects

The broadband carrier module detection tool manufactured by the technical scheme of the utility model has the following advantages:

each part adopts a detachable structural design and fool-proof treatment, thereby being convenient for maintenance and replacement; the display panel adopts LEDs to indicate different states of the target board to be tested, so that whether the module to be tested is qualified or has a certain fault can be conveniently distinguished, and the inspection of products is convenient in a workshop; the introduction of the discharge relay can ensure that no residual electric quantity exists before and after the tested module is tested, and the module is not damaged due to residual voltage in the subsequent carrying and assembling processes; the logo output serial port can accurately position fault points of the target board to be detected and provide technical support for maintaining the target board to be detected; the auxiliary transponder can test in one-to-many mode, so that the test time is not increased, the use quantity of auxiliary equipment can be reduced, and the yield is improved; the attenuator can test the broadband carrier communication performance of the tested module, and the carrier performance meets the index requirement through the qualified product of the detection tool.

Drawings

Fig. 1 is a schematic structural diagram of a wideband carrier module detection tool according to the present utility model;

in the figure, 1, a target plate to be tested; 2. a display panel; 3. a communication test auxiliary transponder; 4. a fixed attenuator; 5. a tooling main board; 6. a discharge relay; 7. debug serial port; 8. a control and status interface; 9. SPI interface; 10. an IO interface; 11. a serial port; 12. a power control interface; 13. and (5) logo output serial ports.

Detailed Description

The present utility model will be described in detail with reference to the accompanying drawings, as shown in fig. 1;

the technical scheme of the utility model is characterized in that the communication test auxiliary transponder is connected with the fixed attenuator through a shielding wire, the fixed attenuator is connected with the target board to be tested through the shielding wire, the tool main board is connected with the target board to be tested and performs data interaction with the target board to be tested, the tool main board is also connected with the display panel and performs data interaction with the display panel, the signal output of the tool main board is connected with the tool logo output serial port 13, the voltage output of the target board to be tested is connected with the discharge relay 6, and the control signal output of the tool main board is connected with the discharge relay and controls the discharge relay to work.

The tool main board is connected with the target board to be tested through the debug serial port 7, the control and status interface 8, the SPI interface 9, the IO interface 10, the serial port 11 and the power control interface 12 respectively and performs data interaction, and the target board to be tested comprises a single-phase module, a three-phase module and a CCO module.

The discharge control process of the discharge relay is as follows:

1) Sampling the super capacitor voltage output by the target board to be tested;

2) Judging the voltage by the tool main board, and if the voltage is more than 0.3v and less than 12v, starting discharging;

3) In the discharging process, continuously sampling the voltage of the super capacitor, taking 100ms sampling once into consideration, and confirming that the corresponding steps are finished if the sampling results of three continuous times meet the requirements;

4) The overtime time of the discharge is 3 seconds, and if the discharge can not reach below the target voltage within 3 seconds, the discharge is considered to be failed;

5) Discharging the voltage to below 0.3v, ending the discharging process, and closing the discharging relay;

6) If the sampling voltage is greater than 1.2v, directly ending the test flow, prompting error, and requiring manual intervention discharge;

7) The time for starting the discharge is at least 800ms, namely at least 800ms as long as the voltage is sampled to be in the discharge voltage range;

the super capacitor discharge voltage in the process is high and low, and parameter setting needs to be supported.

The target board to be tested is subjected to program burning before testing, the program burning adopts Efuse operation, the purpose of the Efuse operation is to write a specific SN number (Efuse content) into a chip, if the chip is already written, the step is skipped, and the Efuse writing operation needs to be self-checked, namely the correctness of a writing result needs to be checked. The method comprises the following specific steps:

1) Releasing an Rst pin, enabling the chip to start an internal guide program, and simultaneously keeping the SPI signal of the tool main board in an input high-resistance state;

2) Executing an Efuse reading operation through the debug serial port, and normally exiting the Efuse operation if the Efuse is valid;

3) If Efuse is invalid, exiting abnormally;

4) If the Efuse is empty, writing the calculated Efuse information according to the internal parameters of the tool;

5) Repeating the reading of Efuse information, repeating the attempt for 3 times if the Efuse information is inconsistent, and repeating the reading for at least 2 times if the Efuse information is consistent;

note that: if the module has a program, the APP can be started after the module is booted, and the tooling needs to ensure normal operation of the Efuse.

The program burning is to burn the content of the program storage Flash, namely a program file. The method comprises the following specific steps:

1) Pulling down the Rst pin again to enable the main chip to be in a reset state;

2) Pulling down the GPIO0 of the main chip, namely, the internal and external selection signals in Flash (only needed when CCO is burnt);

3) Initializing a tooling main board and starting an SPI interface;

4) Confirming Flash availability through an SPI interface;

5) Reading the Flash UID through the SPI interface, and repeating the reading for 3 times, and judging successfully without distinction;

6) Writing a program file into Flash through SPI, wherein each page writing operation needs read-back verification;

7) Generating a key through calculation of the SN number and the Flash UID;

8) Writing the secret key into a specific area of Flash, wherein the writing requires readback verification;

9) After the burning and registering are completed, closing SPI and setting each IO to be in a high-resistance state;

10 Releasing GPIO0, i.e., flash select signal (needed only for CCO burn);

11 Finally releasing the Rst pin.

After the programming is completed, the module can naturally guide the program and start, and the tool enters a testing stage, so that the testing state can be clearly judged by the module for simplifying, and the testing control instruction of the production tool is increased, specifically as follows:

1) For a single three-phase module, the matching process is: waiting for address matching messages at 2400bps baud rate at a service serial port, and finishing address matching operation, wherein the matched address is the current SN number, and the timeout time is 5 seconds (the longest time for boot guidance is required to be confirmed); the matching process comprises 645 address matching and 698 address matching, which are supported simultaneously;

2) For a CCO module, the matching process is: waiting for a CCO power-on report message at 9600bps baud rate at a service serial port, and overtime time is 5 seconds;

3) After the matching is completed, initiating a production tool test enabling instruction to the module, and replying confirmation by the module;

4) Executing various item tests, including frequency offset, weak current interface, HPLC communication and the like;

5) After the test is completed, initiating a production tool test function closing instruction to the module, replying confirmation to the module, and executing a normal work flow by the module;

6) Starting a discharge flow of the super capacitor;

7) And ending the test after the discharge is completed.

After the programming is completed, the module can naturally guide the program and start, the tool enters a testing stage, and the first link is frequency offset testing. The method comprises the following specific steps:

1) After entering a test mode, the tool main board sets a frequency counting pin as input, initiates a 1MHz clock output enabling instruction to a module, and the module needs to respond immediately;

2) Starting a counting timer with an 8MHz clock as a reference by a tool main board, starting to calculate the number of pulses input in 50ms at 1MHz, repeatedly calculating 40 times, and taking an average value to calculate a deviation value; after the calculation is completed, the timer and the counter are closed;

3) The tool main board initiates a 1MHz clock output closing instruction to the module, and the module needs to respond immediately;

4) Judging the frequency offset value by the tool main board, if the absolute value of the deviation exceeds 10ppm, considering that the equipment to be tested is abnormal, and needing maintenance intervention, wherein the frequency offset threshold can be set;

5) If the deviation value is smaller than 10ppm, an SFO writing instruction is sent to the module, the module needs to respond immediately, and SFO information is written into a Flash corresponding area; the write operation requires a read-back acknowledgement, i.e., an SFO read instruction.

After the frequency offset calibration is completed, a weak current interface test is started, and the specific steps are as follows:

1) The weak current interface of the module is divided into an input interface and an output interface, the input interface is tested in a mode of inputting and reading by the tool output module, and the output interface is tested in a mode of outputting the tool by the module;

2) For the module input interfaces, the tooling main board sets the voltage of each weak current IO port in a one-to-one correspondence, wherein the voltage comprises SET, EVO, reset, plugIn (CCO is Reset only), and the specific setting mode is that the target IO is set to be a preset level, and other IOs are set to be the inverse of the preset level;

3) The tool sends a pin IO level reading instruction to the module, the module returns to the current IO level by the pin IO level response, and the module needs to set IO back to a normal state after completing the response;

4) The tool judges whether the current IO level return value accords with the expectation or not, and if not, the tool exits abnormally;

5) For the module output interfaces, the tool directly reads the level of the corresponding IO, then sends a corresponding IO output level overturning instruction, and sets the level of all the module input interfaces IO to be the same level of the current IO reading result;

6) The tooling reads the corresponding IO level again, compares the level result with the level result before overturning, and if the level result is inconsistent, the tooling is correct, and simultaneously sends a level recovery instruction of the corresponding IO;

7) After the level test is finished, all pins of the tool which participate in the IO test are set as floating input;

note that: the Reset pin is implemented as a soft Reset and thus can be tested in an IO fashion.

The HPLC communication test needs external auxiliary tools to cooperate, and according to the design thought, the tool main board only needs to send a test instruction to the module and periodically read the result. The method comprises the following specific steps:

1) The tooling mainboard sends tooling HPLC communication test enabling instructions to the module, and the module replies confirmation;

2) The tool mainboard periodically sends a tool HPLC communication test state reading instruction to the module, and the module replies a tool HPLC communication test state response;

3) According to the period and the overtime total time, the maximum repeated reading times can be calculated;

4) Within the total frequency limit, the module returns to the test state to be successful, the test is normally exited, and otherwise, the test is abnormally exited;

regardless of the exit, the tool HPLC communication test shutdown command needs to be sent, and the module replies to the confirmation.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation. The term "comprising" an element defined by the term "comprising" does not exclude the presence of other identical elements in a process, method, article or apparatus that comprises the element.

The above technical solution only represents the preferred technical solution of the present utility model, and some changes that may be made by those skilled in the art to some parts of the technical solution represent the principles of the present utility model, and the technical solution falls within the scope of the present utility model.

Claims (5)

1. The utility model provides a broadband carrier module detects frock, includes target board (1) to be tested, display panel (2), communication test auxiliary transponder (3) and fixed attenuator (4) and frock mainboard (5), its characterized in that, communication test auxiliary transponder pass through the shielded wire with fixed attenuator is connected, fixed attenuator pass through the shielded wire with target board to be tested is connected, the frock mainboard with target board to be tested is connected and with target board to be tested carries out data interaction, the frock mainboard still with display panel is connected and carry out data interaction with display panel, frock logo output serial ports (13) are connected to the signal output of frock mainboard, discharge relay (6) are connected to the voltage output of target board to be tested, the control signal output of frock mainboard is connected discharge relay and control discharge relay work.

2. The broadband carrier module detection tool according to claim 1, wherein the tool main board is connected with the target board to be tested through a debug serial port (7), a control and status interface (8), an SPI interface (9), a serial port (10), an IO interface (11) and a power control interface (12) respectively, and performs data interaction.

3. The broadband carrier module detection tool according to claim 1, wherein the target board to be tested comprises a single-phase module, a three-phase module and a CCO module.

4. The broadband carrier module detection tool according to claim 1, wherein the discharge relay starts discharge when the voltage output by the target board to be tested is greater than 0.3v and less than 12 v.

5. The broadband carrier module detection tool according to claim 1, wherein the target board to be tested is programmed before testing.