CN219999349U - Buffer circuit of PWM driving signal - Google Patents
Buffer circuit of PWM driving signal Download PDFInfo
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- CN219999349U CN219999349U CN202321701313.0U CN202321701313U CN219999349U CN 219999349 U CN219999349 U CN 219999349U CN 202321701313 U CN202321701313 U CN 202321701313U CN 219999349 U CN219999349 U CN 219999349U
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Abstract
The utility model discloses a buffer circuit of a PWM driving signal, which comprises an enabling signal processing circuit and a buffer chip; the input end of the enabling signal processing circuit is connected with the control pin of the front-stage MCU, and the output end of the enabling signal processing circuit is connected with the enabling pin of the buffer chip; the pulse input end of the buffer chip is connected with the output end of the MCU; the pulse output end of the pulse chip is connected with the input of the isolation amplifying circuit, and the output of the isolation amplifying circuit is connected with the power switch device. The utility model realizes the functions of immediately turning off and time-delay turning on hardware by using a simple additional circuit, and after the buffer circuit is added, one IGBT can be ensured to be turned on after being completely turned off, the phenomenon of straight-through of an upper pipe and a lower pipe is avoided, the function of protecting a power switch device is achieved, and the working reliability of a system is improved.
Description
Technical Field
The utility model relates to the technical field of PWM control, in particular to a buffer circuit of PWM driving signals.
Background
The drive circuit in the existing PWM control technology usually adopts a multichannel buffer chip to realize the isolation and voltage conversion of pulse signals and provide drive power, thereby realizing the reliable drive of power switching devices in circuits with upper and lower bridge arms of a switching tube. However, the drive circuit using such a multichannel buffer chip generally does not have a function of preventing the upper and lower arm switching tubes from being directly connected. ( Bridge arm direct connection means that two power electronic switching devices connected in series are conducted simultaneously, and if voltages exist at two ends, a direct current power supply is short-circuited, and bridge arm power devices are damaged. The upper bridge arm and the lower bridge arm are directly connected with two switch tubes on the same side. )
As shown in fig. 1, a conventional PWM driving circuit is characterized in that a MCU main control chip generates PWM pulse signals, level conversion and power amplification are realized through a buffer chip (such as 54ALS 244), gate electrode switching signals of power switching devices are generated through an isolation amplifying circuit, and power switching devices in circuits with upper and lower bridge arms of a switching tube are driven to act, so that inversion output is realized.
Disclosure of Invention
The utility model aims to solve the technical problem that the buffer circuit for the PWM driving signal has the functions of immediately turning off and delaying on while buffering the driving signal through a simple additional circuit and prevents the upper and lower switching tubes from being directly connected.
The object of the utility model is achieved in the following way:
a buffer circuit of a PWM driving signal, the buffer circuit including an enable signal processing circuit and a buffer chip; the input end of the enabling signal processing circuit is connected with the control pin of the front-stage MCU, and the output end of the enabling signal processing circuit is connected with the enabling pin of the buffer chip; the pulse input end of the buffer chip is connected with the output end of the MCU, the pulse output end of the buffer chip is connected with the input end of the isolation amplifying circuit, and the output end of the isolation amplifying circuit is connected with the power switch device.
The enabling signal processing circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, a third diode D3 and a capacitor C1; the power supply is characterized in that one end of the first resistor R1 is connected with the positive electrode of the power supply, the other end of the first resistor R1 is a STOP pin, the STOP pin is respectively connected with a control pin of the front-stage MCU, one end of the second resistor R2 and the anode of the second diode D2, the other end of the second resistor R2 is connected with the anode of the first diode D1, the cathode of the first diode D1 is an A point, the A point is respectively connected with the anode of the third diode D3 and one end of the capacitor C1, the other end of the capacitor C1 is connected with the third resistor R3, the cathodes of the third resistor R3 and the third diode D3 are both connected with the cathode of the second diode D2, the cathode of the second diode D2 is a B point, and the B point is also connected with an enabling pin of the buffer chip.
The buffer chip is 54ALS244C.
The isolation amplifying circuit adopts a HCPL-3120 driving chip.
The utility model has the beneficial effects that: the utility model has high reliability: the power switch device has the advantages that the immediate turn-off and time-delay turn-on functions on hardware are realized through a simple additional circuit, the function of protecting the power switch device is achieved, and the working reliability of the system is improved. The cost is low; the novel circuit is simple (only few resistance-capacitance components and diodes are added), the additional cost is very low, the protection function is reliable, the phenomenon of straight-through of the upper and lower tubes in the moment of PWM enabling output can be effectively prevented, and the power device is protected from overcurrent damage.
Drawings
Fig. 1 is a conventional PWM driving circuit in the prior art.
Fig. 2 is a PWM driving circuit including an enable signal processing circuit and a buffer chip in the present utility model.
Fig. 3 is a schematic circuit diagram of a snubber circuit of the present utility model.
Detailed Description
The utility model will be described in further detail with reference to the drawings and the detailed description.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the utility model. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs.
In the present utility model, terms such as "fixedly attached," "connected," "coupled," and the like are to be construed broadly and refer to either a fixed connection or an integral or removable connection; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the terms in the present utility model can be determined according to circumstances by a person skilled in the relevant art or the art, and is not to be construed as limiting the present utility model.
As shown in fig. 2, an input end of the buffer circuit is connected with an output end of the MCU, an output end of the buffer circuit is connected with the drive circuit, and the buffer circuit comprises an enable signal processing circuit and a buffer chip; the input end of the enabling signal processing circuit is connected with the control pin of the front-stage MCU, and the output end of the enabling signal processing circuit is connected with the enabling pin of the buffer chip; the pulse input end of the buffer chip is connected with the output end of the MCU, the buffer output end of the buffer chip is connected with the input end of the isolation amplifying circuit, and the output end of the isolation amplifying circuit is connected with the power switch device.
As shown in fig. 3, the enable signal processing circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, a third diode D3, and a capacitor C1; the power supply is characterized in that one end of the first resistor R1 is connected with the positive electrode of the power supply, the other end of the first resistor R1 is a STOP pin, the STOP pin is respectively connected with a control pin of the front-stage MCU, one end of the second resistor R2 and the anode of the second diode D2, the other end of the second resistor R2 is connected with the anode of the first diode D1, the cathode of the first diode D1 is an A point, the A point is respectively connected with the anode of the third diode D3 and one end of the capacitor C1, the other end of the capacitor C1 is connected with the third resistor R3, the cathodes of the third resistor R3 and the third diode D3 are both connected with the cathode of the second diode D2, the cathode of the second diode D2 is a B point, and the B point is also connected with an enabling pin of the buffer chip.
The buffer chip is 54ALS244C.
The isolation amplifying circuit adopts a HCPL-3120 driving chip.
The power switch device is a power switch in a circuit with upper and lower bridge arms of a switch tube; the circuit with the upper bridge arm and the lower bridge arm of the switching tube comprises a three-phase bridge type full-control inversion or rectification circuit.
The working principle of the PWM driving circuit provided by the utility model is as follows: each pin of the buffer chip (taking 54ALS244C as an example) is normally connected with input and output pulse signals, P1-P6 are 6-path PWM pulse input signals, PWM1-PWM6 are 6-path PWM pulse output signals, and the chip mainly plays a role in signal isolation. +5V and DGND are power supply pins of the chip and are connected with +5V power supply. Enable244C is the enable pin of the chip, active low.
The STOP node is connected with a control pin of the front-stage MCU and is connected to an enable pin enable244C of the buffer chip after passing through an enable signal processing circuit. The enabling signal processing circuit mainly comprises a plurality of resistors, diodes and capacitors, is shown as an effective, simple and efficient combination mode through experiments, and can be adjusted according to practical application environments.
A specific functional implementation flow of the enable signal processing circuit will now be described. When STOP is connected with a high-level signal, +5V voltage is input to an enable244C pin through a first resistor R1 and a second diode D2, and the buffer chip turns off output; meanwhile, the +5V voltage charges the capacitor C1 through the first resistor R1, the second resistor R2 and the first diode D1, and the voltage at the point A is approximately +5V after the circuit is stabilized. At this time, when STOP inputs the low level signal, if there is no processing circuit, the low level will directly act on the enable244C pin, enabling the buffer chip to output; however, due to the presence of the enable signal processing circuit, the voltage at the point a does not drop to approximately 0v due to the presence of the capacitor, and the voltage at the point b is equal to the voltage at the point a, so that the buffer chip is not enabled to be turned on immediately. Along with the voltage drop to the low level recognition threshold range of the buffer chip after the capacitor C1 discharges for a period of time through the third resistor R3, the buffer chip can be enabled to output, so that the effects of immediately closing and delaying opening are achieved, one IGBT is ensured to be completely closed, the other IGBT is further opened, and the situation that a PWM signal generated by an MCU is directly connected with an upper pipe and a lower pipe possibly existing in the enabling moment is avoided.
The utility model has the following advantages:
1. the reliability is high: the function of immediately turning off and delaying on the hardware is realized by a simple additional circuit, the function of protecting a power switch device is achieved, and the working reliability of the system is improved; the conventional driving signal is a circuit that is turned off immediately and turned on immediately, and the IGBT that executes the turn-off instruction is not turned off immediately due to the presence of the tailing effect, but has a turn-off process lasting several tens or even hundreds of nanoseconds. If the IGBT executing the turn-on instruction is turned on immediately at this time, the situation that the upper and lower tubes are turned on simultaneously in a short time exists, and the IGBT is damaged by instant overcurrent. After the buffer circuit is added, one IGBT can be ensured to be turned on after being completely turned off, and the phenomenon of straight-through of an upper pipe and a lower pipe is avoided.
2. The cost is low: as can be seen from the figure, the circuit of the utility model is simple (only few resistance-capacitance components and diodes are added), the additional cost is small, the protection function is reliable (the phenomenon of direct connection of the upper tube and the lower tube at the moment of PWM enabling output can be effectively prevented, and the power device can not be damaged by overcurrent).
The circuit with the upper bridge arm and the lower bridge arm of the switching tube comprises a three-phase bridge type full-control inversion or rectification circuit.
While the foregoing description of the embodiments of the present utility model has been presented in conjunction with the drawings, it should be understood that it is not intended to limit the scope of the utility model, but rather, it is intended to cover all modifications or variations within the scope of the utility model as defined by the claims of the present utility model.
Claims (4)
1. A buffer circuit for PWM drive signals, characterized in that: the buffer circuit comprises an enabling signal processing circuit and a buffer chip; the input end of the enabling signal processing circuit is connected with the control pin of the front-stage MCU, and the output end of the enabling signal processing circuit is connected with the enabling pin of the buffer chip; the pulse input end of the buffer chip is connected with the output end of the MCU; the pulse output end of the buffer chip is connected with the input of the isolation amplifying circuit, and the output of the isolation amplifying circuit is connected with the power switch device.
2. The buffer circuit for PWM drive signals according to claim 1, wherein: the enabling signal processing circuit comprises a first resistor (R1), a second resistor (R2), a third resistor (R3), a first diode (D1), a second diode (D2), a third diode (D3) and a capacitor (C1); the power supply is characterized in that one end of the first resistor (R1) is connected with a power supply anode, the other end of the first resistor (R1) is a STOP pin, the STOP pin is respectively connected with a control pin of the front-stage MCU, one end of the second resistor (R2) and an anode of the second diode (D2), the other end of the second resistor (R2) is connected with the anode of the first diode (D1), the cathode of the first diode (D1) is an A point, the A point is respectively connected with the anode of the third diode (D3) and one end of the capacitor (C1), the other end of the capacitor (C1) is connected with the third resistor (R3), the cathodes of the third resistor (R3) and the third diode (D3) are both connected with the cathode of the second diode (D2), the cathode of the second diode (D2) is a B point, and the B point is also connected with an enabling pin of the buffer chip.
3. The buffer circuit for PWM drive signals according to claim 1, wherein: the buffer chip is 54ALS244C.
4. The buffer circuit for PWM drive signals according to claim 1, wherein: the isolation amplifying circuit adopts a HCPL-3120 driving chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321701313.0U CN219999349U (en) | 2023-06-30 | 2023-06-30 | Buffer circuit of PWM driving signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321701313.0U CN219999349U (en) | 2023-06-30 | 2023-06-30 | Buffer circuit of PWM driving signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219999349U true CN219999349U (en) | 2023-11-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321701313.0U Active CN219999349U (en) | 2023-06-30 | 2023-06-30 | Buffer circuit of PWM driving signal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219999349U (en) |
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2023
- 2023-06-30 CN CN202321701313.0U patent/CN219999349U/en active Active
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Effective date of registration: 20240724 Address after: No. 311, Science Avenue, High-tech Zone, Zhengzhou City, Henan Province, 450000 Patentee after: China Shipbuilding Haiwei High tech Co.,Ltd. Country or region after: China Patentee after: 713rd Research Institute of China Shipbuilding Corp.,Ltd. Address before: 450000 No. 126, Jingguang Middle Road, Erqi District, Zhengzhou City, Henan Province Patentee before: 713rd Research Institute of China Shipbuilding Corp.,Ltd. Country or region before: China |
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| TR01 | Transfer of patent right |