CN219998219U - Wafer packaging body capable of preventing aluminum crystal pad of chip from being damaged in probe detection operation - Google Patents
Wafer packaging body capable of preventing aluminum crystal pad of chip from being damaged in probe detection operation Download PDFInfo
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- CN219998219U CN219998219U CN202320642745.2U CN202320642745U CN219998219U CN 219998219 U CN219998219 U CN 219998219U CN 202320642745 U CN202320642745 U CN 202320642745U CN 219998219 U CN219998219 U CN 219998219U
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- Prior art keywords
- chip
- layer
- pad
- aluminum
- wafer
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- 229910052782 aluminium Inorganic materials 0.000 title claims abstract description 60
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title claims abstract description 60
- 239000000523 sample Substances 0.000 title claims abstract description 33
- 239000013078 crystal Substances 0.000 title claims abstract description 11
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 11
- 238000001514 detection method Methods 0.000 title claims abstract description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000010931 gold Substances 0.000 claims abstract description 25
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 17
- 229910052737 gold Inorganic materials 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 9
- 238000007772 electroless plating Methods 0.000 claims abstract description 7
- 238000005516 engineering process Methods 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 59
- 238000007689 inspection Methods 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 8
- 238000002161 passivation Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The utility model discloses a wafer packaging body for preventing an aluminum crystal pad of a chip from being damaged in probe detection operation, which is characterized in that before a plurality of chips in the wafer packaging body carry out probe detection operation, at least one bump is formed on the surface of at least one aluminum crystal pad of each chip in the wafer packaging body by utilizing an electroless plating technology, each bump is a metal stacked structure formed by stacking a nickel layer and a gold layer or a nickel layer, a palladium layer and a gold layer on each aluminum crystal pad and having a certain thickness, so that the structural strength of each aluminum crystal pad of each chip is improved to avoid damage in probe detection operation, and the quality and reliability of each chip in subsequent operation such as wire bonding operation are improved.
Description
Technical Field
The present utility model relates to a wafer package, and more particularly, to a wafer package in which at least one Bump (Bump) is disposed on at least one aluminum Pad (Die Pad) of each chip before each chip (Die) performs a probe inspection operation, so as to prevent the surface of the aluminum Pad of the chip from being damaged during the probe inspection operation.
Background
In the semiconductor industry, after the Wafer (Wafer) is manufactured, a probe inspection operation is generally performed before a subsequent operation such as a redistribution line (RDL, redistribution Layer) is performed, wherein probes are abutted against aluminum pads (Die pads) of dies (Die) on the Wafer to generate electrical connection for testing. The embodiment shown in fig. 8 is a conventional wafer 5, and a surface 5a of the conventional wafer 5 includes a plurality of chips 5b, and at least one aluminum pad 5c and at least one protection layer (Passivation) 5d are disposed on each chip 5 b; when the existing wafer 5 is subjected to probe detection operation, at least one probe 3 is utilized to generate electrical connection on each aluminum wafer pad 5c of each chip 5b on the existing wafer 5 for testing, and electrical signals are transmitted back to a related testing machine for analysis and discrimination of functions, characteristics or conditions of each chip 5b so as to screen out defective products; the conventional wafer 5 is divided into a plurality of chip package units 5e after the probe inspection is completed, and each chip package unit 5e is used for performing operations such as wire bonding or other soldering operations, for example, but not limited to, as shown in fig. 10, a first bonding pad 4a is formed on each aluminum die pad 5c by a bonding wire 4, and a second bonding pad 4b is formed on an external electronic component 2, so that each chip package unit 5e is electrically connected with the electronic component 2. However, when the probes 3 (as shown in fig. 8) in the probe inspection process generate electrical connection on the aluminum pads 5c of the chips 5b pressed against the conventional wafer 5 for testing, the positive pressure (as shown by arrow N in fig. 8) generated by the probes 3 (as shown in fig. 8) pressing against the aluminum pads 5c in the testing process leaves concave holes 5f (as shown in fig. 9 and 10) on the surface of the aluminum pads 5c which are relatively soft metal, which affects the quality and reliability of the subsequent processes such as wire bonding or other soldering processes of the chips, and is unfavorable for the market competitiveness of the product.
Therefore, a wafer package that avoids the damage of the aluminum pads of the chip during the probe inspection operation is highly desired in the related industry.
Disclosure of Invention
The present utility model provides a wafer package for preventing the aluminum pads of chips from being damaged during the probe inspection operation, wherein before the plurality of chips in the wafer package are subjected to the probe inspection operation, at least one bump is formed on the surface of at least one aluminum pad of each chip in the wafer package by using the electroless plating technique, and each bump is a metal stacked structure formed by stacking a nickel layer and a gold layer or a nickel layer, a palladium layer and a gold layer on each aluminum pad, so as to improve the structural strength of each aluminum pad of each chip to avoid damage during the probe inspection operation, and effectively solve the problem that the probes in the probe inspection operation leave concave holes on at least one aluminum pad of the plurality of chips in the existing wafer.
In order to achieve the above-mentioned objective, the present utility model provides a wafer package for preventing an aluminum pad of a chip from being damaged during a probe inspection operation, the wafer package comprises a plurality of chips (Die), at least one dielectric layer and a plurality of bumps (Bump); wherein the chips are arranged on one surface of the wafer package in an array manner, and each chip is provided with at least one aluminum Die Pad (Die Pad) and at least one protection layer (passage); the at least one dielectric layer is arranged on the surface of the wafer package body, the at least one dielectric layer is provided with at least one opening corresponding to the at least one aluminum crystal pad of the chips, and the at least one aluminum crystal pad is electrically connected outwards from the at least one opening; the bumps are formed in the at least one opening of the at least one dielectric layer by using an electroless plating technology and are electrically connected with the at least one aluminum die pad in the at least one opening, and the bumps are a metal stacked structure formed by stacking a nickel (Ni) layer and a gold (Au) layer on the at least one aluminum die pad in sequence, or a metal stacked structure formed by stacking a nickel (Ni) layer, a palladium (Pd) layer and a gold (Au) layer on the at least one aluminum die pad in sequence, so that the structural strength of the at least one aluminum die pad of the chips is improved, the damage in probe detection operation is avoided, the quality and the reliability of the chips in other subsequent operations are improved, and the market competitiveness of products is improved.
In a preferred embodiment of the present utility model, the wafer package is capable of being singulated into a plurality of die package units using a singulation tool.
In a preferred embodiment of the present utility model, the plurality of chip packaging units are electrically connected to the electronic component by forming a first solder joint on the plurality of bumps of the plurality of chip packaging units and a second solder joint on an external electronic component through a bonding wire.
Drawings
Fig. 1 is a schematic plan view of a side view in cross section of a wafer package in an embodiment of the utility model.
Fig. 2 is a schematic plan view of a side cross section of a chip package unit in an embodiment of the utility model.
Fig. 3 is a schematic plan view of a side cross-section of a wafer package in another embodiment of the present utility model.
Fig. 4 is a schematic plan view in side cross section of a chip packaging unit in another embodiment of the utility model.
Fig. 5 is a partial top plan view of a wafer package of the present utility model.
Fig. 6 is a schematic plan view of a side view of a chip package unit and an electronic device electrically connected together according to an embodiment of the utility model.
Fig. 7 is a schematic plan view of a side view of a chip package unit and an electronic component electrically connected together according to another embodiment of the utility model.
Fig. 8 is a schematic plan view of a side view cross section of a conventional wafer.
Fig. 9 is a partial top plan view of a conventional wafer.
Fig. 10 is a schematic plan view of a side cross section of a chip package unit and an electronic device electrically connected together, which are separated from a conventional wafer.
Reference numerals illustrate: 1-a wafer package; 1 a-surface; 1 b-a chip packaging unit; 10-chip; 11-an aluminum die pad; 12-a protective layer; 20-a dielectric layer; 21-opening; 30-bump; 31-nickel layer; a 32-palladium layer; 33-gold layer; 2-electronic components; 3-probe; 4-bonding wire; 4 a-a first welding spot; 4 b-a second welding spot; 5-an existing wafer; 5 a-surface; 5 b-chip; 5 c-an aluminum die pad; 5 d-a protective layer; 5 e-a chip packaging unit; 5 f-concave holes.
Detailed Description
The following detailed description of the structure and technical features of the present utility model is provided with reference to the drawings, wherein each drawing is only for illustrating the structural relationship and related functions of the present utility model, and thus the dimensions of each element in each drawing are not drawn to actual scale and are not intended to limit the present utility model.
Referring to fig. 1 and 3, the present utility model provides a wafer package 1 for preventing an aluminum pad of a chip from being damaged during a probe inspection operation, wherein the wafer package 1 includes a plurality of chips (Die) 10, at least one dielectric layer 20 and a plurality of bumps (Bump) 30.
Each chip 10 is disposed on a surface 1a of the wafer package 1 in an array, and at least one aluminum Pad (Die Pad) 11 and at least one Passivation layer (Passivation) 12 are disposed on each chip 10 as shown in fig. 1 and 3.
Each dielectric layer 20 is disposed on the surface 1a of the wafer package 1, each dielectric layer 20 has at least one opening 21 corresponding to the position of each aluminum pad 11 of each chip 10, and each aluminum pad 11 is electrically connected to the outside through each opening 21 as shown in fig. 1 and 3.
Each bump 30 is formed in each opening 21 of each dielectric layer 20 by using the electroless plating technique and is electrically connected to each aluminum die pad 11 in each opening 21, and each bump 30 is a metal stacked structure formed by stacking a nickel (Ni) layer 31 and a gold (Au) layer 33 on each aluminum die pad 11 in sequence and having a certain thickness, as shown in fig. 1, 2 and 6, or a metal stacked structure formed by stacking a nickel (Ni) layer 31, a palladium (Pd) layer 32 and a gold (Au) layer 33 on each aluminum die pad 11 in sequence and having a certain thickness, as shown in fig. 3, 4 and 7, so as to improve the structural strength of each aluminum die pad 11 of each chip 10 to avoid damage during probe inspection operation.
In the structure of each bump 30, only a part of the Au layer 33 is used, and the rest of the constituent metals of each bump 30 are the nickel (Ni) layer 31 as shown in fig. 2, or the combination of the nickel (Ni) layer 31 and the palladium (Pd) layer 32 as shown in fig. 4, so that the amount of the Au layer 33 used at a relatively high cost can be reduced by such distribution, and the bump 30 does not lose a certain structural strength, thereby being beneficial to the reduction of the manufacturing cost.
After the probe inspection operation is performed on the wafer package 1 having the bumps 30, since the bumps 30 of the present utility model are used to replace the aluminum pads 11 of the chips 10 to receive a positive pressure from the probes 3 as shown by the arrow N in fig. 1 and 3, no concave holes are left on the aluminum pads 11 of the chips 10, and even no concave holes are left on the bumps 30, but not limited to the one shown in fig. 5.
The wafer package 1 of the present utility model may be realized by the following manufacturing method, but is not limited thereto:
step S1: a wafer package 1 is provided, and a surface 1a of the wafer package 1 has a plurality of chips (Die) 10 arranged in an array, and each chip 10 is provided with at least one aluminum Pad (Die Pad) 11 and at least one protection layer (Passivation) 12, as shown in fig. 1 and 3.
Step S2: before each chip 10 in the wafer package 1 performs the probe inspection operation, at least one dielectric layer 20 is disposed on the surface 1a of the wafer package 1, each dielectric layer 20 has at least one opening 21 corresponding to the position of each aluminum pad 11 of each chip 10, and each aluminum pad 11 is electrically connected to the outside through each opening 21 as shown in fig. 1 and 3.
Step S3: at least one Bump (Bump) 30 is formed in each opening 21 of each dielectric layer 20 by using an electroless plating technique, each Bump 30 is electrically connected to each aluminum die pad 11 in each opening 21, and each Bump 30 is a metal stacked structure formed by sequentially stacking a nickel (Ni) layer 31 and a gold (Au) layer 33 on each aluminum die pad 11 and having a certain thickness, as shown in fig. 1 and 2, or a metal stacked structure formed by sequentially stacking a nickel (Ni) layer 31, a palladium (Pd) layer 32 and a gold (Au) layer 33 on each aluminum die pad 11 and having a certain thickness, as shown in fig. 3 and 4.
In addition, after the step S2, a step of dividing the wafer package 1 (as shown in fig. 1 and 3) into a plurality of chip package units 1b (as shown in fig. 2 and 4) by a dividing tool is further included, but not limited thereto; the chip package units 1b are configured for Wire Bonding (Wire Bonding) operations, but not limited to those shown in fig. 6 and 7, and a Bonding Wire 4 is used to form a first Bonding point 4a on each bump 30 of each chip package unit 1b and a second Bonding point 4b on an external electronic component 2, so that each chip package unit 1b and the electronic component 2 are electrically connected together, as shown in fig. 6 and 7.
The wafer package 1 (shown in fig. 1 and 3) of the present utility model has the following advantages compared with the conventional wafer 5 (shown in fig. 8):
before the probe inspection operation is performed on each chip 10 in the wafer package 1 of the present utility model, at least one dielectric layer 20 having each opening 21 is disposed on the surface 1a of the wafer package 1, each opening 21 corresponds to each aluminum pad 11 of each chip 10, each bump 30 is formed in each opening 21 by using the electroless plating technique, each bump 30 is a metal stacked structure formed by stacking a nickel (Ni) layer 31 and a gold (Au) layer 33 on each aluminum pad 11 in sequence, as shown in fig. 1 and 2, or a metal stacked structure formed by stacking a nickel (Ni) layer 31, a palladium (Pd) layer 32 and a gold (Au) layer 33 on each aluminum pad 11 in sequence, so as to improve the structural strength of each aluminum pad 11 of each chip 10 to avoid damage in the probe inspection operation, without leaving a metal stacked structure with a certain thickness on each aluminum pad 11 of each chip 10, thereby facilitating the subsequent promotion of quality of chips 10 and the subsequent market competition improvement of quality and the reliability of products.
The foregoing is merely a preferred embodiment of the present utility model, which is intended to be illustrative and not limiting; it will be appreciated by those skilled in the art that many variations, modifications and even equivalent changes may be made thereto within the spirit and scope of the utility model as defined in the appended claims, but are still within the scope of the utility model.
Claims (3)
1. A wafer package for preventing an aluminum die pad of a chip from being damaged during a probe inspection operation is characterized by comprising:
the plurality of chips are arranged on one surface of the wafer packaging body in an array manner, and each chip is provided with at least one aluminum crystal pad and at least one protective layer;
the at least one dielectric layer is arranged on the surface of the wafer package body, the at least one dielectric layer is provided with at least one opening corresponding to the at least one aluminum crystal pad of the chips, and the at least one aluminum crystal pad is electrically connected outwards from the at least one opening; and
The plurality of bumps are formed in the at least one opening of the at least one dielectric layer by utilizing an electroless plating technology and are electrically connected with the at least one aluminum die pad in the at least one opening, and the plurality of bumps are a metal stacked structure formed by stacking a nickel layer and a gold layer on the at least one aluminum die pad in sequence or a metal stacked structure formed by stacking a nickel layer, a palladium layer and a gold layer on the at least one aluminum die pad in sequence and having a certain thickness, so that the structural strength of the at least one aluminum die pad of the plurality of chips is improved to avoid damage in probe detection operation.
2. The wafer package of claim 1, wherein the wafer package is capable of being singulated into a plurality of die package units using a singulation tool.
3. The wafer package according to claim 2, wherein the plurality of die package units are electrically connected to the electronic component by a bonding wire to form a first bonding pad on the plurality of bumps of the plurality of die package units and a second bonding pad on an external electronic component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320642745.2U CN219998219U (en) | 2023-03-28 | 2023-03-28 | Wafer packaging body capable of preventing aluminum crystal pad of chip from being damaged in probe detection operation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320642745.2U CN219998219U (en) | 2023-03-28 | 2023-03-28 | Wafer packaging body capable of preventing aluminum crystal pad of chip from being damaged in probe detection operation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219998219U true CN219998219U (en) | 2023-11-10 |
Family
ID=88619846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320642745.2U Active CN219998219U (en) | 2023-03-28 | 2023-03-28 | Wafer packaging body capable of preventing aluminum crystal pad of chip from being damaged in probe detection operation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219998219U (en) |
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2023
- 2023-03-28 CN CN202320642745.2U patent/CN219998219U/en active Active
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| GR01 | Patent grant |