CN219759581U - Chip package with metal shielding layer - Google Patents
Chip package with metal shielding layer Download PDFInfo
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- CN219759581U CN219759581U CN202223047412.XU CN202223047412U CN219759581U CN 219759581 U CN219759581 U CN 219759581U CN 202223047412 U CN202223047412 U CN 202223047412U CN 219759581 U CN219759581 U CN 219759581U
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- chip
- layer
- metal shielding
- dielectric layer
- chip package
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- 239000002184 metal Substances 0.000 title claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 45
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 238000003466 welding Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 136
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 239000010931 gold Substances 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The utility model discloses a chip package with a metal shielding layer, wherein the chip package comprises a chip, a rewiring layer and a metal shielding layer; the chip is formed by cutting a wafer; the re-wiring layer is arranged on one surface of at least one chip protection layer of the chip, the re-wiring layer is provided with at least one conducting wire way which is correspondingly and electrically connected with at least one crystal pad of the chip, and each conducting wire way is provided with at least one welding pad which is exposed on one surface of the re-wiring layer so as to be electrically connected with the outside; the metal shielding layer is arranged on the second surface of the chip in a covering way and is used for preventing the chip and each conducting wire from being interfered by electromagnetic or light from the outside, thereby improving the structural strength of the chip package.
Description
Technical Field
The present utility model relates to a chip package, and more particularly, to a chip package with a metal shielding layer.
Background
The 5G technology or the future 6G technology is sequentially applied or designed on each electronic product, each electronic product is free from using the chip packaging product, however, the chip or the internal circuit of the chip packaging product in the electronic product has the problem of being subjected to electromagnetic interference (EMI, electromagnetic Interference) or optical interference from the outside, and when the chip or the internal circuit is interfered, the problem of poor operation or failure and the like of the electronic product is easily caused, so that the reliability of the existing chip packaging product is reduced.
It is conceivable that the electronic product has personal safety problem when applied to the traffic or medical field, so that the problem of poor operation or failure of the product caused by external electromagnetic interference or optical interference of the chip or the internal circuit of the conventional chip package must be improved.
Therefore, a chip package having a metal shielding layer for preventing the chip or the internal circuit from being subjected to electromagnetic interference or optical interference from the outside is highly desired in the related industry.
Disclosure of Invention
The present utility model provides a chip package with a metal shielding layer, wherein the chip package comprises a chip, a redistribution layer and a metal shielding layer; the chip is provided with a first surface and a second surface opposite to the first surface; the rewiring layer is provided with at least one conducting wire which is correspondingly and electrically connected with at least one crystal pad of the chip, and each conducting wire is provided with at least one welding pad which is exposed out of one surface of the rewiring layer so as to be electrically connected with the outside; the metal shielding layer is arranged on the second surface of the chip in a covering way and is used for preventing the chip and each conducting wire from being interfered by electromagnetic or light from the outside, thereby improving the structural strength of the chip package and effectively solving the problem that the chip or the internal circuit of the traditional chip package is interfered by electromagnetic interference (EMI, electromagnetic Interference) or light from the outside.
To achieve the above objective, the present utility model provides a chip package with a metal shielding layer, the chip package comprises a chip, a redistribution layer (RDL, redistribution Layer) and a metal shielding layer; the chip has a first surface and a second surface opposite to the first surface, at least one Die Pad (Die Pad) and at least one chip protection layer are arranged on the first surface, wherein the chip is formed by dividing a wafer; the re-wiring layer is arranged on one surface of the at least one chip protection layer of the chip, the re-wiring layer is provided with at least one conducting wire way which is correspondingly and electrically connected with the at least one crystal Pad of the chip, and the at least one conducting wire way is provided with at least one welding Pad (Pad), and the at least one welding Pad is exposed on one surface of the re-wiring layer so as to be electrically connected with the outside; the metal shielding layer is arranged on the second surface of the chip in a covering way and is used for preventing the chip and the at least one conducting wire from being interfered by electromagnetic or light from the outside, so that the structural strength of the chip package is improved, and the reliability and the market competitiveness of the product are improved.
In a preferred embodiment of the present utility model, the metal shielding layer is further made of silver (Ag) paste material.
In a preferred embodiment of the present utility model, the metal shielding layer further has a surface and a back surface opposite to the surface of the metal shielding layer, the chip is disposed on the surface of the metal shielding layer, and a bottom protection layer is further disposed on the back surface of the metal shielding layer.
In a preferred embodiment of the present utility model, the bottom passivation layer is further made of nickel (Ni) or gold (Au) metal material.
In a preferred embodiment of the present utility model, the redistribution layer further comprises at least one first dielectric layer, at least one second dielectric layer, and at least one insulating layer; the at least one first dielectric layer is arranged on the surface of the at least one chip protection layer of the chip in a covering way, and at least one first groove is formed on the at least one first dielectric layer, so that the at least one crystal pad can be exposed outwards from the at least one first groove; wherein the at least one second dielectric layer is arranged on one surface of the at least one first dielectric layer in a covering way, and at least one second groove is formed on the at least one second dielectric layer and communicated with the at least one first groove of the at least one first dielectric layer; wherein the at least one conductive line is further formed by filling the at least one first groove and the at least one second groove with a metal paste, so that the at least one die pad can be electrically connected with the at least one conductive line; the at least one insulating layer is arranged on one surface of the at least one second dielectric layer and one surface of the at least one conducting wire, and the at least one insulating layer is provided with an opening for exposing the at least one bonding pad of the at least one conducting wire.
In a preferred embodiment of the present utility model, at least one solder ball is further disposed on the opening of the at least one insulating layer, so that the at least one bonding pad on the at least one conductive trace can be electrically connected to the outside through the at least one solder ball.
In a preferred embodiment of the present utility model, the at least one conductive line is further made of silver (Ag) paste material.
In a preferred embodiment of the present utility model, the at least one conductive line further includes a bump, and the bump is made of nickel (Ni) or gold (Au) metal material.
Drawings
FIG. 1 is a schematic side view in cross section of a wafer having a plurality of dies according to the present utility model.
Fig. 2 is a schematic diagram of the multiple chips of fig. 1 after completing the division.
Fig. 3 is a schematic side cross-sectional view of a chip package of the present utility model.
Fig. 4 is a schematic side cross-sectional view of a chip of the present utility model.
Fig. 5 is a schematic diagram of the chip in fig. 4 with a first dielectric layer thereon.
Fig. 6 is a schematic diagram of the first dielectric layer of fig. 5 with a second dielectric layer thereon.
FIG. 7 is a schematic illustration of the first and second grooves of FIG. 6 filled with metal paste.
FIG. 8 is a schematic view of the conductive traces formed in the first and second grooves of FIG. 7.
Fig. 9 is a schematic view of the conductive circuit of fig. 8 with bumps.
Fig. 10 is a schematic view of the second surface of the chip of fig. 9 with a metal shielding layer disposed thereon.
Reference numerals illustrate: 1-packaging a chip; 10-chip; 11-a first surface; 12-a second surface; 13-a die pad; 14-a chip protection layer; 141-surface; 20-a rewiring layer; 21-a conductive line; 21 a-metal paste; 22-bonding pads; 23-surface; 24-a first dielectric layer; 241-first groove; 242-surface; 25-a second dielectric layer; 251-a second groove; 252-surface; 26-an insulating layer; 261-opening; 27-bump; 30-a metal shielding layer; 31-surface; 32-back; 40-bottom protective layer; 50-tin balls; 2-wafer; 2 a-dicing lanes.
Detailed Description
The structure and features of the present utility model will be described in detail below with reference to the accompanying drawings, wherein the drawings are for illustrating the structural relationships and related functions of the present utility model, and thus the dimensions of the elements in the drawings are not drawn to actual scale and are not intended to limit the present utility model.
Referring to fig. 3, the present utility model provides a chip package 1 with a metal shielding layer, the chip package 1 includes a chip 10, a redistribution layer (RDL, redistribution Layer) 20 and a metal shielding layer 30.
The chip 10 has a first surface 11 and a second surface 12 opposite to the first surface 11, and the first surface 11 is provided with at least one Die Pad (Die Pad) 13 and at least one chip protection layer 14 as shown in fig. 4; wherein the die 10 are singulated from a wafer 2 as shown in fig. 1.
The redistribution layer 20 is disposed on a surface 141 of each chip protection layer 14 of the chip 10 as shown in fig. 9, the redistribution layer 20 has at least one conductive trace 21 for electrically connecting with each die Pad 13 of the chip 10, and each conductive trace 21 has at least one Pad (Pad) 22 as shown in fig. 9, and each Pad 22 is exposed on a surface 23 of the redistribution layer for external electrical connection as shown in fig. 9; wherein each conductive trace 21 is further made of, but not limited to, a silver (Ag) paste material.
Wherein the redistribution layer 20 further comprises at least one first dielectric layer 24, at least one second dielectric layer 25, and at least one insulating layer 26, as shown in fig. 9; wherein each first dielectric layer 24 is disposed on the surface 141 of each chip protection layer 14 of the chip 10, and at least one first groove 241 is formed on each first dielectric layer 24, so that each die pad 13 can be exposed from each first groove 241 to the outside as shown in fig. 5; wherein each second dielectric layer 25 is disposed on a surface 242 of each first dielectric layer 24, and at least one second groove 251 is formed on each second dielectric layer 25, and each second groove 251 communicates with each first groove 241 of each first dielectric layer 24 as shown in fig. 6; wherein each conductive trace 21 is further formed by filling a metal paste 21a (as shown in fig. 7) in each first recess 241 and each second recess 251 smoothly, but not limited thereto, so that each die pad 13 can be electrically connected to each conductive trace 21 as shown in fig. 8; wherein each insulating layer 26 is disposed on a surface 252 of each second dielectric layer 25 and the surface 23 of each conductive trace 21, and each insulating layer 26 has an opening 261 for exposing each bonding pad 22 of each conductive trace 21 to the outside as shown in fig. 9; wherein each of the conductive traces 21 further includes a bump 27, but not limited to, as shown in fig. 9, the bump 27 is made of nickel (Ni) or gold (Au) metal material, thereby enhancing the structural strength of each of the conductive traces 21.
The metal shielding layer 30 is disposed on the second surface 12 of the chip 10 in a covering manner as shown in fig. 10, and is used for preventing the chip 10 and each conductive trace 21 from being interfered by electromagnetic or light from the outside, thereby improving the structural strength of the chip package 1; wherein the metallic shield layer 30 is further made of, but not limited to, a silver (Ag) paste material.
Wherein the metal shielding layer 30 further has a surface 31 and a back surface 32 opposite to the surface 31 of the metal shielding layer 30, but not limited to, as shown in fig. 10, the chip 10 is disposed on the surface 31 of the metal shielding layer 30, and a bottom passivation layer 40 is further disposed on the back surface 32 of the metal shielding layer 30, but not limited to, as shown in fig. 3, so as to enhance the structural strength of the chip package 1; wherein each of the under-jackets 40 is further made of, but not limited to, a nickel (Ni) or gold (Au) metal material.
Referring to fig. 3, at least one solder ball 50 is further disposed on each opening 261 of each insulating layer 26, but not limited thereto, so that each bonding pad 22 on each conductive trace 21 can be electrically connected to the outside through each solder ball 50.
Referring to fig. 1 to 10, the chip package 1 may be manufactured by a manufacturing method of a chip package having an interference shielding layer on a back surface, the manufacturing method comprising the steps of:
step S1: providing a wafer 2, wherein a plurality of chips 10 arranged in an array are disposed on the wafer 2 as shown in fig. 1, each chip 10 has a first surface 11 and a second surface 12 opposite to the first surface 11, and at least one Die Pad 13 and at least one chip protection layer 14 are disposed on the first surface 11 as shown in fig. 4; wherein a scribe line 2a for dividing each chip 10 is provided between two adjacent chips 10 on the wafer 2 as shown in fig. 1.
Step S2: at least one redistribution layer (RDL, redistribution Layer) 20 is correspondingly disposed on a surface 141 of each chip protection layer 14 of each chip 10 as shown in fig. 9, the redistribution layer 20 has at least one conductive trace 21 for corresponding electrical connection with each die Pad 13 of each chip 10, and each conductive trace 21 has at least one Pad (Pad) 22, and each Pad 22 is exposed on a surface 23 of the redistribution layer 20 for external electrical connection as shown in fig. 9; at least one first dielectric layer 24 is disposed on the surface 141 of the chip protection layer 14 of each chip 10 correspondingly, but not limited to fig. 5, and at least one first groove 241 is formed on each first dielectric layer 24, so that each die pad 13 can be exposed from each first groove 241 to the outside as shown in fig. 5; wherein, at least one second dielectric layer 25 is correspondingly disposed on a surface 242 of each first dielectric layer 241 as shown in fig. 6, at least one second groove 251 is formed on each second dielectric layer 25, and each second groove 251 communicates with each first groove 241 of each first dielectric layer 24 as shown in fig. 6; wherein a metal paste 21a is filled into each first recess 241 and each second recess 251, and the thickness of the metal paste 21a is higher than a surface 252 of each second dielectric layer 25 as shown in fig. 7; wherein the metal paste 21a higher than the surface 252 of each second dielectric layer 25 is polished and the surface 252 of each second dielectric layer 25 is exposed, so that the surface of the metal paste 21a (shown in fig. 7) is level with the surface 252 of each second dielectric layer 25 to form each conductive trace 21 as shown in fig. 8; at least one insulating layer 26 is disposed on a surface 252 of each second dielectric layer 25 and the surface 23 of each conductive trace 21 as shown in fig. 9, and each insulating layer 26 has an opening 261 for exposing each bonding pad 22 of each conductive trace 21 to the outside as shown in fig. 9; wherein each conductive trace 21, each first dielectric layer 24, each second dielectric layer 25, and each insulating layer 26 form each redistribution layer 20 as shown in fig. 9.
Step S3: a metal shielding layer 30 is disposed on the second surface 12 of each die 10 as shown in fig. 10.
Step S4: the chips 10 on the wafer 2 are divided along the dicing streets 2a (shown in fig. 1) of the wafer 2 to form a plurality of chip packages 1 as shown in fig. 2.
Compared with the conventional chip package, the chip package 1 of the present utility model has the following advantages that the metal shielding layer 30 of the present utility model is provided on the second surface 12 of the chip 10 in a covering manner as shown in fig. 10:
(1) The chip 10 and the conductive lines 21 are used for preventing the chip from being interfered by electromagnetic or light from the outside, so that the problem that the chip or the internal circuit of the conventional chip package is interfered by electromagnetic interference (EMI, electromagnetic Interference) or light from the outside is effectively solved, and the reliability and market competitiveness of the product are improved.
(2) Therefore, the structural strength of the chip package 1 is improved, and the problems that the chip package 1 is damaged to influence the electronic product to generate poor operation or faults and the like are avoided, so that the reliability and the market competitiveness of the product are improved.
The trend of technological products of 5G technology or future 6G technology is gradually moving to various fields, so that most of electronic products need to be applied to chip packaging products if the electronic products meet market demands, and therefore, when the electronic system is applied to the traffic or medical fields, the electronic system operated by the chip or the internal circuit of the chip packaging products can keep normal operation, and the danger of personal safety is avoided.
The foregoing is merely a preferred embodiment of the present utility model, which is intended to be illustrative and not limiting; it will be appreciated by those skilled in the art that many changes, modifications and even equivalent changes may be made thereto without departing from the spirit and scope of the utility model as defined in the appended claims, but are to be accorded the true scope of the utility model.
Claims (8)
1. A chip package having a metal shielding layer, comprising:
a chip having a first surface and a second surface opposite to the first surface, wherein the first surface is provided with at least one die pad and at least one chip protection layer; wherein the chip is formed by dividing a wafer;
the rewiring layer is arranged on one surface of the at least one chip protection layer of the chip, is provided with at least one conducting wire which is correspondingly and electrically connected with the at least one crystal pad of the chip, and is provided with at least one welding pad which is exposed on one surface of the rewiring layer so as to be electrically connected with the outside; and
And the metal shielding layer is arranged on the second surface of the chip in a covering way and is used for preventing the chip and the at least one conducting wire from being interfered by electromagnetic or light from the outside, thereby improving the structural strength of the chip package.
2. The chip package of claim 1, wherein the metal shielding layer is further made of a silver paste material.
3. The chip package of claim 1, wherein the metal shielding layer further has a surface and a back surface opposite to the surface of the metal shielding layer, the chip being disposed on the surface of the metal shielding layer, and a bottom passivation layer being further disposed on the back surface of the metal shielding layer.
4. The chip package of claim 3, wherein the bottom protective layer is further made of nickel or gold metal material.
5. The chip package of claim 1, wherein the redistribution layer further comprises at least one first dielectric layer, at least one second dielectric layer, and at least one insulating layer; the at least one first dielectric layer is arranged on the surface of the at least one chip protection layer of the chip in a covering way, and at least one first groove is formed on the at least one first dielectric layer, so that the at least one crystal pad can be exposed outwards from the at least one first groove; wherein the at least one second dielectric layer is arranged on one surface of the at least one first dielectric layer in a covering way, and at least one second groove is formed on the at least one second dielectric layer and communicated with the at least one first groove of the at least one first dielectric layer; wherein the at least one conductive line is further formed by filling the at least one first groove and the at least one second groove with a metal paste, so that the at least one die pad can be electrically connected with the at least one conductive line; the at least one insulating layer is arranged on one surface of the at least one second dielectric layer and one surface of the at least one conducting wire, and the at least one insulating layer is provided with an opening for exposing the at least one bonding pad of the at least one conducting wire.
6. The chip package of claim 5, wherein the opening of the at least one insulating layer is further provided with at least one solder ball, such that the at least one bonding pad on the at least one conductive trace can be electrically connected to the outside through the at least one solder ball.
7. The chip package of claim 1, wherein the at least one conductive trace is further made of a silver paste material.
8. The chip package of claim 1, wherein the at least one conductive trace further comprises a bump, the bump being made of a nickel or gold metal material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223047412.XU CN219759581U (en) | 2022-11-16 | 2022-11-16 | Chip package with metal shielding layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223047412.XU CN219759581U (en) | 2022-11-16 | 2022-11-16 | Chip package with metal shielding layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219759581U true CN219759581U (en) | 2023-09-26 |
Family
ID=88072543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223047412.XU Active CN219759581U (en) | 2022-11-16 | 2022-11-16 | Chip package with metal shielding layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219759581U (en) |
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2022
- 2022-11-16 CN CN202223047412.XU patent/CN219759581U/en active Active
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