CN219123231U - Chip packaging structure with electromagnetic interference shielding layer - Google Patents

Abstract

The utility model discloses a chip packaging structure with an electromagnetic interference shielding layer, wherein the chip packaging structure comprises a chip, a rewiring layer, an insulating layer and an electromagnetic interference shielding layer; wherein, the insulating layer is formed with a circumferential wall around the circumference of at least one first opening of the insulating layer to surround each first opening, and a recessed platform is formed in the peripheral area of the circumferential wall, and the horizontal height of the platform is lower than that of the circumferential wall; wherein the electromagnetic interference shielding layer is arranged on the platform of the insulating layer in a covering way and is used for preventing each conducting circuit and the chip from electromagnetic interference; the electromagnetic interference shielding layer is isolated and electrically insulated from each welding pad through the peripheral wall of the insulating layer so as to improve the reliability of the product and increase the market competitiveness of the product.

Description

Chip packaging structure with electromagnetic interference shielding layer

Technical Field

The present utility model relates to a chip package, and more particularly to a chip package with an electromagnetic interference shielding layer.

Background

Along with the progress of technology and the change of the use demands of people, the 5G technology or the future 6G technology can be applied to various electronic products successively, and the various electronic products can not use chip products.

The temperature of a chip or an internal circuit in the electronic product is easy to rise along with the increase of the service time, so that the product is short-circuited or broken, even damaged, and the reliability of the product is easy to be reduced. In addition, in daily life, there is a problem of electromagnetic interference (EMI, electromagnetic Interference), and if the chip or internal circuit in the electronic product is subjected to electromagnetic interference, the product will be shorted or failed, so that the reliability of the product is easily reduced.

Therefore, the problem of short circuit or failure of the chip or internal circuit in the electronic product due to high temperature and electromagnetic interference must be improved.

Therefore, a chip package structure with an electromagnetic interference shielding layer, which can solve the problem of short circuit or failure of the chip or internal circuit due to high temperature and electromagnetic interference, is highly desired by the related industry.

Disclosure of Invention

The utility model provides a chip packaging structure with an electromagnetic interference shielding layer, wherein the chip packaging structure comprises a chip, a rewiring layer, an insulating layer and an electromagnetic interference shielding layer; wherein, the insulating layer is formed with a circumferential wall around the circumference of at least one first opening of the insulating layer to surround each first opening, and a recessed platform is formed in the peripheral area of the circumferential wall, and the horizontal height of the platform is lower than that of the circumferential wall; wherein the electromagnetic interference shielding layer is arranged on the platform of the insulating layer in a covering way and is used for preventing each conducting circuit and the chip from electromagnetic interference; the electromagnetic interference shielding layer is isolated from each welding pad through the peripheral wall of the insulating layer and is electrically insulated from each welding pad, so that the problem of product short circuit or failure caused by high temperature and electromagnetic interference of chips or internal circuits in electronic products is effectively solved.

In order to achieve the above-mentioned objective, the present utility model provides a chip package structure with an electromagnetic interference shielding layer, the chip package structure comprises a chip, a redistribution layer (RDL, redistribution Layer), an insulating layer and an electromagnetic interference shielding layer; the chip has a surface, at least one Die Pad (Die Pad) and at least one chip protection layer are disposed on the surface, wherein the chip is formed by dividing a wafer; the re-wiring layer is arranged on one surface of the at least one chip protection layer of the chip, the re-wiring layer is provided with at least one conducting wire way which is correspondingly and electrically connected with the at least one crystal Pad of the chip, and the at least one conducting wire way is provided with at least one welding Pad (Pad), and the at least one welding Pad is exposed on one surface of the re-wiring layer so as to be electrically connected with the outside; the insulating layer is fully covered on the surface of the re-wiring layer, and is provided with at least one first opening so that the at least one welding pad on the at least one conducting wire can be exposed outwards through the at least one first opening, wherein the insulating layer is provided with a circumferential wall at the circumferential position of the at least one first opening so as to surround the at least one first opening, and a concave platform is formed at the peripheral area of the circumferential wall, and the horizontal height of the platform is lower than that of the circumferential wall; the electromagnetic interference shielding layer is formed by metal materials and is arranged on the platform of the insulating layer in a covering manner for preventing the at least one conducting wire and the chip from being subjected to electromagnetic interference; wherein the electromagnetic interference shielding layer is isolated from and electrically insulated from the at least one bonding pad by the peripheral wall of the insulating layer.

In a preferred embodiment of the present utility model, the electromagnetic interference shielding layer is further made of silver (Ag) paste material.

In a preferred embodiment of the present utility model, the level of the emi shielding layer is further not higher than the level of the insulating layer at the peripheral wall.

In a preferred embodiment of the present utility model, at least one solder ball is further disposed on the at least one first opening of the insulating layer, so that the at least one bonding pad on the at least one conductive trace can be electrically connected to the outside through the at least one solder ball, wherein the at least one solder ball is isolated from and electrically insulated from the electromagnetic interference shielding layer by the peripheral wall of the insulating layer.

In a preferred embodiment of the present utility model, at least one outer passivation layer is further disposed on a surface of the electromagnetic interference shielding layer.

In a preferred embodiment of the present utility model, the at least one outer passivation layer is further made of nickel (Ni) or gold (Au) metal material.

In a preferred embodiment of the present utility model, the redistribution layer further comprises at least one first dielectric layer and at least one second dielectric layer; the at least one first dielectric layer is arranged on one surface of the at least one chip protection layer of the chip in a covering way, and at least one first groove is formed on the at least one first dielectric layer, so that the at least one crystal pad can be exposed outwards from the at least one first groove; wherein the at least one second dielectric layer is arranged on one surface of the at least one first dielectric layer in a covering way, and at least one second groove is formed on the at least one second dielectric layer and communicated with the at least one first groove of the at least one first dielectric layer; wherein the at least one conductive line is further formed by filling the at least one first groove and the at least one second groove with a metal paste, so that the at least one die pad can be electrically connected with the at least one conductive line.

In a preferred embodiment of the present utility model, the at least one conductive line is further made of silver (Ag) paste material.

In a preferred embodiment of the present utility model, the at least one conductive line further includes a bump, and the bump is made of nickel (Ni) or gold (Au) metal material.

Drawings

FIG. 1 is a schematic side view in cross section of a wafer having a plurality of dies according to the present utility model.

Fig. 2 is a schematic diagram of the multiple chips of fig. 1 after completing the division.

Fig. 3 is a schematic side view of a chip package structure according to the present utility model.

Fig. 4 is a schematic side cross-sectional view of a chip of the present utility model.

Fig. 5 is a schematic diagram of the chip in fig. 4 with a first dielectric layer thereon.

Fig. 6 is a schematic diagram of the first dielectric layer of fig. 5 with a second dielectric layer thereon.

FIG. 7 is a schematic illustration of the first and second grooves of FIG. 6 filled with metal paste.

FIG. 8 is a schematic view of the conductive traces formed in the first and second grooves of FIG. 7.

Fig. 9 is a schematic view of the conductive circuit of fig. 8 with bumps.

Fig. 10 is a schematic view of the redistribution layer of fig. 9 with an insulating layer disposed thereon.

Fig. 11 is a schematic illustration of the insulating layer of fig. 10 filled with metal paste on the mesa.

Fig. 12 is a schematic view of an electromagnetic interference shielding layer formed on the platform of the insulating layer of fig. 11.

Reference numerals illustrate: 1-a chip packaging structure; 10-chip; 11-surface; 12-a die pad; 13-a chip protection layer; 14-surface; 20-a rewiring layer; 201-surface; 21-a conductive line; 21 a-metal paste; 211-surface; 212-bonding pads; 213-bump; 22-a first dielectric layer; 221-a first groove; 222-surface; 23-a second dielectric layer; 231-a second groove; 232-surface; 30-an insulating layer; 31-a first opening; 32-a peripheral wall; 33-a platform; 40-an electromagnetic interference shielding layer; 40 a-metal paste; 41-surface; 50-tin balls; 60-an outer sheath; 2-wafer; 2 a-dicing lanes.

Detailed Description

The structure and features of the present utility model will be described in detail below with reference to the accompanying drawings, wherein the drawings are for illustrating the structural relationships and related functions of the present utility model, and thus the dimensions of the elements in the drawings are not drawn to actual scale and are not intended to limit the present utility model.

Referring to fig. 3, the present utility model provides a chip package structure 1 with an electromagnetic interference shielding layer, wherein the chip package structure 1 comprises a chip 10, a redistribution layer (RDL, redistribution Layer) 20, an insulating layer 30 and an electromagnetic interference shielding layer 40.

The chip 10 has a surface 11, and the surface 11 is provided with at least one Die Pad 12 and at least one chip protection layer 13 as shown in fig. 4; wherein the die 10 are singulated from a wafer 2 as shown in fig. 1.

The redistribution layer (RDL, redistribution Layer) 20 is disposed on a surface 14 of each chip protection layer 13 of the chip 10, the redistribution layer 20 has at least one conductive trace 21 for corresponding electrical connection with each die Pad 12 of the chip 10 as shown in fig. 8, and each conductive trace 21 has at least one Pad (Pad) 212, and each Pad 212 is exposed on a surface 201 of the redistribution layer 20 for external electrical connection as shown in fig. 10; wherein each conductive trace 21 is further made of, but not limited to, a silver (Ag) paste material.

The insulating layer 30 is entirely disposed on the surface 201 of the redistribution layer 20, and the insulating layer 30 has at least one first opening 31, so that each bonding pad 212 on each conductive trace 21 can be exposed through each first opening 31 as shown in fig. 10; wherein the insulating layer 30 has a peripheral wall 32 formed around the periphery of each first opening 31 to surround each first opening 31, and a recessed land 33 is formed in the peripheral area of the peripheral wall 32 as shown in fig. 10; wherein the level of the platform 33 is lower than the level of the peripheral wall 32 as shown in fig. 10.

The electromagnetic interference shielding layer 40 is made of metal material, and the electromagnetic interference shielding layer 40 is arranged on the platform 33 of the insulating layer 30 in a covering manner for preventing each conductive line 21 and the chip 10 from being subjected to electromagnetic interference as shown in fig. 12; wherein the electromagnetic interference shielding layer 40 is further made of, but not limited to, silver (Ag) paste material; the level of the emi shielding layer 40 is further not higher than the level of the insulating layer 30 at the peripheral wall 32, i.e. the emi shielding layer 40 is isolated from the peripheral wall 32 by the peripheral wall 32, so that the emi shielding layer 40 is isolated from and electrically insulated from the pads 212 without interfering with or affecting the pads 212.

The emi shielding layer 40 is isolated from and electrically insulated from each of the pads 212 by the peripheral wall 32 of the insulating layer 30 as shown in fig. 12.

Referring to fig. 1 to 3, at least one solder ball 50 is further disposed on each first opening 31 of the insulating layer 30, but not limited to, so that each bonding pad 212 on each conductive trace 21 can be electrically connected to the outside through each solder ball 50; wherein each solder ball 50 is isolated from and electrically insulated from the emi shielding layer 40 by the peripheral wall 32 of the insulating layer 30.

Referring to fig. 3, at least one outer protective layer 60 is further disposed on a surface 41 of the electromagnetic interference shielding layer 40, which is not limited thereto, and helps to increase the protection of the product; wherein each of the outer passivation layers 60 is further made of, but not limited to, nickel (Ni) or gold (Au) metal material, which helps to enhance the heat dissipation effect.

Referring to fig. 8, the redistribution layer 20 further includes, but is not limited to, at least a first dielectric layer 22 and at least a second dielectric layer 23; wherein each first dielectric layer 22 is disposed on a surface 14 of each chip protection layer 13 of the chip 10, and at least one first groove 221 is formed on each first dielectric layer 22, so that each die pad 12 can be exposed from each first groove 221 to the outside as shown in fig. 5; wherein each second dielectric layer 23 is disposed on a surface 222 of each first dielectric layer 22, and at least one second recess 231 is formed on each second dielectric layer 23, and each second recess 231 is in communication with each first recess 221 of each first dielectric layer 22 as shown in fig. 6; each of the conductive traces 21 (as shown in fig. 8) is further formed by filling a metal paste 21a in each of the first grooves 221 and each of the second grooves 231 (as shown in fig. 7) so that each of the die pads 12 can be electrically connected with each of the conductive traces 21, and the problem that the thickness of the conductive trace structure is thicker or the manufacturing process is complicated in the conventional chip product is effectively improved by the redistribution layer technology, so as to conform to the trend of the modern chip-passing conductive trace structure toward thinner and thinner, and be beneficial to reducing the manufacturing end cost.

Referring to fig. 9, each conductive trace 21 further includes a bump 213, but not limited to, to facilitate the structural protection or electrical conduction of each conductive trace 21, wherein the bump 213 is made of nickel (Ni) or gold (Au) metal material, but not limited to.

Referring to fig. 1, 2, 4 to 8, and 10 to 12, the chip package structure 1 of the present utility model may be manufactured by a manufacturing method comprising the steps of:

step S1: providing a wafer 2, wherein a plurality of chips 10 (shown in fig. 1) arranged in an array are disposed on the wafer 2, each chip 10 has a surface 11, and at least one Die Pad 12 and at least one chip protection layer 13 are disposed on the surface 11 as shown in fig. 4; wherein a scribe line 2a for dividing each chip 10 is provided between two adjacent chips 10 on the wafer 2 as shown in fig. 1.

Step S2: at least one redistribution layer (RDL, redistribution Layer) 20 is disposed on a surface 14 of each chip protection layer 13 of each chip 10 correspondingly, the redistribution layer 20 has at least one conductive trace 21 for corresponding electrical connection with each die Pad 12 of the chip 10 (as shown in fig. 8), and each conductive trace 21 has at least one Pad (Pad) 212, and each Pad 212 is exposed on a surface 211 of the redistribution layer 20 for external electrical connection as shown in fig. 10.

At least one first dielectric layer 22 is disposed on the surface 14 of the chip protection layer 13 of each chip 10 correspondingly, as shown in fig. 5, and at least one first groove 221 is formed on each first dielectric layer 22, so that each die pad 12 can be exposed from each first groove 21, as shown in fig. 5; wherein, at least one second dielectric layer 23 is correspondingly disposed on a surface 222 of each first dielectric layer 22 in a covering manner as shown in fig. 6, at least one second groove 231 is formed on each second dielectric layer 23, and each second groove 231 is communicated with each first groove 221 of each first dielectric layer 22 as shown in fig. 6; wherein a metal paste 21a is filled into each of the first grooves 221 and each of the second grooves 231, and the thickness of the metal paste 21a is higher than a surface 32 of each of the second dielectric layers 30 as shown in fig. 7; wherein the metal paste 21a (shown in fig. 7) above a surface 232 of each second dielectric layer 23 is polished and the surface 222 of each second dielectric layer 22 is exposed, so that the surface of the metal paste 21a (shown in fig. 7) is level with the surface 232 of each second dielectric layer 23 to form each conductive line 21 as shown in fig. 8; wherein each conductive trace 21, each first dielectric layer 22, and each second dielectric layer 23 constitute each redistribution layer 20 as shown in fig. 8.

Step S3: an insulating layer 30 is fully disposed on a surface 201 of the redistribution layer 20, as shown in fig. 10, and the insulating layer 30 has at least one first opening 31, so that each bonding pad 212 on each conductive trace 21 can be exposed from each first opening 31 to the outside, as shown in fig. 10.

Step S4: forming a peripheral wall 32 around the periphery of each first opening 31 of the insulating layer 30 to enclose each first opening 31, and forming a recessed land 33 on the insulating layer 30 in the peripheral area of the peripheral wall 32 as shown in fig. 10; wherein the level of the platform 33 is lower than the level of the peripheral wall 32 as shown in fig. 10.

Step S5: forming an electromagnetic interference shielding layer 40 on the platform 33 of the insulating layer 30 in a covering manner as shown in fig. 12, wherein the electromagnetic interference shielding layer 40 is made of a metal material; wherein the emi shielding layer 40 is isolated from and electrically isolated from each of the pads 212 by the peripheral wall 32 of the insulating layer 30 as shown in fig. 12.

Wherein, the platform 33 of the insulating layer 30 is filled with a metal paste 40a, but not limited to, as shown in fig. 11, and the thickness of the metal paste 40a is higher than the horizontal height of the peripheral wall 32 as shown in fig. 11; wherein the metal paste 40a (shown in fig. 11) higher than the peripheral wall 32 is polished and the horizontal surface of the peripheral wall 32 is exposed so that the surface of the metal paste 40a (shown in fig. 11) is flush with the horizontal surface of the peripheral wall 32 to constitute the electromagnetic interference shielding layer 40 as shown in fig. 12.

Step S6: the dicing lanes 2a of the wafer 2 are used to divide the chips 10 on the wafer 2 as shown in fig. 1, so as to form a plurality of chip packages 1 as shown in fig. 2.

Compared with the existing chip packaging structure, the chip packaging structure 1 has the following advantages:

the insulating layer 30 of the present utility model has the peripheral wall 32 formed around the periphery of each first opening 31 to surround each first opening 31, and the recessed land 33 is formed in the peripheral area of the peripheral wall 32, and the level of the land 33 is lower than the level of the peripheral wall 32; the electromagnetic interference shielding layer 40 of the present utility model is made of metal material to facilitate the heat dissipation of the product, and the electromagnetic interference shielding layer 40 is disposed on the platform 33 of the insulating layer 30 in a covering manner for preventing the conductive traces 21 and the chip 10 from electromagnetic interference; the emi shielding layer 40 is isolated from and electrically insulated from each bonding pad 212 by the peripheral wall 32 of the insulating layer 30, so as to effectively solve the problem of product short circuit or failure caused by high temperature and electromagnetic interference of chips or internal circuits in the electronic product, thereby improving the reliability of the product and being beneficial to improving the market competitiveness of the product.

In addition, technological product trends of 5G technology or future 6G technology are gradually going to various fields, so that most of electronic products need to be applied to chips if the electronic products are in line with market demands, and therefore, when the electronic system is applied to the traffic or medical fields, the electronic system operated by the chips or internal circuits in the electronic products can keep normal operation, and the danger of personal safety is avoided.

The foregoing description of the preferred embodiments of the present utility model is merely illustrative, and not restrictive, of the utility model. It will be appreciated by those skilled in the art that many variations, modifications and even equivalent changes may be made thereto within the spirit and scope of the utility model as defined in the appended claims, but are still within the scope of the utility model.

Claims (9)

1. A chip package structure with an electromagnetic interference shielding layer, comprising:

a chip having a surface with at least one die pad and at least one chip protection layer thereon; wherein the chip is formed by dividing a wafer;

the rewiring layer is arranged on one surface of the at least one chip protection layer of the chip, is provided with at least one conducting wire which is correspondingly and electrically connected with the at least one crystal pad of the chip, and is provided with at least one welding pad which is exposed on one surface of the rewiring layer so as to be electrically connected with the outside;

an insulating layer which is entirely covered on the surface of the re-wiring layer, wherein the insulating layer is provided with at least one first opening so that the at least one bonding pad on the at least one conducting wire can be exposed outside through the at least one first opening; wherein the insulating layer is provided with a circumferential wall around the circumference of the at least one first opening to surround the at least one first opening, and a concave platform is formed in the circumferential region of the circumferential wall; wherein the level of the platform is lower than the level of the peripheral wall; a kind of electronic device with high-pressure air-conditioning system

The electromagnetic interference shielding layer is formed by a metal material and is arranged on the platform of the insulating layer in a covering manner for preventing the at least one conducting wire path and the chip from electromagnetic interference;

wherein the electromagnetic interference shielding layer is isolated from and electrically insulated from the at least one bonding pad by the peripheral wall of the insulating layer.

2. The chip package of claim 1, wherein the emi shielding layer is further made of a silver paste material.

3. The chip package structure of claim 1, wherein the level of the emi shielding layer is not higher than the level of the insulating layer at the peripheral wall.

4. The chip package structure of claim 1, wherein the at least one first opening of the insulating layer is further provided with at least one solder ball, so that the at least one bonding pad on the at least one conductive trace can be electrically connected to the outside through the at least one solder ball; wherein the at least one solder ball is isolated from and electrically insulated from the electromagnetic interference shielding layer by the peripheral wall of the insulating layer.

5. The chip package structure of claim 1, wherein the electromagnetic interference shielding layer further comprises at least one outer passivation layer on a surface thereof.

6. The chip package structure of claim 5, wherein the at least one outer passivation layer is further made of nickel or gold metal material.

7. The chip package structure of claim 1, wherein the redistribution layer further comprises at least one first dielectric layer and at least one second dielectric layer; the at least one first dielectric layer is arranged on one surface of the at least one chip protection layer of the chip in a covering way, and at least one first groove is formed on the at least one first dielectric layer, so that the at least one crystal pad can be exposed outwards from the at least one first groove; wherein the at least one second dielectric layer is arranged on one surface of the at least one first dielectric layer in a covering way, and at least one second groove is formed on the at least one second dielectric layer and communicated with the at least one first groove of the at least one first dielectric layer; wherein the at least one conductive line is further formed by filling the at least one first groove and the at least one second groove with a metal paste, so that the at least one die pad can be electrically connected with the at least one conductive line.

8. The chip package of claim 1, wherein the at least one conductive trace is further made of a silver paste material.

9. The chip package structure of claim 1, wherein the at least one conductive trace further comprises a bump made of a nickel or gold metal material.

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