CN219918483U - Super capacitor charging and discharging circuit - Google Patents
Super capacitor charging and discharging circuit Download PDFInfo
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- CN219918483U CN219918483U CN202320351405.4U CN202320351405U CN219918483U CN 219918483 U CN219918483 U CN 219918483U CN 202320351405 U CN202320351405 U CN 202320351405U CN 219918483 U CN219918483 U CN 219918483U
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- effect transistor
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- 239000003990 capacitor Substances 0.000 title claims abstract description 62
- 238000007599 discharging Methods 0.000 title claims abstract description 20
- 230000005669 field effect Effects 0.000 claims abstract description 51
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 24
- 238000004146 energy storage Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- Direct Current Feeding And Distribution (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
- Stand-By Power Supply Arrangements (AREA)
Abstract
The utility model discloses a super capacitor charge-discharge circuit, which comprises a diode and a first resistor which are arranged in parallel, wherein a first common end between a cathode of the diode and the first resistor is connected with an output end, and a second common end between an anode of the diode and the first resistor is connected with a plurality of charge-discharge units which are sequentially connected in series; each charge-discharge unit comprises a voltage dividing resistor, a field effect transistor, a current limiting resistor, a voltage stabilizing diode and a super capacitor; one end of the divider resistor is connected with the input end, the other end of the divider resistor is connected with the grid electrode of the field effect transistor, the drain electrode of the field effect transistor is connected with the anode of the voltage stabilizing diode after passing through the current limiting resistor, and the super capacitor is arranged between the cathode of the voltage stabilizing diode and the source electrode of the field effect transistor in parallel. The super capacitor charging and discharging circuit provided by the utility model can effectively improve the energy storage of the super capacitor and delay the power-down time of the system.
Description
Technical Field
The utility model belongs to the field of electronic circuits, and particularly relates to a super capacitor charging and discharging circuit.
Background
Along with the continuous improvement of the science and technology level, the quality requirement of electronic products is also higher and higher, in some scenes related to the power supply of an RTC clock, after the power supply end is powered off, the power supply is continuously supplied for a later-stage circuit through setting a super capacitor or a battery and the like, in addition, in some occasions, because the RTC clock runs at the moment, when the system is powered off, the power is insufficient, the whole system time is stopped, and the time displayed by the system at the next power-on time is not the current time.
However, in the prior art, a battery is used as a standby power supply, the battery is easy to damage due to overdischarge and cannot be charged, the battery cannot be used for multiple times, a super capacitor is used as the standby power supply, the circuit power consumption is high, the super capacitor is not long in time for maintaining a later-stage circuit, data cannot be correspondingly stored, and some technical defects exist. Therefore, how to increase the energy storage of the backup capacitor and delay the power-down time of the system is a problem to be solved.
Disclosure of Invention
The utility model provides a super capacitor charging and discharging circuit which is used for solving the problem of how to improve the energy storage of a standby capacitor and delay the power-down time of a system.
In order to solve the technical problems, the utility model provides a super capacitor charging and discharging circuit, which comprises a diode D1 and a first resistor R1 which are arranged in parallel, wherein a first common end between a cathode of the diode D1 and the first resistor R1 is connected with an output end, and a second common end between an anode of the diode D1 and the first resistor R1 is connected with a plurality of charging and discharging units which are sequentially connected in series;
each charge-discharge unit comprises a voltage dividing resistor, a field effect transistor, a current limiting resistor, a voltage stabilizing diode and a super capacitor; one end of the divider resistor is connected with the input end, the other end of the divider resistor is connected with the grid electrode of the field effect transistor, the drain electrode of the field effect transistor is connected with the anode of the voltage stabilizing diode after passing through the current limiting resistor, and the super capacitor is arranged between the cathode of the voltage stabilizing diode and the source electrode of the field effect transistor in parallel; and the source electrode of the field effect transistor arranged in the last series-connected charge and discharge unit is grounded.
Further, a bias resistor is further arranged in each charge-discharge unit, one end of the bias resistor is connected to a connection node between the voltage dividing resistor and the grid electrode of the field effect transistor, and the other end of the bias resistor is grounded.
Further, a second resistor R2 is further disposed in parallel between the first resistor R1 and the diode D1.
Further, in each charge-discharge unit, the positive electrode of the super capacitor is connected with the cathode of the zener diode, and the negative electrode of the super capacitor is connected with the source electrode of the field effect transistor.
Further, when the voltage of the input end is greater than 0, the input end charges the super capacitor arranged in each charge-discharge unit after passing through the first resistor R1 and the second resistor R2;
when the input terminal voltage=0, the electric energy stored by the super capacitor arranged in the charge and discharge units arranged in series sequentially supplies power to the output terminal through the diode D1.
Further, the resistance value of the first resistor R1 and the second resistor R2 is 10Ω.
Further, the diode D1 is a schottky diode.
Compared with the prior art, the super capacitor charging and discharging circuit provided by the utility model has the following beneficial effects:
according to the super capacitor charging and discharging circuit provided by the utility model, the super capacitor is used as a standby power supply by arranging the plurality of charging and discharging units, and the power supply is powered by the plurality of super capacitors connected in series after the power supply is powered off, so that the energy storage of the super capacitor is improved, the power-down time of a system is delayed, and the system data can be stored in time.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions of the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, but not all embodiments, and other drawings obtained according to these drawings without inventive effort are all within the scope of the present utility model.
Fig. 1 is a schematic structural diagram of a super capacitor charging and discharging circuit according to an embodiment of the present utility model;
fig. 2 is a schematic structural diagram of a discharging process of a super capacitor in a super capacitor charging and discharging circuit according to an embodiment of the present utility model.
Detailed Description
In order to make the objects, technical solutions and advantages of the present utility model more apparent, the present utility model will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
In order that the present disclosure may be more fully described and fully understood, the following description is provided by way of illustration of embodiments and specific examples of the present utility model; this is not the only form of practicing or implementing the utility model as embodied. The description covers the features of the embodiments and the method steps and sequences for constructing and operating the embodiments. However, other embodiments may be utilized to achieve the same or equivalent functions and sequences of steps. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein.
In the description of the embodiments of the present utility model, unless otherwise indicated, "/" means or, for example, a/B may represent a or B; the text "and/or" is merely an association relation describing the associated object, and indicates that three relations may exist, for example, a and/or B may indicate: in addition, in the description of the embodiments of the present utility model, "plural" means two or more, and other words and the like, it is to be understood that the preferred embodiments described herein are for illustration and explanation of the present utility model only, and are not intended to limit the present utility model, and embodiments of the present utility model and features in the embodiments may be combined with each other without conflict.
Referring to fig. 1-2, an embodiment of the present utility model provides a super capacitor charging and discharging circuit for improving the energy storage of a backup capacitor and delaying the power-down time of a system. As shown in fig. 1, a schematic structural diagram of a super capacitor charge-discharge circuit provided by the embodiment of the utility model includes a diode D1 and a first resistor R1 that are arranged in parallel, wherein a first common terminal between a cathode of the diode D1 and the first resistor R1 is connected with an output terminal, and a second common terminal between an anode of the diode D1 and the first resistor R1 is connected with a plurality of charge-discharge units that are sequentially connected in series.
In the utility model, each charge-discharge unit comprises a voltage dividing resistor, a field effect transistor, a current limiting resistor, a voltage stabilizing diode and a super capacitor, wherein one end of the voltage dividing resistor is connected with an input end, the other end of the voltage dividing resistor is connected with a grid electrode of the field effect transistor, a drain electrode of the field effect transistor is connected with an anode of the voltage stabilizing diode after passing through the current limiting resistor, the super capacitor is arranged between a cathode of the voltage stabilizing diode and a source electrode of the field effect transistor in parallel, an anode of the super capacitor is connected with a cathode of the voltage stabilizing diode, a cathode of the super capacitor is connected with the source electrode of the field effect transistor, and the source electrode of the field effect transistor arranged in the last charge-discharge unit in series is grounded.
Further, a bias resistor is further arranged in each charge-discharge unit, one end of the bias resistor is connected to a connection node between the voltage dividing resistor and the grid electrode of the field effect transistor, and the other end of the bias resistor is grounded.
Further, a second resistor R2 is further disposed in parallel between the first resistor R1 and the diode D1, and the diode D1 is a schottky diode.
IN the utility model, when the voltage VCC_IN of the input end is more than 0, namely when the voltage is applied to VCC_IN, the input end charges the super capacitor arranged IN each charge and discharge unit through the first resistor R1 and the second resistor R2; when the input terminal voltage vcc_in=0, that is, when the system is powered down, vcc_in is instantaneously zero, and the electric energy stored IN the super capacitors arranged IN the plurality of serially arranged charge and discharge units is sequentially supplied to the output terminal through the diode D1.
Referring to fig. 1, two serially connected charge and discharge units are shown, wherein the first charge and discharge unit includes a voltage dividing resistor R4, a field effect transistor Q1, a current limiting resistor R3, a zener diode D2, and a supercapacitor C1, one end of the voltage dividing resistor R4 is connected to an input end, the other end of the voltage dividing resistor R4 is connected to a gate of the field effect transistor Q1, a drain electrode of the field effect transistor Q1 is connected to an anode of the zener diode D2 after passing through the current limiting resistor R3, the supercapacitor C1 is arranged in parallel between a cathode of the zener diode D2 and a source electrode of the field effect transistor Q1, an anode of the supercapacitor C1 is connected to a cathode of the zener diode D2, a cathode of the supercapacitor C1 is connected to a source electrode of the field effect transistor Q1, one end of the supercapacitor R5 is connected to a connection node between the voltage dividing resistor R4 and the gate of the field effect transistor Q1, and the other end of the supercapacitor R5 is grounded.
The second charge-discharge unit comprises a voltage dividing resistor R7, a field effect transistor Q2, a current limiting resistor R6, a voltage stabilizing diode D3 and a super capacitor C2, wherein one end of the voltage dividing resistor R7 is connected with an input end, the other end of the voltage dividing resistor R7 is connected with the grid electrode of the field effect transistor Q2, the drain electrode of the field effect transistor Q2 is connected with the anode of the voltage stabilizing diode D3 after passing through the current limiting resistor R6, the super capacitor C2 is arranged between the cathode of the voltage stabilizing diode D3 and the source electrode of the field effect transistor Q2 in parallel, the anode of the super capacitor C2 is connected with the cathode of the voltage stabilizing diode D3, the source electrode of the field effect transistor Q2 is connected with the cathode of the super capacitor C2 and then grounded, the second charge-discharge unit further comprises a bias resistor R8, one end of the bias resistor R8 is connected with a connection node between the voltage dividing resistor R7 and the grid electrode of the field effect transistor Q2, and the other end of the bias resistor R8 is grounded.
Taking the two series-connected charge-discharge units as an example, when the voltage is applied to VCC_IN, the super capacitor C1 and the super capacitor C2 are charged through the first resistor R1 and the second resistor R2, the bias resistor R5 and the bias resistor R8 ensure that the driving voltage Vgs of the field-effect transistor Q1 and the field-effect transistor Q2 before the voltage is applied is pulled down, false triggering is prevented, and meanwhile, a release loop is provided at the moment of power failure, so that the field-effect transistor Q1 and the field-effect transistor Q2 are rapidly and reliably turned off, the voltage division resistor R4 and the bias resistor R5 form voltage division IN the first charge-discharge unit, and the driving voltage Vgs of the field-effect transistor Q1 is reduced; the voltage dividing resistor R7 and the bias resistor R8 constitute a voltage division in the second charge-discharge unit, and the driving voltage Vgs of the field-effect transistor Q2 is reduced.
Specifically, when the system is powered on, namely the input end voltage VCC_IN is more than 0, the driving voltage Vgs of the field effect transistor Q1 and the field effect transistor Q2 is more than a specified value, the field effect transistor Q1 and the field effect transistor Q2 are conducted at the moment, the voltage stabilizing diode D2 and the voltage stabilizing diode D3 respectively stabilize the super capacitor C1 and the super capacitor C2, the charging voltage is not too high, meanwhile, the super capacitor C1 and the super capacitor C2 are subjected to voltage equalizing and current equalizing, the current limiting resistor R3 and the current limiting resistor R6 are the current limiting resistors of the voltage stabilizing diode D2 and the voltage stabilizing diode D3 respectively, and damage caused by overlarge current of the voltage stabilizing diode is prevented.
Referring to fig. 2, a schematic structural diagram of a supercapacitor discharging process IN a supercapacitor charging and discharging circuit according to an embodiment of the present utility model is shown, when a system is powered down, i.e. when an input terminal voltage vcc_in=0, a field effect transistor Q1 and a field effect transistor Q2 are turned off instantaneously, but IN practical application, the resistance values of the first resistor R1 and the second resistor R2 are preferably set to 10Ω, at this time, electric energy stored IN the supercapacitor C1 and the supercapacitor C2 can only supply power to an output terminal through a diode D1, and IN the whole power supply process, the electric energy stored IN the supercapacitor C1 and the supercapacitor C2 is not consumed through the first resistor R1 and the second resistor R2, so that power consumption of the whole system is greatly reduced, and meanwhile, a circuit formed by the voltage stabilizing diode D2, the current limiting resistor R3, the field effect transistor Q1, the voltage stabilizing diode D3, the current limiting resistor R6 and the field effect transistor Q2 is not consumed, so that the utilization rate of the supercapacitor C1 and the supercapacitor C2 is further improved.
Of course, in order to increase the capacity of the super capacitor, we can continue to serially connect the charge and discharge units with the same structure, and increase the super capacitors C3 and C4, but it is necessary to ensure that the source of the field effect transistor disposed in the last serial charge and discharge unit is grounded, and the rest of the circuit structure is not described in detail herein.
According to the super capacitor charging and discharging circuit provided by the utility model, the super capacitor is used as a standby power supply by arranging the plurality of charging and discharging units, and the power supply is powered by the plurality of super capacitors connected in series after the power supply is powered off, so that the energy storage of the super capacitor is improved, the power-down time of a system is delayed, and the system data can be stored in time.
In the several embodiments provided in the present utility model, it should be understood that the disclosed apparatus, device and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model.
Claims (7)
1. The super capacitor charging and discharging circuit is characterized by comprising a diode D1 and a first resistor R1 which are arranged in parallel, wherein a first common end between the cathode of the diode D1 and the first resistor R1 is connected with an output end, and a second common end between the anode of the diode D1 and the first resistor R1 is connected with a plurality of charging and discharging units which are sequentially connected in series;
each charge-discharge unit comprises a voltage dividing resistor, a field effect transistor, a current limiting resistor, a voltage stabilizing diode and a super capacitor; one end of the divider resistor is connected with the input end, the other end of the divider resistor is connected with the grid electrode of the field effect transistor, the drain electrode of the field effect transistor is connected with the anode of the voltage stabilizing diode after passing through the current limiting resistor, and the super capacitor is arranged between the cathode of the voltage stabilizing diode and the source electrode of the field effect transistor in parallel; and the source electrode of the field effect transistor arranged in the last series-connected charge and discharge unit is grounded.
2. The super capacitor charge-discharge circuit as set forth in claim 1, wherein each of said charge-discharge cells is further provided therein with a bias resistor, one end of said bias resistor is connected to a connection node between said voltage dividing resistor and said field effect transistor gate, and the other end of said bias resistor is grounded.
3. The super capacitor charge-discharge circuit as claimed in claim 2, wherein a second resistor R2 is further arranged in parallel between the first resistor R1 and the diode D1.
4. A supercapacitor charge-discharge circuit according to claim 3, wherein in each of the charge-discharge cells, a positive electrode of the supercapacitor is connected to a cathode of the zener diode, and a negative electrode of the supercapacitor is connected to a source of the fet.
5. The super capacitor charge and discharge circuit of claim 4, wherein,
when the voltage of the input end is more than 0, the input end charges the super capacitor arranged in each charge-discharge unit after passing through the first resistor R1 and the second resistor R2;
when the input terminal voltage=0, the electric energy stored by the super capacitor arranged in the charge and discharge units arranged in series sequentially supplies power to the output terminal through the diode D1.
6. A supercapacitor charge-discharge circuit according to claim 3, wherein the first resistor R1 and the second resistor R2 have a resistance of 10Ω.
7. The supercapacitor charge-discharge circuit according to claim 1, wherein the diode D1 is a schottky diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320351405.4U CN219918483U (en) | 2023-03-01 | 2023-03-01 | Super capacitor charging and discharging circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320351405.4U CN219918483U (en) | 2023-03-01 | 2023-03-01 | Super capacitor charging and discharging circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219918483U true CN219918483U (en) | 2023-10-27 |
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ID=88467417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320351405.4U Active CN219918483U (en) | 2023-03-01 | 2023-03-01 | Super capacitor charging and discharging circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219918483U (en) |
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2023
- 2023-03-01 CN CN202320351405.4U patent/CN219918483U/en active Active
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