CN219872365U - Field programmable gate array circuit - Google Patents
Field programmable gate array circuit Download PDFInfo
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- CN219872365U CN219872365U CN202320180643.3U CN202320180643U CN219872365U CN 219872365 U CN219872365 U CN 219872365U CN 202320180643 U CN202320180643 U CN 202320180643U CN 219872365 U CN219872365 U CN 219872365U
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Abstract
The utility model discloses a field programmable gate array circuit, comprising: the device comprises a controller, an FPGA chip, a memory chip and a switcher; the memory chip is used for storing a control program; the switch is connected to the controller, the FPGA chip and the storage chip, wherein the FPGA chip is connected to the storage chip through the switch; wherein, in the control program downloading or updating stage, the controller controls the switcher to connect the memory chip to the controller to download or update the control program; in a default stage, the controller controls the switcher to connect the storage chip to the FPGA chip so as to enable the FPGA chip to automatically load the control program for running. According to the scheme, the storage chip is arranged outside the FPGA chip, the connection relation between the storage chip and the FPGA chip and the connection relation between the storage chip and the controller are switched through the switcher, and the FPGA chip and the storage chip are not directly connected, so that the storage chip is not influenced by the pin level on the FPGA chip when the program is downloaded or updated, and the success rate of the program downloading or updating can be improved.
Description
Technical Field
The disclosed embodiments of the present utility model relate to the field of FPGA technology, and more particularly, to field programmable gate array circuits.
Background
A field programmable gate array (Field Program Gate Array, FPGA) is an integrated circuit that supports reprogramming, but because it generally does not have a storage medium, it requires a scalable memory chip.
In general, after the memory chip is expanded on the FPGA chip, the controller controls the program in the memory chip to be downloaded or updated, and then the FPGA automatically operates the program in the memory chip, however, the program in the expanded memory chip is affected by the pin level on the FPGA, so that the success rate of the program download or update is reduced.
Thus, the present utility model has been made to solve the problem of low success rate of program download or update in the prior art.
Disclosure of Invention
According to the embodiment of the utility model, the utility model provides a field programmable gate array circuit to solve the problem of program downloading or updating success rate in the prior art.
The utility model discloses a field programmable gate array circuit, comprising: the device comprises a controller, an FPGA chip, a memory chip and a switcher; the memory chip is used for storing a control program; the switch is connected to the controller, the FPGA chip and the storage chip, wherein the FPGA chip is connected to the storage chip through the switch; wherein, in the control program downloading or updating stage, the controller controls the switcher to connect the memory chip to the controller to download or update the control program; and in a default stage, the controller controls the switcher to connect the storage chip to the FPGA chip so that the FPGA chip automatically loads the control program to operate.
According to the scheme, the storage chip is arranged outside the FPGA chip, the connection relation between the storage chip and the FPGA chip and the connection relation between the storage chip and the controller are switched through the switcher, and the FPGA chip and the storage chip are not directly connected, so that the storage chip is not influenced by the pin level on the FPGA chip when the program is downloaded or updated, and the success rate of the program downloading or updating can be improved.
The controller comprises a first control pin, the FPGA chip comprises a second control pin, and the first control pin of the controller is connected with the second control pin of the FPGA chip; and in response to the FPGA circuit operating in the default stage, the controller enables the second control pin of the FPGA chip to operate in a first state through the first control pin, and the FPGA chip loads the control program from the storage chip.
According to the scheme, the controller is connected to the second control pin of the FPGA chip through the first control pin, so that the FPGA chip can automatically load and operate a control program in a default stage, and the efficiency is improved.
Wherein the first state is a logic low state.
The controller comprises a first feedback pin, the FPGA chip comprises a second feedback pin, and the first feedback pin of the controller is connected with the second feedback pin of the FPGA chip; and in response to the FPGA circuit operating in the default stage, the controller determines whether the FPGA chip loads the loading state of the control program based on the feedback signal on the first feedback pin.
According to the scheme, the first feedback pin of the controller is connected with the second feedback pin of the FPGA chip, and the FPGA chip can feed back the loading state of the control program to the controller, so that the efficiency is further improved.
Wherein, in response to the feedback signal on the first feedback pin being at a first working level, the controller determines that the FPGA chip successfully loaded the control program; and in response to the feedback signal on the first feedback pin being at a second working level, the controller determines that the FPGA chip has not successfully loaded the control program.
Wherein the first working level is a logic high level; the second operating level is a logic low level.
The storage chip comprises a first storage unit and a second storage unit, wherein the first storage unit is used for storing a backup control program, and the second storage unit is used for storing an application control program.
According to the scheme, different programs are stored in the storage chip, and after the program is downloaded or updated, the FPGA chip can still load the backup control program to realize normal operation, so that the problem that the system cannot normally operate due to the program downloading or updating failure is avoided, and the efficiency is further improved.
Wherein, the backup control program is a control program which is not downloaded or updated before the program downloading or updating stage is carried out; the application control program is a control program which is downloaded or updated after the program downloading or updating stage is carried out.
According to the scheme, different programs are stored in the storage chip, and after the program is downloaded or updated, the FPGA chip can still load the backup control program to realize normal operation, so that the problem that the system cannot normally operate due to the program downloading or updating failure is avoided, and the efficiency is further improved.
The switch comprises a switching chip and a Schmitt trigger, wherein the switching chip is connected to the controller, the FPGA chip and the storage chip, and the switching chip is also connected to the controller through the Schmitt trigger.
The switching chip further comprises a first enabling pin and a second enabling pin, and the controller further comprises a third control pin; the first enable pin is connected to a third control pin of the controller through the schmitt trigger, and the second enable pin is connected to the third control pin of the controller.
Drawings
The utility model will be further described with reference to the accompanying drawings and embodiments, in which:
FIG. 1 is a schematic diagram of a frame structure of an FPGA circuit of the present utility model;
fig. 2 is a schematic diagram of a switch according to the present utility model.
Detailed Description
In order to make the technical scheme of the present utility model better understood by those skilled in the art, the technical scheme of the present utility model will be further described in detail with reference to the accompanying drawings and the detailed description.
Specific terms are used throughout the specification to refer to specific components. As will be appreciated by those skilled in the art, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "comprise" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to.
The following description is of the best contemplated mode of carrying out the utility model. This description is made for the purpose of illustrating the general principles of the utility model and is not meant to be limiting. The scope of the utility model is determined by the appended claims.
The utility model discloses a field programmable gate array (Field Program Gate Array, FPGA) circuit, please refer to FIG. 1, FIG. 1 is a schematic diagram of a frame structure of the FPGA circuit of the utility model; specifically, the FPGA circuit includes: a controller 10, an FPGA chip 20, a memory chip 30, and a switcher 40; the memory chip 30 is used for storing a control program; the switch 40 is connected to the controller 10, the FPGA chip 20, and the memory chip 30, wherein the FPGA chip 20 is connected to the memory chip 30 through the switch 40; wherein, in the control program downloading or updating stage, the controller 10 controls the switcher 40 to connect the memory chip 30 to the controller 10 to download or update the control program; at the default stage, the controller 10 controls the switch 40 to connect the memory chip 30 to the FPGA chip 20 so that the FPGA chip 20 automatically loads the control program to operate.
In the above-mentioned scheme, the memory chip 30 is externally arranged on the FPGA chip 20, the connection relationship between the memory chip 30 and the FPGA chip 20 and the controller 10 is switched by the switch 40, and the FPGA chip 20 and the memory chip 30 are not directly connected, so that the memory chip 30 is not affected by the pin level on the FPGA chip 20 when the program is downloaded or updated, and the success rate of the program download or update can be improved.
In a specific implementation scenario, the FPGA chip 20 may adopt an MSPI mode, the memory chip 30 is used for storing a control program that the FPGA chip 20 needs to operate, the FPGA chip 20 and the memory chip 30 are respectively connected to the switch 40, and the switch 40 is responsible for switching on a hardware connection, that is, the memory chip 30 is controlled to be respectively connected to the controller 10 or the FPGA chip 20 at different stages; in a default phase, the memory is connected to the FPGA chip 20, and the FPGA chip 20 can automatically load and operate the control program in the memory chip 30; when the program needs to be updated or downloaded online, the controller 10 controls the memory chip 30 to be connected to the controller 10 through the switcher 40, so that the memory chip 30 can update or download the control program online; after the control program is downloaded or updated on line, the controller 10 controls the storage chip 30 to disconnect from the controller 10 and restore the connection between the storage chip 30 and the FPGA chip 20 through the switch 40, and the FPGA chip 20 automatically loads and runs the control program in the storage chip 30.
In a possible embodiment, please continue to refer to fig. 1, the controller 10 includes a first control pin K1, the FPGA chip 20 includes a second control pin K2, wherein the first control pin K1 of the controller 10 is connected to the second control pin K2 of the FPGA chip 20; in response to the FPGA circuit operating in the default phase, the controller 10 operates the second control pin K2 of the FPGA chip 20 in the first state through the first control pin K1, and the FPGA chip 20 loads the control program from the memory chip 30.
In one possible implementation, the first state is a logic low state; in other possible implementations, the first state may also be a logic high state.
In a specific implementation scenario, when downloading or online updating of the control program is required, the controller 10 controls the switch to connect the storage chip 30 to the controller 10, the storage chip 30 performs downloading and online updating of the control program, after the downloading or online updating is completed, a default stage is entered, the controller 10 controls the switch to connect the storage chip 30 to the FPGA chip 20, a logic low level is output on the first control pin K1 of the controller 10, and after the second control pin K2 of the FPGA chip 20 receives the logic low level, the FPGA chip 20 automatically loads the downloaded or online updated control program to run.
In the above scheme, the controller 10 is connected to the second control pin of the FPGA chip 20 through the first control pin, so that the FPGA chip 20 can automatically load and operate the control program in a default stage, thereby improving efficiency.
In one possible embodiment, the controller 10 includes a first feedback pin F1, and the FPGA chip 20 includes a second feedback pin F2, wherein the first feedback pin F1 of the controller 10 is connected to the second feedback pin F2 of the FPGA chip 20; in response to the FPGA circuit operating in the default phase, the controller 10 determines whether the FPGA chip 20 is loaded with the loading state of the control program based on the feedback signal on the first feedback pin F1.
In one possible implementation, in response to the feedback signal on the first feedback pin F1 being at the first operating level, the controller 10 determines that the FPGA chip 20 successfully loaded the control program; in response to the feedback signal on the first feedback pin F1 being at the second operating level, the controller 10 determines that the FPGA chip 20 did not successfully load the control program.
In one possible implementation, the first operating level is a logic high level; the second operating level is a logic low level.
In a specific implementation scenario, during the default phase, the FPGA chip 20 automatically loads the control program, if the control program fails to load, the second feedback pin F2 outputs a logic low level, the first feedback pin F1 receives the logic low level, and the controller 10 determines that the FPGA chip 20 fails to load the control program.
In the above scheme, the first feedback pin of the controller 10 is connected with the second feedback pin of the FPGA chip 20, so that the FPGA chip 20 can feed back the loading state of the control program to the controller 10, thereby further improving the efficiency.
In one possible embodiment, please continue to refer to fig. 1, the memory chip 30 includes a first memory unit 31 and a second memory unit 32, where the first memory unit 31 is used for storing a backup control program, and the second memory unit 32 is used for storing an application control program; in other possible embodiments, the memory chip 30 may further include more memory units for storing other control programs, which are not limited herein.
In one possible embodiment, the backup control program is a control program that has not been downloaded or updated before the program download or update phase is performed; the application control program is a control program which has been downloaded or updated after the program download or update stage.
In a specific implementation scenario, when downloading or online updating of the control program is required, the controller 10 controls the switcher 40 to connect the memory chip 30 to the controller 10, the memory chip 30 performs downloading and online updating of the control program, after the downloading or online updating is completed, a default stage is entered, the controller 10 controls the switcher 40 to connect the memory chip 30 to the FPGA chip 20, a logic low level is output on the first control pin K1 of the controller 10, and after the second control pin K2 of the FPGA chip 20 receives the logic low level, the FPGA chip 20 automatically loads the downloaded or online updated control program to operate; if the control program fails to be loaded, the second feedback pin F2 outputs a logic low level, the first feedback pin F1 receives the logic low level, and the controller 10 further determines that the FPGA chip 20 fails to load the control program, so as to solve the problem that the control program cannot be normally operated due to the failure of downloading or online updating, the storage chip 30 may be divided into two storage units for storing the control program before updating and the control program after updating respectively, and if the FPGA chip 20 cannot load and operate the control program after updating, the control program before updating is loaded and operated; if the control program is successfully loaded, the second feedback pin F2 outputs a logic high level, and the first feedback pin F1 receives the logic high level, so that the controller 10 determines that the FPGA chip 20 is successfully loaded with the control program, and the backup control program stored in the first storage unit 31 can be updated.
In the above scheme, different programs are stored in the memory chip 30, and after the program download or update fails, the FPGA chip 20 can still load the backup control program to realize normal operation, so as to avoid the system from being unable to operate normally due to the program download or update failure, thereby further improving the efficiency.
In some possible implementations, the FPGA chip 20 is also connected to the controller 10 by a first bus; information interaction can be performed between the FPGA chip 20 and the controller 10 through a first bus; in one particular implementation, the first bus may be a local bus.
In one possible embodiment, referring to fig. 2, fig. 2 is a schematic structural diagram of the switch of the present utility model; specifically, the switcher 40 includes a switching chip U1 and a schmitt trigger U2, the switching chip U1 is connected to the controller 10, the FPGA chip 20, and the memory chip 30, and the switching chip U1 is also connected to the controller 10 through the schmitt trigger U2; when connection switching is required, the switching chip U1 can realize connection switching between the memory chip 30 and the controller 10 or the FPGA chip 20.
In a specific implementation scenario, the switching chip U1 may be designed using a 74LVC244 chip, so that the cost can be reduced and the efficiency can be improved.
In other possible implementation scenarios, the switch 40 may also use an analog switch circuit to implement a connection switching function between the memory chip 30 and the controller 10 and FPGA chip 20; for example, the analog switch circuit may include a first switch path and a second switch path, where the memory chip 30 is connected to the controller 10 and the FPGA chip 20 through the first switch path and the second switch path, and when the connection needs to be switched, the first switch path and the second switch path may be controlled to be turned on or off, and only one of the first switch path and the second switch path is turned on or off at the same time; in addition, the switch 40 may take other forms, and the present utility model is not limited to the specific implementation of the switch 40.
In one possible implementation, the switching chip further includes a first enable pin EN1 and a second enable pin EN2, and the controller 10 further includes a third control pin K3; the first enable pin is connected to the third control pin K3 of the controller 10 through the schmitt trigger, and the second enable pin is connected to the third control pin K3 of the controller 10.
Those skilled in the art will readily appreciate that many modifications and variations are possible in the device and method while maintaining the teachings of the utility model. Accordingly, the above disclosure should be viewed as limited only by the scope of the appended claims.
Claims (10)
1. A field programmable gate array circuit, comprising:
a controller;
an FPGA chip;
a memory chip for storing a control program;
the switch is connected to the controller, the FPGA chip and the storage chip, wherein the FPGA chip is connected to the storage chip through the switch;
wherein, in the control program downloading or updating stage, the controller controls the switcher to connect the memory chip to the controller to download or update the control program; and in a default stage, the controller controls the switcher to connect the storage chip to the FPGA chip so that the FPGA chip automatically loads the control program to operate.
2. The circuit of claim 1, wherein the circuit comprises a plurality of capacitors,
the controller comprises a first control pin, the FPGA chip comprises a second control pin, and the first control pin of the controller is connected with the second control pin of the FPGA chip;
and in response to the FPGA circuit operating in the default stage, the controller enables the second control pin of the FPGA chip to operate in a first state through the first control pin, and the FPGA chip loads the control program from the storage chip.
3. The circuit of claim 2, wherein the circuit further comprises a logic circuit,
the first state is a logic low state.
4. The circuit of claim 1, wherein the circuit comprises a plurality of capacitors,
the controller comprises a first feedback pin, the FPGA chip comprises a second feedback pin, and the first feedback pin of the controller is connected with the second feedback pin of the FPGA chip;
and in response to the FPGA circuit operating in the default stage, the controller determines whether the FPGA chip loads the loading state of the control program based on the feedback signal on the first feedback pin.
5. The circuit of claim 4, wherein the circuit further comprises a logic circuit,
in response to the feedback signal on the first feedback pin being at a first operating level, the controller determines that the FPGA chip successfully loaded the control program;
and in response to the feedback signal on the first feedback pin being at a second working level, the controller determines that the FPGA chip has not successfully loaded the control program.
6. The circuit of claim 5, wherein the circuit further comprises a logic circuit,
the first working level is a logic high level; the second operating level is a logic low level.
7. The circuit of claim 1, wherein the memory chip comprises a first memory unit for storing a backup control program and a second memory unit for storing an application control program.
8. The circuit of claim 7, wherein the backup control program is a control program that was not downloaded or updated prior to the program download or update phase; the application control program is a control program which is downloaded or updated after the program downloading or updating stage is carried out.
9. The circuit of claim 1, wherein the switch comprises a switching chip and a schmitt trigger, the switching chip being connected to the controller, FPGA chip and memory chip, the switching chip also being connected to the controller through the schmitt trigger.
10. The circuit of claim 9, wherein the switching chip further comprises a first enable pin and a second enable pin, and the controller further comprises a third control pin; the first enable pin is connected to a third control pin of the controller through the schmitt trigger, and the second enable pin is connected to the third control pin of the controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320180643.3U CN219872365U (en) | 2023-02-10 | 2023-02-10 | Field programmable gate array circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320180643.3U CN219872365U (en) | 2023-02-10 | 2023-02-10 | Field programmable gate array circuit |
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| Publication Number | Publication Date |
|---|---|
| CN219872365U true CN219872365U (en) | 2023-10-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202320180643.3U Active CN219872365U (en) | 2023-02-10 | 2023-02-10 | Field programmable gate array circuit |
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| CN (1) | CN219872365U (en) |
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