CN112307697A - FPGA logic reloading circuit - Google Patents
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Abstract
The invention discloses an FPGA logic reloading circuit, which comprises: at least 2 flashes, 1 programmable logic circuit, at least 2 flashes are hung on the programmable logic circuit to backup each other, and a chip selection signal CS output by the FPGA is coupled between the flashes and the FPGA through the programmable logic circuit; the FPGA logic reloading circuit has 3 application modes: a logic loading mode, a logic online upgrading mode and a logic offline upgrading mode; the circuit realizes the functions of judging and reloading the logic loading state of the FPGA through the control logic in the CPLD, and can realize the function of upgrading the logic of the designated Flash in an online state and an offline state. The embodiment of the invention avoids the defect that the traditional FPGA logic storage and loading circuit can not normally complete the loading operation when a Flash chip fails or the upgrading and loading is abnormally interrupted.
Description
The technical field is as follows:
the present invention relates to, but not limited to, the field of computer hardware technologies, and in particular, to an FPGA logic reload circuit in a circuit system.
Background art:
in modern avionic product design, FPGAs are widely used for development and design of various embedded systems and modules. Because an avionic system has strict reliability requirements on the starting of an electronic module, the traditional electronic module designed based on the FPGA mostly adopts 1 Flash to provide logic storage and loading functions for an FPGA chip, and when the Flash chip fails, pins of the Flash chip are desoldered/bridged or abnormal power supply occurs in the logic upgrading and loading process, the situation that the FPGA cannot be normally loaded and the electronic module cannot work due to 'brick change' can be caused.
The invention content is as follows:
the purpose of the invention is: the embodiment of the invention provides an FPGA logic reloading circuit, which aims to solve the problem that the whole circuit cannot normally complete loading operation possibly caused by Flash chip failure or abnormal interruption of upgrading and loading in the traditional FPGA logic storing and loading circuit.
The technical solution of the invention is as follows: the embodiment of the invention provides an FPGA logic reloading circuit, which comprises: at least 2 flashes, 1 programmable logic circuit, wherein the at least 2 flashes are hung on the programmable logic circuit and are backups for each other;
clock signals CLK, data signals, address signals and control signals of the at least 2 Flash chips are connected to the FPGA in a multiplexing connection mode, and chip selection signals CS output by the FPGA are coupled between the Flash chips and the FPGA through a programmable logic circuit; the FPGA logic reloading circuit has 3 application modes: a logic loading mode, a logic online upgrading mode and a logic offline upgrading mode;
the FPGA logic reloading circuit is used for controlling the loading process of 2 flashes through the programmable logic circuit, so that the judging and reloading functions of the FPGA logic loading state are controlled through the control logic in the programmable logic circuit in a logic loading mode, the logic upgrading function of the specified Flash in an online state is realized in a logic online upgrading mode, and the logic upgrading function of the specified Flash in an offline state is realized in a logic offline upgrading mode.
Optionally, in the FPGA logic reload circuit as described above,
in the FPGA logic reloading circuit, a logic loading signal ROGRAM _ B of the FPGA and a logic loading completion signal DONE of the FPGA are both connected to the programmable logic circuit;
the input signals of the programmable logic circuit comprise: a chip select signal CS, an online upgrade enable signal EN _ online _ upgrade, an online upgrade Flash select signal SEL _ online _ Flash, the DONE, and a start load signal INIT _ B input by the FPGA, and an offline upgrade enable signal EN _ offflash _ upgrade, an offline upgrade Flash select signal SEL _ offflash, a time set signal TimeSet1, and a TimeSet2 input by an external driver;
the output signals of the programmable logic circuit include: a logic loading signal PROGRAM _ B output to the FPGA, and a strobe signal CS1 output to one of the flashes and a strobe signal CS2 output to the other Flash.
Optionally, in the FPGA logic reload circuit as described above,
the mode for controlling the logic loading state judgment and the reloading function of the FPGA in the logic loading mode comprises the following steps: and the FPGA defaults to load logic from one Flash, and if the FPGA is not normally started after a loading period, the loading signal CS is gated to the other Flash through the control logic of the programmable logic circuit, and the FPGA is forced to start a new loading sequence.
Optionally, in the FPGA logic reload circuit as described above,
the mode for realizing the logic upgrading function of the specified Flash in the online state in the logic online upgrading mode comprises the following steps: in the power-on process, a logic online upgrading mode is enabled by enabling an online upgrading enabling signal EN _ online _ upgrade, a Flash to be upgraded is selected by controlling an online upgrading Flash selection signal SEL _ online _ Flash, and the programmable logic circuit executes online upgrading operation on the selected Flash by judging the signals.
Optionally, in the FPGA logic reload circuit as described above,
the mode for realizing the logic upgrading function of the designated Flash in the off-line state in the logic off-line upgrading mode comprises the following steps: in the power-on process, a logic off-line upgrading mode is enabled by enabling an off-line upgrading enabling signal EN _ offline _ upgrade, a Flash to be upgraded is selected by controlling an off-line upgrading Flash selection signal SEL _ offline _ Flash, and the programmable logic circuit executes off-line upgrading operation on the selected Flash by judging the signals.
Optionally, in the FPGA logic reload circuit, the control logic in the programmable logic circuit is: the loading process of the FPGA is controlled through the programmable logic circuit, and the redundancy design, configurable upgrading and loading dynamic switching functions of the loading circuit are realized;
the control logic control architecture of the programmable logic circuit comprises: the device comprises a mode selection control unit, a timer unit, a loading control unit and a chip selection control unit.
Optionally, in the FPGA logic reload circuit as described above,
the mode selection control unit in the programmable logic circuit is used for judging and outputting the chip selection gating control signal CS _ Ctrl according to the states of an online upgrading enabling signal EN _ online _ upgrade, an offline upgrading enabling signal EN _ offline _ upgrade, an online upgrading Flash selection signal SEL _ online _ Flash, an offline upgrading enabling signal EN _ offline _ upgrade and a TimeOut signal Timeout.
Optionally, in the FPGA logic reload circuit as described above,
the timer unit in the programmable logic circuit is used for setting corresponding loading time timeout values to be 300ms, 500ms, 1s and 2s respectively through values '00', '01', '10' and '11' of time setting signals TimeSet1 and TimeSet2, and starting to time after a loading starting signal INIT _ B is effective;
if the FPGA logic loading completion signal DONE is not valid before the TimeOut time is reached, the output TimeOut signal TimeOut is '1';
if the FPGA logic loading completion signal DONE is valid before the TimeOut time is reached, the output TimeOut signal TimeOut is '0';
and the timer unit is also used for judging the state of the received Reload signal Reload output by the load control unit to restart timing under the condition of load timeout.
Optionally, in the FPGA logic reload circuit as described above,
and the loading control unit in the programmable logic circuit is used for outputting a low pulse to start an FPGA reloading process by judging the state of the TimeOut signal Timeout when the loading is overtime, namely the Timeout output by the timer unit is '1', and outputting a reloading signal Reload to the timer unit.
Optionally, in the FPGA logic reload circuit as described above,
the chip selection control unit in the programmable logic circuit is used for executing the gating operation from the chip selection signal CS output by the PPGA to the gating chip selection signals CS1 and CS2 of the 2 Flash chips according to the chip selection gating control signal CS _ Ctrl output by the mode selection control unit; when CS _ Ctrl is '0', the output is gated with CS1, and CS2 has no output; when CS _ Ctrl is '1', the output is gated CS2, and CS1 has no output.
The invention has the advantages that:
according to the FPGA logic reloading circuit provided by the embodiment of the invention, the FPGA logic storage loading circuit adopts a design that at least 2 flashes are mutual backups, 1 CPLD is used for controlling the loading process of the 2 FPGAs, CLK clock signals, data signals, address signals and control signals of the 2 Flash chips are connected to the FPGA in a multiplexing connection mode, and chip selection signals (CS) output by the FPGA are coupled between the flashes and the FPGA through the CPLD. The FPGA logic reloading circuit realizes the functions of judging and reloading the logic loading state of the FPGA through the control logic in the CPLD and can realize the function of upgrading the logic of the designated Flash in an online state and an offline state. In addition, the FPGA logic reloading circuit provided by the embodiment of the invention has the following advantages:
1) and the reliability is high: the logic storage backup design is used for automatically judging the loading state of the FPGA and ensuring that the logic reloading operation is executed under the condition of abnormal loading;
2) and the working mode can be set as follows: the current working mode can be set as a logic loading mode or a logic upgrading mode;
3) and setting various logic upgrading modes: the logic upgrading function of the designated Flash under the conditions of online and offline is supported;
4) and the compatibility is good: the method is suitable for the reliability design of logic loading circuits of various types of FPGAs.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic structural diagram of an FPGA logic reload circuit diagram for executing a method for reloading FPGA logic according to an embodiment of the present invention;
fig. 2 is a diagram of a CPLD logic control architecture in a circuit diagram for reloading FPGA logic provided in the embodiment shown in fig. 1.
The specific implementation mode is as follows:
in order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The invention provides an FPGA logic reloading circuit and a logic reloading method thereof aiming at the defect that the traditional FPGA logic storing and loading circuit can not normally complete the loading operation when a Flash chip fails or the upgrading and loading is abnormally interrupted, and realizes the redundant design, configurable upgrading and loading dynamic switching functions of the FPGA logic storing and loading circuit, thereby avoiding the situation that the FPGA logic can not normally complete the loading due to the current Flash chip failure of logic storage or the abnormal interruption of the upgrading and loading, and improving the reliability of a module and a system.
The following specific embodiments of the present invention may be combined, and the same or similar concepts or processes may not be described in detail in some embodiments.
Fig. 1 is a schematic structural diagram of an FPGA logic reload circuit according to an embodiment of the present invention. The embodiment of the invention uses 1 CPLD to control the loading process of the FPGA, such as the FPGA logic reloading circuit and related signals shown in figure 1. In the FPGA logic reloading circuit in the embodiment of the invention, a logic loading signal of the FPGA is connected to the CPLD, 2 FLASH chips are connected to the CPLD for mutual backup, a clock signal CLK, a data signal, an address signal and a control signal of the 2 FLASH chips are connected to the FPGA in a multiplexing connection mode, and a chip selection signal CS output by the FPGA is coupled between the FLASH and the FPGA through a programmable logic circuit. The input signal of the CPLD specifically includes: CS, EN _ online _ update, EN _ offline _ update, SEL _ online _ flash, SEL _ offline _ flash, TimeSet1, TimeSet2, DONE, INIT _ B signals, the output signals including: PROGRAM _ B, CS1, CS2 signal.
The application mode of the FPGA logic reloading circuit comprises the following steps: a logic loading mode, a logic online upgrading mode and a logic offline upgrading mode.
The FPGA logic reloading circuit provided by the embodiment of the invention can control the loading process of 2 flashes through the programmable logic circuit, thereby controlling the judging and reloading functions of the FPGA logic loading state in a logic loading mode through the control logic in the programmable logic circuit, realizing the logic upgrading function of a specified Flash in an online state in a logic online upgrading mode, and realizing the logic upgrading function of the specified Flash in an offline state in a logic offline upgrading mode.
In the FPGA logic reloading circuit of the embodiment of the invention, a logic loading signal ROGRAM _ B of the FPGA and a logic loading completion signal DONE of the FPGA are both connected to a programmable logic Circuit (CPLD);
the input signal of the programmable logic Circuit (CPLD) comprises: the system comprises a chip selection signal CS input by FPGA, an online upgrade enable signal EN _ online _ upgrade, an online upgrade Flash selection signal SEL _ online _ Flash, the DONE, a start loading signal INIT _ B, an offline upgrade enable signal EN _ offline _ upgrade, an offline upgrade Flash selection signal SEL _ offline _ Flash, a time setting signal TimeSet1 and a TimeSet2, wherein the chip selection signal CS, the online upgrade enable signal EN _ online _ upgrade, the online upgrade Flash selection signal SEL _ online _ Flash, the DONE, the start loading signal INIT _ B and the offline upgrade enable signal EN _ offline _ upgrade, the offline upgrade Flash selection signal.
The output signal of the programmable logic Circuit (CPLD) comprises: a logic loading signal PROGRAM _ B output to the FPGA, and a strobe signal CS1 output to one of the flashes and a strobe signal CS2 output to the other Flash.
The following describes the loading method of the application mode in 3:
the logic loading mode is as follows: and the FPGA loads logic from one Flash by default, and after one loading period, if the FPGA is not started normally, the CPLD gates a loading signal to the other Flash through the control logic and forces the FPGA to start a new loading sequence.
The logic online upgrading mode is as follows: in the power-on process, an online upgrade mode is enabled by enabling an online upgrade enabling signal EN _ online _ upgrade, in practical application, '1' can be defined as enabling/'0' as forbidden, and the online upgrade needs to be forbidden after the online upgrade operation is completed; and selecting the upgraded FLASH by controlling an 'online upgrade Flash selection' signal SEL _ online _ Flash, wherein the CPLD executes online upgrade operation by judging the signals, and the definition of a mode state truth table is shown in a table 1.
The logic off-line upgrading mode is as follows: in the power-on process, an off-line upgrade mode is enabled by enabling an off-line upgrade enabling signal EN _ offline _ upgrade, and in practical application, '1' can be defined as enabling/'0' as forbidden and default is pull-down; and selecting the upgraded FLASH by controlling an off-line upgrading Flash selection signal SEL _ offflash _ Flash, wherein the CPLD executes off-line upgrading operation by judging the signals, and the mode state truth table is defined as shown in the table 1.
TABLE 1 mode State truth table
The loading process of the FPGA is controlled through the CPLD, and the functions of redundancy design, configurable upgrading and dynamic loading switching of the loading circuit are realized. As shown in fig. 2, which is a schematic diagram of a CPLD logic control architecture in the embodiment of the present invention, the control logic of the CPLD is: the loading process of the FPGA is controlled through a programmable logic circuit, the redundancy design, configurable upgrading and loading dynamic switching functions of a loading circuit are realized, and the logic control architecture of the CPLD comprises the following steps: a mode selection control unit, a timer unit, a loading control unit and a chip selection control unit. The following description is made in conjunction with input/output signals and specific operations.
(1) Mode selection control unit
Defining a mode state truth table as shown in table 1, the mode selection control unit judges and outputs a chip selection gating control signal CS _ Ctrl according to states of an online upgrade enable signal EN _ online _ upgrade, an offline upgrade enable signal EN _ offline _ upgrade, an online upgrade Flash select signal SEL _ online _ Flash, an offline upgrade enable signal EN _ offline _ upgrade and a TimeOut signal TimeOut;
(2) timer unit
The timer unit sets corresponding loading time TimeOut values through values ('00', '01', '10', '11') of a 'time setting signal' TimeSet1/TimeSet2, for example, 300ms, 500ms, 1s, and 2s, respectively, starts timing after a 'start loading signal' INIT _ B is valid ('1' is valid), outputs a 'TimeOut signal' outtime to '1' if a 'FPGA logic loading completion signal' DONE is not valid ('1' is valid, '0' is invalid) before the TimeOut time is reached, and otherwise outputs '0', and determines that the timing is restarted by determining a state of a received 'Reload signal' Reload ('1' is valid) output by the loading control unit.
(3) Load control unit
And the loading control unit judges the state of a 'TimeOut signal' TimeOut, outputs a low pulse (default is external pull-up processing) to a 'logic loading signal' PROGRAM _ B to start the FPGA reloading process when the loading is overtime, namely the TimeOut output by the timer unit is '1', and simultaneously outputs a 'Reload signal' Reload ('1' is effective) to the timer unit.
(4) Chip selection control unit
And the chip selection control unit realizes the gating from the chip selection signal CS output by the PPGA to the chip selection signals CS1 and CS2 of the 2 Flash chips according to the chip selection gating control signal CS _ Ctrl output by the mode selection control unit, and the mode selection gating control unit is specifically defined in a mode state truth table in Table 1. When CS _ Ctrl is '0', the output is gated CS1, and CS2 has no output; when CS _ Ctrl is '1', the output is gated CS2, and CS1 has no output.
According to the FPGA logic reloading circuit provided by the embodiment of the invention, the FPGA logic storage loading circuit adopts a design that at least 2 flashes are mutual backups, 1 CPLD is used for controlling the loading process of the 2 FPGAs, CLK clock signals, data signals, address signals and control signals of the 2 Flash chips are connected to the FPGA in a multiplexing connection mode, and chip selection signals (CS) output by the FPGA are coupled between the flashes and the FPGA through the CPLD. The FPGA logic reloading circuit realizes the functions of judging and reloading the logic loading state of the FPGA through the control logic in the CPLD and can realize the function of upgrading the logic of the designated Flash in an online state and an offline state. In addition, the reliability of the FPGA logic reloading circuit of the embodiment of the invention is high: the logic storage backup design is used for automatically judging the loading state of the FPGA and ensuring that the logic reloading operation is executed under the condition of abnormal loading; the working mode can be set as follows: the current working mode can be set as a logic loading mode or a logic upgrading mode; setting a plurality of logic upgrading modes: the logic upgrading function of the designated Flash under the conditions of online and offline is supported; the compatibility is good: the method is suitable for the reliability design of logic loading circuits of various types of FPGAs.
By adopting the FPGA logic reloading circuit provided by the embodiment of the invention, the defect that the traditional FPGA logic storage and loading circuit cannot normally complete loading operation when a Flash chip fails or the upgrading and loading is abnormally interrupted can be avoided, the redundancy design and the configurable upgrading and loading dynamic switching function of the FPGA logic storage and loading circuit are realized, and the reliability of a module and a system is improved.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An FPGA logic reload circuit, comprising: at least 2 flashes, 1 programmable logic circuit, wherein the at least 2 flashes are hung on the programmable logic circuit and are backups for each other;
clock signals CLK, data signals, address signals and control signals of the at least 2 Flash chips are connected to the FPGA in a multiplexing connection mode, and chip selection signals CS output by the FPGA are coupled between the Flash chips and the FPGA through a programmable logic circuit; the FPGA logic reloading circuit has 3 application modes: a logic loading mode, a logic online upgrading mode and a logic offline upgrading mode;
the FPGA logic reloading circuit is used for controlling the loading process of 2 flashes through the programmable logic circuit, so that the judging and reloading functions of the FPGA logic loading state are controlled through the control logic in the programmable logic circuit in a logic loading mode, the logic upgrading function of the specified Flash in an online state is realized in a logic online upgrading mode, and the logic upgrading function of the specified Flash in an offline state is realized in a logic offline upgrading mode.
2. The FPGA logic reload circuit of claim 1,
in the FPGA logic reloading circuit, a logic loading signal ROGRAM _ B of the FPGA and a logic loading completion signal DONE of the FPGA are both connected to the programmable logic circuit;
the input signals of the programmable logic circuit comprise: a chip select signal CS, an online upgrade enable signal EN _ online _ upgrade, an online upgrade Flash select signal SEL _ online _ Flash, the DONE, and a start load signal INIT _ B input by the FPGA, and an offline upgrade enable signal EN _ offflash _ upgrade, an offline upgrade Flash select signal SEL _ offflash, a time set signal TimeSet1, and a TimeSet2 input by an external driver;
the output signals of the programmable logic circuit include: a logic loading signal PROGRAM _ B output to the FPGA, and a strobe signal CS1 output to one of the flashes and a strobe signal CS2 output to the other Flash.
3. The FPGA logic reload circuit of claim 2,
the mode for controlling the logic loading state judgment and the reloading function of the FPGA in the logic loading mode comprises the following steps: and the FPGA defaults to load logic from one Flash, and if the FPGA is not normally started after a loading period, the loading signal CS is gated to the other Flash through the control logic of the programmable logic circuit, and the FPGA is forced to start a new loading sequence.
4. The FPGA logic reload circuit of claim 2,
the mode for realizing the logic upgrading function of the specified Flash in the online state in the logic online upgrading mode comprises the following steps: in the power-on process, a logic online upgrading mode is enabled by enabling an online upgrading enabling signal EN _ online _ upgrade, a Flash to be upgraded is selected by controlling an online upgrading Flash selection signal SEL _ online _ Flash, and the programmable logic circuit executes online upgrading operation on the selected Flash by judging the signals.
5. The FPGA logic reload circuit of claim 2,
the mode for realizing the logic upgrading function of the designated Flash in the off-line state in the logic off-line upgrading mode comprises the following steps: in the power-on process, a logic off-line upgrading mode is enabled by enabling an off-line upgrading enabling signal EN _ offline _ upgrade, a Flash to be upgraded is selected by controlling an off-line upgrading Flash selection signal SEL _ offline _ Flash, and the programmable logic circuit executes off-line upgrading operation on the selected Flash by judging the signals.
6. The FPGA logic reloading circuit of any one of claims 1-5, wherein the control logic in the programmable logic circuit is: the loading process of the FPGA is controlled through the programmable logic circuit, and the redundancy design, configurable upgrading and loading dynamic switching functions of the loading circuit are realized;
the control logic control architecture of the programmable logic circuit comprises: the device comprises a mode selection control unit, a timer unit, a loading control unit and a chip selection control unit.
7. The FPGA logic reload circuit of claim 6,
the mode selection control unit in the programmable logic circuit is used for judging and outputting the chip selection gating control signal CS _ Ctrl according to the states of an online upgrading enabling signal EN _ online _ upgrade, an offline upgrading enabling signal EN _ offline _ upgrade, an online upgrading Flash selection signal SEL _ online _ Flash, an offline upgrading enabling signal EN _ offline _ upgrade and a TimeOut signal Timeout.
8. The FPGA logic reload circuit of claim 7,
the timer unit in the programmable logic circuit is used for setting corresponding loading time timeout values to be 300ms, 500ms, 1s and 2s respectively through values '00', '01', '10' and '11' of time setting signals TimeSet1 and TimeSet2, and starting to time after a loading starting signal INIT _ B is effective;
if the FPGA logic loading completion signal DONE is not valid before the TimeOut time is reached, the output TimeOut signal TimeOut is '1';
if the FPGA logic loading completion signal DONE is valid before the TimeOut time is reached, the output TimeOut signal TimeOut is '0';
and the timer unit is also used for judging the state of the received Reload signal Reload output by the load control unit to restart timing under the condition of load timeout.
9. The FPGA logic reload circuit of claim 6,
and the loading control unit in the programmable logic circuit is used for outputting a low pulse to start an FPGA reloading process by judging the state of the TimeOut signal Timeout when the loading is overtime, namely the Timeout output by the timer unit is '1', and outputting a reloading signal Reload to the timer unit.
10. The FPGA logic reload circuit of claim 6,
the chip selection control unit in the programmable logic circuit is used for executing the gating operation from the chip selection signal CS output by the PPGA to the gating chip selection signals CS1 and CS2 of the 2 Flash chips according to the chip selection gating control signal CS _ Ctrl output by the mode selection control unit; when CS _ Ctrl is '0', the output is gated with CS1, and CS2 has no output; when CS _ Ctrl is '1', the output is gated CS2, and CS1 has no output.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113010233A (en) * | 2021-04-15 | 2021-06-22 | 天津讯联科技有限公司 | FPGA multi-backup program loading method and device suitable for commercial satellite |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2425627A (en) * | 2005-04-29 | 2006-11-01 | O2Micro Inc | Upgrading bit files for a Field Programmable Gate Array |
| CN200976140Y (en) * | 2005-04-29 | 2007-11-14 | 美国凹凸微系有限公司 | System for updating on-site programmable gate array bit files |
| WO2018041061A1 (en) * | 2016-08-29 | 2018-03-08 | 深圳市中兴微电子技术有限公司 | Onboard device upgrade method, device, system and computer storage medium |
-
2020
- 2020-11-05 CN CN202011227311.3A patent/CN112307697B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2425627A (en) * | 2005-04-29 | 2006-11-01 | O2Micro Inc | Upgrading bit files for a Field Programmable Gate Array |
| CN200976140Y (en) * | 2005-04-29 | 2007-11-14 | 美国凹凸微系有限公司 | System for updating on-site programmable gate array bit files |
| WO2018041061A1 (en) * | 2016-08-29 | 2018-03-08 | 深圳市中兴微电子技术有限公司 | Onboard device upgrade method, device, system and computer storage medium |
Non-Patent Citations (2)
| Title |
|---|
| H. ENGEL 等: "The ALICE high-level trigger read-out upgrade for LHC Run 2", 《JOURNAL OF INSTRUMENTATION》, pages 1 - 8 * |
| 唐文 等: "MSP430 系列单片机软件在线升级设计与实现", 《通信技术》, vol. 45, no. 1, pages 144 - 149 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113010233A (en) * | 2021-04-15 | 2021-06-22 | 天津讯联科技有限公司 | FPGA multi-backup program loading method and device suitable for commercial satellite |
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