CN219832635U

CN219832635U - Semiconductor packaging structure

Info

Publication number: CN219832635U
Application number: CN202321140622.5U
Authority: CN
Inventors: 颜尤龙; 博恩·卡尔·艾皮特; 凯·史提芬·艾斯格
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2023-05-12
Filing date: 2023-05-12
Publication date: 2023-10-13
Anticipated expiration: 2033-05-12

Abstract

The application provides a semiconductor packaging structure, one embodiment of which comprises: the first chip is provided with a first active surface and a first back surface opposite to the first active surface, and the first back surface is provided with a first cavity; and the second chip is accommodated in the first cavity, and is electrically connected with the first active surface of the first chip. The first cavity is formed in the first back surface opposite to the first active surface of the first chip, and the second chip is accommodated in the first cavity, so that the first chip and the second chip are mainly made of silicon, CTE is basically the same, and the use of a substrate or an intermediate layer is avoided, therefore, the situation of mismatch of CTE can be avoided, and warping and mechanical stress caused by mismatch of CTE are avoided. In addition, the problem of increased package thickness due to increased chips in the prior art 3DIC can be avoided.

Description

Semiconductor packaging structure

Technical Field

The application relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure.

Background

The current trend towards advanced packaging is increasingly towards stacked chips. Among other things, 3D IC (Integrated Circuit) packaging requires through silicon vias (TSV, through Silicon Via) and micro solder bumps within the chip to enable interconnection of stacked chips. As the chip and interconnect thickness increases, the package thickness increases with each additional chip in the stack. 2.5D IC packages require an interposer rather than an organic substrate to achieve high density interconnection. The interposer's through silicon vias and rewiring Layer (RDL, reDistribution Layer) require interconnection of all chips and printed circuit boards (PCB, printed Circuit Board), the interposer's cost is high and is affected by the interposer area. In summary, one of the major problems with current package structures is the mismatch in coefficient of thermal expansion (CTE, coefficient of thermal expansion) between the silicon and the substrate, which can lead to substrate warpage and mechanical stress.

Disclosure of Invention

The utility model provides a semiconductor packaging structure.

In a first aspect, the present utility model provides a semiconductor package structure, comprising: the first chip is provided with a first active surface and a first back surface opposite to the first active surface, and the first back surface is provided with a first cavity;

and the second chip is accommodated in the first cavity, and is electrically connected with the first active surface of the first chip.

In some alternative embodiments, the second chip has a second active surface facing away from the first active surface, and the semiconductor package further includes:

and the rewiring layer is arranged on the second chip and the first back surface of the first chip and is electrically connected to the second active surface of the second chip.

In some alternative embodiments, the first chip has a through silicon via for connecting the first active surface of the first chip and the redistribution layer.

In some alternative embodiments, the second chip has a second active surface facing the first active surface of the first chip, and the first chip has a through silicon via to connect the first active surface of the first chip with the second active surface of the second chip.

In some alternative embodiments, the through silicon vias overlap with the projection of the second chip in the horizontal direction.

In some alternative embodiments, the first back surface of the first chip has a second cavity, and the semiconductor package structure further includes: and a third chip accommodated in the second cavity, the third chip having a third active surface and a third back surface opposite to the third active surface.

In some alternative embodiments, the semiconductor package structure further includes:

and the rewiring layer is arranged on the second chip and the third chip and is used for electrically connecting the second chip and the third chip.

and the second back surface of the second chip is provided with a third cavity for accommodating the fourth chip.

In some alternative embodiments, the first active surface of the first chip is electrically connected to the fourth active surface of the fourth chip.

In some alternative embodiments, the first active surface of the first chip faces the fourth active surface of the fourth chip, wherein the fourth chip has through silicon vias to connect the first active surface of the first chip and the fourth active surface of the fourth chip.

In order to solve the problems of substrate warpage, mechanical stress and the like caused by mismatch of thermal expansion coefficients between silicon and a substrate in the current packaging technology, the application provides a semiconductor packaging structure, which comprises a first chip, a second chip and a first substrate, wherein the first chip is provided with a first active surface and a first back surface opposite to the first active surface, and a first cavity is arranged on the first back surface; and the second chip is accommodated in the first cavity, and is electrically connected with the first active surface of the first chip.

Specifically, the first cavity is formed in the first back surface opposite to the first active surface of the first chip, and the second chip is accommodated in the first cavity, so that the first chip and the second chip are mainly made of silicon, CTE is basically the same, and the use of a substrate or an intermediate layer is avoided, therefore, the situation of mismatch of CTE can be avoided, and warping and mechanical stress caused by mismatch of CTE are avoided. In addition, the problem of increased package thickness due to increased chips in the prior art 3DIC can be avoided.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:

Fig. 1 is a schematic longitudinal sectional structure of one embodiment 1a of a semiconductor package structure according to the present application;

fig. 2 is a schematic longitudinal sectional structure of another embodiment 2a of a semiconductor package structure according to the present application;

fig. 3 is a schematic longitudinal sectional structure of another embodiment 3a of a semiconductor package structure according to the present application;

fig. 4 is a schematic longitudinal sectional structure of another embodiment 4a of a semiconductor package structure according to the present application;

fig. 5 is a schematic longitudinal sectional structure of another embodiment 5a of a semiconductor package structure according to the present application;

fig. 6 is a schematic longitudinal sectional structure of another embodiment 6a of a semiconductor package structure according to the present application;

fig. 7 is a schematic longitudinal sectional structure of another embodiment 7a of a semiconductor package structure according to the present application;

fig. 8 is a schematic longitudinal sectional structure of another embodiment 8a of a semiconductor package structure according to the present application;

fig. 9 is a schematic longitudinal sectional structure of another embodiment 9a of a semiconductor package structure according to the present application;

fig. 10 is a schematic view of a longitudinal sectional structure of another embodiment 10a of a semiconductor package structure according to the present application;

FIGS. 11-13 are schematic views showing steps in manufacturing an embodiment 1a of a semiconductor package structure according to the present application, respectively;

FIGS. 14-16 are schematic views each showing a manufacturing step of another embodiment 2a of the semiconductor package structure according to the present application;

FIGS. 17-21 are schematic views each showing a manufacturing step of another embodiment 3a of the semiconductor package structure according to the present application;

FIGS. 22-26 are schematic views each showing a manufacturing step of another embodiment 4a of the semiconductor package structure according to the present application;

FIGS. 27-29 are schematic views of steps in the manufacture of another embodiment 5a of a semiconductor package structure according to the present application, respectively;

FIGS. 30-32 are schematic views each showing a manufacturing step of another embodiment 6a of a semiconductor package structure according to the present application;

FIGS. 33-35 are schematic views each showing a manufacturing step of another embodiment 7a of the semiconductor package structure according to the present application;

FIGS. 36-39 are schematic views each showing a manufacturing step of another embodiment 8a of the semiconductor package structure according to the present application;

FIGS. 40-42 are schematic views each showing a manufacturing step of another embodiment 9a of a semiconductor package structure according to the present application;

FIGS. 43-45 are schematic views each showing a manufacturing step of another embodiment 10a of a semiconductor package structure according to the present application;

Reference numerals/symbol description:

10-a first chip; 11-a first through silicon via; 12-a second dielectric layer; 13-a first dielectric layer; 14-a bottom rewiring layer; 15-solder balls; 16-a first connection pad (pad); 17-an upper rewiring layer; 18-a second connection pad; 19-an adhesive layer; 20-a second chip; 21-molding a sealing material; 22-copper pillars (pilar); 23-bump (bump); 24-a second through silicon via; 25-a third chip; 26-a carrier plate; 27-an adhesive layer; 28-resist; 29-fourth chip; 30-a first cavity; 31-a second cavity; 32-a third cavity; 33-penetrating plastic holes; 34-a first back side; 35-a first active surface; 36-a third through silicon via; 37-fourth through silicon vias; 38-a second active surface; 39-a second back side; 40-a third active surface; 41-a third back surface; 42-fourth active surface; 43-fourth back side.

Detailed Description

The following description of the embodiments of the present application will be given with reference to the accompanying drawings and examples, and it is easy for those skilled in the art to understand the technical problems and effects of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. In addition, for convenience of description, only a portion related to the related application is shown in the drawings.

It should be readily understood that the meanings of "on", "above" and "above" in the present application should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.

Further, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate (substrate) may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

The term "substrate" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, or the like. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are only used for being matched with those described in the specification for understanding and reading, and are not intended to limit the applicable limitation of the present application, so that the present application has no technical significance, and any modification of structures, changes in proportions or adjustment of sizes, without affecting the efficacy and achievement of the present application, should still fall within the scope covered by the technical content disclosed in the present application. Also, the terms "upper", "first", "second", and "a" and the like are used herein for descriptive purposes only and are not intended to limit the scope of the application for which the application may be practiced, but rather for relative changes or modifications without materially altering the technical context.

It should be further noted that, in the embodiment of the present application, the corresponding longitudinal section may be a section corresponding to a front view direction, the corresponding transverse section may be a section corresponding to a right view direction, and the corresponding horizontal section may be a section corresponding to an upper view direction.

In addition, the embodiments of the present application and the features in the embodiments may be combined with each other without collision. The application will be described in detail below with reference to the drawings in connection with embodiments.

Referring to fig. 1, fig. 1 is a schematic longitudinal sectional structure of one embodiment 1a of a semiconductor package structure according to the present application.

As shown in fig. 1, the semiconductor package 1a is an embodiment in which a fan-out chip is placed in a fan-in chip (FO Chip in FI Chip), and specifically, the semiconductor package 1a includes a first chip 10 and a second chip 20. The first chip 10 has a first active surface 35 and a first back surface 34 opposite to the first active surface 35, and the first back surface 34 is provided with a first cavity 30 for accommodating the second chip 20, the second chip 20 is fixed in the first cavity 30 of the first chip 10 by the adhesive layer 19, and the second chip 20 is electrically connected with the first active surface 35 of the first chip 10.

Here, the first chip 10 and the second chip 20 may be various bare chips (Die). The first chip 10 and the second chip 20 may be arranged back-to-back, i.e. the second chip 20 may have a second active surface 38 opposite to the first active surface 35. The first active surface 35 of the first chip 10 may have a first connection pad 16, and the second active surface 38 of the second chip 20 may have a second connection pad 18, where the first connection pad 16 and the second connection pad 18 are used to input and output signals.

In some alternative embodiments, the semiconductor package 1a further includes an underlying rerouting layer 14 disposed on the first active surface 35 of the first chip 10, the underlying rerouting layer 14 being electrically connected to the first connection pad 16 of the first active surface 35. Optionally, the distribution area of the bottom redistribution layer 14 is within the first active surface 35 of the first chip 10, and is a Fan-In (FI) structure.

In some alternative embodiments, the bottom rerouting layer 14 may comprise a first dielectric layer 13 contacting the first active surface 35 of the first chip 10.

In some alternative embodiments, the semiconductor package structure 1a further includes solder balls 15 disposed on the underlying rewiring layer 14, the solder balls 15 being configured to connect to an external device, such as a connection substrate or a rewiring layer of a PCB or other structure.

In some embodiments, the semiconductor package 1a further includes an upper redistribution layer 17, where the upper redistribution layer 17 is disposed on the second active surface 38 of the second chip 20 and the first back surface 34 of the first chip 10, and is electrically connected to the second active surface 38 of the second chip 20.

In some embodiments, the first chip 10 has a first through silicon via 11 for connecting the first active surface 35 of the first chip 10 and the upper redistribution layer 17.

In some alternative embodiments, the semiconductor package 1a further includes a second dielectric layer 12, where the second dielectric layer 12 fills the first cavity 30, encapsulates the second chip 20, and is interposed between the upper redistribution layer 17 and the second active surface 38 of the second chip 20 (and the first back surface 34 of the first chip 10).

In the semiconductor package structure 1a of this embodiment, the substrate is avoided, the first back surface 34 of the first chip 10 serving as the mother chip is provided with the first cavity 30, and the second chip 20 serving as the sub-chip is provided in the first cavity 30, and the CTE is substantially the same as the CTE due to the main materials of the first chip 10 and the second chip 20, so that the problem of CTE mismatch can be avoided, and further the package structure warpage and mechanical stress accumulation are avoided.

Referring to fig. 2, fig. 2 is a schematic longitudinal sectional structure of another embodiment 2a of a semiconductor package structure according to the present application. The semiconductor package 2a shown in fig. 2 is similar to the semiconductor package 1a shown in fig. 1, except that:

as shown in fig. 2, the semiconductor package 2a is an embodiment in which a fan-out chip is placed in a fan-out chip (FO Chip in FO Chip). Specifically, the semiconductor package 2a includes a first chip 10, and a first cavity 30 is formed in a first back surface 34 of the first chip 10, and a second chip 20 is fixed to the first back surface 34 of the first chip 10 through an adhesive layer 19, and the second chip 20 is electrically connected to a first active surface 35 of the first chip 10.

The semiconductor package 2a further includes a mold compound 21, wherein the mold compound 21 encapsulates the first chip 10, fills the first cavity 30, and encapsulates the second chip 20 in the first cavity 30. Here, the underlying rewiring layer 14 provided on the first active surface 35 of the first chip 10 is not only distributed within the range of the first active surface 35 of the first chip 10, but also partially distributed on the surface of the mold compound 21 outside the range of the first active surface 35, and has a Fan Out (FO) structure.

The semiconductor package 2a may further include a molding hole 33 (through molding via, TMV) penetrating the molding compound 21 to connect the first active surface 35 of the first chip 10 and the upper redistribution layer 17.

The semiconductor package structure 2a protects the chips (the first chip 10 and the second chip 20) by a mold sealing means, realizes isolation of the chips from the outside, prevents impurities in the air, and protects the surfaces of the chips due to degradation of electrical performance caused by corrosion of the chip circuits.

Referring to fig. 3, fig. 3 is a schematic longitudinal sectional structure of another embodiment 3a of a semiconductor package structure according to the present application. The semiconductor package 3a shown in fig. 3 is similar to the semiconductor package 1a shown in fig. 1, except that:

As shown in fig. 3, the semiconductor package 3a is an embodiment in which a fan-out chip is finally placed into a fan-in chip (FO Chip Last in FI Chip), specifically, the second chip 20 in the semiconductor package 3a has a second active surface 38 facing the first active surface 35 of the first chip 10, and the first chip 10 has a second through silicon via 24 for connecting the first active surface 35 of the first chip 10 and the second active surface 38 of the second chip 20.

The second active surface 38 of the second chip 20 may have the second connection pad 18, the copper pillar 22 and the bump 23, and the second active surface 38 is connected to the first active surface 35 of the first chip 10 through the second through-silicon via 24.

In some embodiments, the second through silicon via 24 overlaps the projection of the second chip 20 in the horizontal direction, i.e., it means that the second chip 20 is received in the first cavity 30 of the first chip 10.

Referring to fig. 4, fig. 4 is a schematic longitudinal sectional structure of another embodiment 4a of a semiconductor package structure according to the present application. The semiconductor package structure 4a shown in fig. 4 is similar to the semiconductor package structure 3a shown in fig. 3, except that:

as shown in fig. 4, the semiconductor package structure 4a is an embodiment in which the fan-out chip is finally placed into the fan-out chip (FO Chip Last in FO Chip), and specifically, the semiconductor package structure 4a further includes a mold compound 21, wherein the mold compound 21 encapsulates the first chip 10, fills the first cavity 30, and encapsulates the second chip 20 in the first cavity 30. Here, the bottom rewiring layer 14 is a fan-out (FO) structure.

Alternatively, in the process, the molding operation may be performed on the edge of the first chip 10, and the secondary molding operation may be performed after the second chip 20 is placed in the first cavity 30 of the first chip 10.

Referring to fig. 5, fig. 5 is a schematic longitudinal sectional structure of another embodiment 5a of a semiconductor package structure according to the present application.

As shown in fig. 5, the semiconductor package 5a is an embodiment of a fan-out Chip embedded in a Multi-Cavity Chip (FO Chip in Multi-Cavity Chip), specifically, the first Chip 10 of the semiconductor package 5a has a first Cavity 30 for accommodating a second Chip 20, the second Chip 20 is fixed in the first Cavity 30 of the first Chip 10 by an adhesive layer 19, the second Chip 20 has a second active surface 38 facing away from the first active surface 35 and a second back surface 39 opposite to the second active surface 38, and the active surface of the second Chip 20 is provided with an upper redistribution layer 17, and the upper redistribution layer 17 is electrically connected to the active surface of the first Chip 10 by a first through-silicon via 11.

The first chip 10 further has a second cavity 31 for accommodating a third chip 25, the third chip 25 is fixed in the second cavity 31 by the adhesive layer 19, the third chip 25 has a third active surface 40 facing away from the first active surface 35 and a third back surface 41 opposite to the third active surface 40, and the upper redistribution layer 17 is further disposed on the active surfaces of the third chip 25 and electrically connected to each other.

The semiconductor package structure 5a further includes a second dielectric layer 12 for filling the first cavity 30 and the second cavity 31, covering the second chip 20 and the third chip 25, isolating the upper redistribution layer 17 and protecting the circuit.

Here, the upper redistribution layer 17 is disposed on the second chip 20 and the third chip 25, and may be used to electrically connect the second chip 20 and the third chip 25.

Referring to fig. 6, fig. 6 is a schematic longitudinal sectional structure of another embodiment 6a of a semiconductor package structure according to the present application. The semiconductor package 6a shown in fig. 6 is similar to the semiconductor package 5a shown in fig. 5, except that:

as shown in fig. 6, the semiconductor package 6a is a schematic diagram of a plurality of fan-out chips embedded in a fan-in chip (Multi-FO Chips in FI Chip), specifically, the first chip 10 of the semiconductor package 6a has a first cavity 30 for accommodating the second chip 20 and the third chip 25, and the second chip 20 and the third chip 25 can be electrically connected to the active surface of the first chip 10 through the upper redistribution layer 17 and the first through-silicon vias 11, so as to accommodate a plurality of chips in one chip, and reduce the problem of warpage and mechanical stress of the substrate caused by mismatch of thermal expansion coefficients between the interposer and the substrate.

Referring to fig. 7, fig. 7 is a schematic longitudinal sectional structure of another embodiment 7a of a semiconductor package structure according to the present application. The semiconductor package 7a shown in fig. 7 is similar to the semiconductor package 1a shown in fig. 1, except that:

as shown in fig. 7, the semiconductor package 7a is a 3D nested integrated fan-in chip package (NIC FI), and the semiconductor package further includes a fourth chip 29, the fourth chip 29 having a fourth active surface 42 and a fourth back surface 43 opposite the fourth active surface 42, and the fourth chip 29 being accommodated in a third cavity 32 provided in a second back surface 39 of the second chip 20. In one embodiment, the first active surface 35 of the first chip 10 is electrically connected to the fourth active surface 42 of the fourth chip 29.

Specifically, the semiconductor package 7a has a first chip 10, the first back surface 34 of the first chip 10 has a first cavity 30 for accommodating the second chip 20, the second active surface 38 of the second chip 20 faces the first active surface 35 of the first chip 10, and the connection between the second chip 20 and the first chip 10 is achieved through the second through-silicon via 24; the second chip 20 has a second back surface 39 opposite to the second active surface 38, the second back surface 39 has a third cavity 32 for accommodating a fourth chip 29, and the fourth chip 29 is fixed in the third cavity 32 of the second chip 20 by the adhesive layer 19, the fourth chip 29 has an upper redistribution layer 17 and a second connection pad 18, and the connection with the second chip 20 and the first chip 10 is realized by the first through-silicon via 11.

Referring to fig. 8, fig. 8 is a schematic longitudinal sectional structure of another embodiment 8a of a semiconductor package structure according to the present application. The semiconductor package 8a shown in fig. 8 is similar to the semiconductor package 7a shown in fig. 7, except that:

as shown in fig. 8, the semiconductor package 8a is another 3D nested integrated fan-out chip package (3D Nested Integrated Chip FO), specifically, the semiconductor package 8a has a first chip 10, and the first back surface 34 of the first chip 10 has a first cavity 30 for accommodating a second chip 20, the second active surface 38 of the second chip 20 faces the first active surface 35 of the first chip 10, and the second back surface 39 of the second chip 20 has a third cavity 32 for accommodating a plurality of fourth chips 29, the fourth active surfaces 42 of the plurality of chips 29 are all fixed in the third cavity 32 of the second chip 20 by an adhesive layer 19, and after the fourth chip 29 is fixed in the fourth cavity, the semiconductor package is secondarily molded, thereby protecting the circuit from the outside, and the semiconductor package 8a may further include a through hole 33 penetrating through the molding compound 21 for connecting the first active surface 35 of the first chip 10 and the upper layer rerouting layer 17.

Referring to fig. 9, fig. 9 is a schematic longitudinal sectional structure of another embodiment 9a of a semiconductor package structure according to the present application. The semiconductor package 9a shown in fig. 9 is similar to the semiconductor package 9a shown in fig. 7, except that:

as shown in fig. 9, the semiconductor package 9a is another 3D nested integrated fan-in chip package (3D Nested Integrated Chip FI), specifically, the semiconductor package 9a has a first chip 10, a first back surface 34 of the first chip 10 has a first cavity 30 for accommodating a second chip 20, a second active surface 38 of the second chip 20 faces the first active surface 35 of the first chip 10, a second back surface 39 of the second chip 20 has a third cavity 32 for accommodating a fourth chip 29, a fourth active surface 42 of the fourth chip 29 faces the second active surface 38 of the second chip 20 and the first active surface 35 of the first chip 10, and the fourth active surface 42 of the fourth chip 29 may have copper pillars 22, second connection pads 18 and bumps 23, and is connected to the second chip 20 through a third through-silicon via 36 and then connected to the first active surface 35 of the first chip 10 through the second through-silicon via 24.

Referring to fig. 10, fig. 10 is a schematic view of a longitudinal sectional structure of another embodiment 10a of the semiconductor package structure of the present application. The semiconductor package structure 10a shown in fig. 10 is similar to the semiconductor package structure 9a shown in fig. 9, except that:

As shown in fig. 10, the semiconductor package 10a is another 3D nested integrated fan-out chip package (3D Nested Integrated Chip FO), specifically, the fourth active surface 42 of the fourth chip 29 in the semiconductor package 10a faces the first active surface 35 of the first chip 10, and an upper redistribution layer 17 is built on the first back surface 34 of the fourth chip 29 to connect with the second chip 20 and the first chip 10 through the third through silicon via 36, and the semiconductor package 10a may further include a through plastic hole 33 penetrating through the mold seal 21 to connect with the first active surface 35 of the first chip 10 and the upper redistribution layer 17.

In one embodiment, the first active surface 35 of the first chip 10 faces the fourth active surface 42 of the fourth chip 29, wherein the fourth chip has a fourth through silicon via 37 for connecting the first active surface 35 of the first chip 10 and the fourth active surface 42 of the fourth chip 29.

Referring to fig. 11 to 13, fig. 11 to 13 are schematic views of manufacturing steps of one embodiment 1a of a semiconductor package structure according to the present application.

Referring to fig. 11, fig. 11 shows a second chip 20 fixed in a first cavity 30 of the first chip 10 by an adhesive layer 19.

Before fig. 11, a through silicon via is formed on the first chip 10 by a process such as plasma etching, and copper plating is performed on the through silicon via to form a first through silicon via 11; then, the underlying redistribution layer 14 is formed on the first active surface 35 of the first chip 10, and then, cavity etching is performed on the first back surface 34 opposite to the first active surface 35 of the first chip 10 to form the first cavity 30, so that the second chip 20 may be fixed in the first cavity 30 by the adhesive layer 19 in fig. 11.

Referring to fig. 12, fig. 12 shows a second dielectric layer 12 formed by coating the semiconductor package 1a with a dielectric material based on fig. 11.

Referring to fig. 13, fig. 13 illustrates that an upper layer of redistribution layer 17 is formed on top of the second chip 20 in the semiconductor package 1a on the basis of fig. 12, wherein the second connection pad 18 on the second active surface 38 of the second chip 20 is electrically connected to the upper layer of redistribution layer 17, and then the ball mounting operation can be performed on the bottom layer of redistribution layer 14 of the semiconductor package 1a on the basis of fig. 13, so as to facilitate subsequent connection with a substrate or the like.

Referring to fig. 14 to 16, fig. 14 to 16 are schematic views showing a manufacturing step of another embodiment 2a of the semiconductor package structure according to the present application.

Referring to fig. 14, fig. 14 illustrates an operation of fixing the second chip 20 in the first cavity 30 of the first chip 10 through the adhesive layer 19 in the semiconductor package 2 a.

Before fig. 14, a first chip 10 is provided, a cavity etching operation is performed on the first chip 10, then the first chip 10 after the cavity etching operation is fixed on a carrier plate 26 through an adhesive layer 27, and the first chip 10 has a first connection pad 16 in contact with the adhesive layer 27; and the second chip 20 is fixed in the first cavity 30, and then the semiconductor package 2a is subjected to a molding operation to form a molding material 21, in an alternative embodiment, after the semiconductor package 2a is molded, the molding material 21 may be subjected to a grinding operation, so that the surface of the molding material 21 is smoother.

Referring to fig. 15, fig. 15 illustrates that a redistribution layer is formed on the second active surface 38 of the second chip 20 after the molding, and the second chip 20 is electrically connected to the redistribution layer through the second connection pad 18, and is connected to the first active surface 35 of the first chip 10 through the first through silicon via 11. And the carrier removal operation is performed on the basis of fig. 15.

Referring to fig. 16, fig. 16 illustrates the formation of an underlying rerouting layer 14 on the first active surface 35 of the first chip 10 after the deplating operation, and the electrical connection to the underlying rerouting layer 14 is made through the first connection pad 16. Optionally, the bottom layer rewiring layer 14 of the semiconductor package 2a may be subjected to a ball mounting operation, so as to facilitate connection with an external device.

Referring to fig. 17 to 21, fig. 17 to 21 are schematic views of manufacturing steps of another embodiment 3a of a semiconductor package structure according to the present application, respectively.

Referring to fig. 17, fig. 17 is a cavity etching operation, unlike the foregoing cavity etching operation, fig. 17 protects a partial region from etching by a resist 28, facilitating control of the size of the area of cavity etching, etc. Before the cavity etching operation of fig. 17, the first chip 10 needs to be provided, and the bottom rerouting layer 14 is formed on the active surface of the first chip 10.

Referring to fig. 18, fig. 18 is a process of recoating the resist 28 on the basis of fig. 17 and developing the resist 28 by laser direct imaging (LDI, laser direct imaging) to pattern the resist 28.

Referring to fig. 19, fig. 19 is a process of performing reactive ion etching to form a through silicon via on the basis of fig. 18, and then stripping the resist.

Referring to fig. 20, fig. 20 illustrates a conductive material filling operation of the through silicon via after the resist stripping operation performed on the basis of fig. 19, to form a conductive second through silicon via 24, wherein the conductive material may be copper or silver, and in an alternative embodiment, silver may be used to fill the through silicon via for better conductive efficiency.

Referring to fig. 21, fig. 21 illustrates the placement of the second chip 20 based on fig. 20, that is, the second active surface 38 of the second chip 20 faces the first active surface 35 of the first chip 10, and the connection with the first chip 10 is achieved by soldering the copper pillar 22 and the bump 23 thereon with the second through silicon via 24. The semiconductor package 3a is then encapsulated and ball-attaching operations may be performed on the underlying rewiring layer 14 for subsequent operations.

Referring to fig. 22 to 26, fig. 22 to 26 are schematic views showing a manufacturing step of another embodiment 4a of the semiconductor package structure according to the present application.

Referring to fig. 22, fig. 22 is a step of performing a redistribution layer fabrication on the first chip 10 to form an underlying redistribution layer 14, and connecting the underlying redistribution layer 14 through the first connection pad 16; the first chip 10 is provided before this, and the first chip 10 is placed on the carrier plate 26, and the first chip 10 is fixed on the carrier plate 26 by the adhesive layer 27, on which the semiconductor package structure 4a is molded to form the mold seal material 21 with a specific pattern, and in an alternative embodiment, the mold seal material 21 is ground after the mold seal, so that the surface of the mold seal material is flat, and the subsequent operation is facilitated.

Referring to fig. 23, fig. 23 is a schematic diagram showing the structure shown in fig. 23, in which the resist 28 is spray-printed after the inverted carrier removal operation is performed on the basis of fig. 22, so as to protect the resist 28 spray-printed area from being etched during the subsequent cavity etching operation.

Referring to fig. 24, fig. 24 illustrates a second through silicon via 24 formed by conducting a conductive material filling operation after the through silicon via etching operation performed on the basis of fig. 23, wherein one end of the second through silicon via 24 is connected to the first connection pad 16, thereby realizing connection with the underlying rewiring layer 14.

Referring to fig. 25, fig. 25 illustrates the placement of the second chip 20 based on fig. 24, wherein the second active surface 38 of the second chip 20 faces the first active surface 35 of the first chip 10, and is soldered to the second through-silicon via 24 through the copper pillar 22 and the bump 23 thereon, so as to achieve the connection with the first chip 10.

Referring to fig. 26, fig. 26 is a schematic diagram of performing a secondary molding operation on the basis of fig. 25, so as to isolate the semiconductor package structure 4a from the outside, and not match the thermal expansion coefficients of the substrate and the chip, so as to relieve the mechanical stress caused by the external environmental changes such as heat. In addition, the semiconductor packaging structure 4a can be subjected to ball mounting operation after being molded, so that subsequent operation is facilitated.

Referring to fig. 27 to 29, fig. 27 to 29 are schematic views of manufacturing steps of one embodiment 5a of a semiconductor package structure according to the present application.

Referring to fig. 27, fig. 27 is a schematic diagram of cavity etching of the first chip 10, and in order to facilitate subsequent accommodating of the second chip 20 and the third chip 25, the first chip 10 needs to be cavity etched to form a first cavity 30 and a second cavity 31.

Before the cavity etching operation, the first chip 10 is provided in advance, and then the through silicon vias are etched on the first chip 10 to form a plurality of through silicon vias, and then the through silicon vias are electroplated to form a plurality of first through silicon vias 11, and then the first chip 10 is subjected to the re-wiring layer manufacturing to form the bottom re-wiring layer 14, and the connection with the bottom re-wiring layer 14 is realized through the first connection pad 16. The second chip 20 is then fixed in the first cavity 30 of the first chip 10 by the adhesive layer 19, the third chip 25 is fixed in the second cavity 31 of the first chip 10, and the second active surface 38 of the second chip 20 and the third active surface 40 of the third chip 25 are both the first active surface 35 of the first chip 10.

Referring to fig. 28, fig. 28 is a schematic diagram of dielectric filling of the semiconductor package structure 5a to form the second dielectric layer 12 for filling the cavities, protecting the chips, and protecting the insulation between the circuit and the layers.

Referring to fig. 29, fig. 29 is a schematic diagram of the fabrication of a redistribution layer for the semiconductor package structure 5a to form the upper redistribution layer 17, and the connection of the second chip 20 and the third chip 25 to the upper redistribution layer 17 is achieved through the second connection pad 18, and the connection of the upper redistribution layer 17 to the lower redistribution layer 14 is achieved through the first through-silicon via 11. And then the semiconductor packaging structure 5a is subjected to ball mounting operation on the basis of the method, so that the subsequent operation is facilitated.

Referring to fig. 30 to 32, fig. 30 to 32 are schematic views of manufacturing steps of another embodiment 6a of a semiconductor package structure according to the present application.

Referring to fig. 30, fig. 30 is a schematic operation diagram of fixing the second chip 20 and the third chip 25 to the first cavity 30 of the first chip 10, wherein the second chip 20 and the third chip 25 are both fixed in the first cavity 30 of the first chip 10 by the adhesive layer 19, and the second active surface 38 of the second chip 20 and the fourth active surface 42 of the third chip 25 are both opposite to the first active surface 35 of the first chip 10.

Before this operation, the first chip 10 needs to be provided, and the first chip 10 is subjected to a through-silicon via etching operation to form a through-silicon via, and the first through-silicon via 11 is formed by means of through-silicon via copper plating, and the first active surface 35 of the first chip 10 is subjected to a redistribution layer fabrication to form the bottom redistribution layer 14, and is connected to the bottom redistribution layer 14 through the first connection pad 16, and then the first back surface 34 of the first chip 10 is subjected to a cavity etching operation to form the first cavity 30 for accommodating the second chip 20 and the third chip 25.

Referring to fig. 31, fig. 31 is a schematic diagram illustrating an operation of filling a dielectric layer based on fig. 30, and a second dielectric layer 12 is formed to fill each cavity, protect each chip, and protect insulation between a circuit and each layer.

Referring to fig. 32, fig. 32 is a schematic diagram of the fabrication of the rewiring layer based on fig. 31, forming the upper rewiring layer 17, and connecting the second chip 20 and the third chip 25 through the second connection pad 18. Then, the semiconductor package 6a is subjected to ball mounting operation, so that the subsequent connection of external devices is facilitated.

Referring to fig. 33 to 35, fig. 33 to 35 are schematic views of manufacturing steps of one embodiment 7a of a semiconductor package structure according to the present application.

Referring to fig. 33, fig. 33 is a schematic view of an operation of soldering the second chip 20 to the first cavity 30 of the first chip 10, wherein the second chip 20 needs to be subjected to a cavity etching process and a re-wiring layer fabrication in advance before being soldered to the first cavity 30, so as to form a third cavity 32 and a re-wiring layer; before this, it is necessary to provide the first chip 10, perform the re-wiring layer manufacturing on the first chip 10, then perform the through-silicon via forming operation to form the first through-silicon via 11, perform the cavity etching operation on the first back surface 34 of the first chip 10 to form the first cavity 30, then perform the through-silicon via etching and the through-silicon via conductive material filling operation in the first cavity 30 to form the second through-silicon via 24, and further implement the connection with the first chip 10 through the second through-silicon via 24 through the second connection pad 18 in fig. 33.

Referring to fig. 34, fig. 34 is a schematic view of the operation of the fourth chip 29 in addition to fig. 33, the fourth chip 29 is fixed in the third cavity 32 of the second chip 20 by the adhesive layer 19, and the fourth active surface 42 of the fourth chip 29 is opposite to the first active surface 35 of the first chip 10. Then, the semiconductor package 7a is subjected to a molding operation, and the formed mold seal 21 is subjected to a grinding operation.

Referring to fig. 35, fig. 35 is a schematic diagram of the fabrication of the rewiring layer of the fourth chip 29 based on fig. 34 to form the upper rewiring layer 17, and then, the ball mounting operation may be further performed on the semiconductor package structure 7a to facilitate the subsequent connection of external devices.

Referring to fig. 36 to 39, fig. 36 to 39 are schematic views showing the manufacturing steps of one embodiment 8a of the semiconductor package structure according to the present application.

Referring to fig. 36, fig. 36 is a schematic operation of the second chip 20 soldered into the first cavity 30 of the first chip 10, with the second active surface 38 of the second chip 20 facing the first active surface 35 of the first chip 10 and being soldered with the second through-silicon via 24 by the bump 23. Before this, it is necessary to provide the first chip 10, and perform a redistribution layer fabrication on the first active surface 35 of the first chip 10, form the bottom redistribution layer 14, connect with the bottom redistribution layer 14 through the first connection pad 16, then form the first cavity 30 on the first back surface 34 of the first chip 10 through a cavity etching operation, so as to accommodate the second chip 20, then perform a molding operation, fill the molding material 21 to isolate the circuit from the outside, and perform a grinding operation on the molding material 21.

Referring to fig. 37, fig. 37 is a schematic view of the second back surface 39 of the second chip 20 being subjected to cavity etching on the basis of the above operation, thereby forming a third cavity 32 for accommodating the fourth chip 29.

Referring to fig. 38, fig. 38 is a schematic diagram of a third through silicon via 36 formed by performing a through silicon via forming operation on the basis of fig. 37.

Referring to fig. 39, fig. 39 is a schematic diagram of the fourth chip 29 bonding operation performed on the basis of fig. 38, and the fourth chip 29 is bonded to the third through-silicon via 36 by the bump 23, so that the fourth chip 29 is connected to the first chip 10 and the second chip 20. And then, performing a mold sealing operation to isolate the semiconductor package structure 8a from the outside, and performing a ball mounting operation on the bottom rewiring layer 14 of the first active surface 35 of the first chip 10, so as to facilitate subsequent operations.

Referring to fig. 40 to 42, fig. 40 to 42 are schematic views showing a manufacturing step of one embodiment 9a of a semiconductor package structure according to the present application.

Referring to fig. 40, fig. 40 is a schematic view of a cavity etching operation performed on the first back surface 34 of the second chip 20, and a third cavity 32 is formed by cavity etching the first back surface 34 of the second chip 20 to accommodate the fourth chip 29. Before this, a first chip 10 is provided, and a through-silicon via forming operation is performed on the first chip 10 to generate a first through-silicon via 11, then the first chip 10 is fixed on a carrier by an adhesive layer, a mold sealing and grinding operation is performed on the first chip 10, and after the carrier is removed, a redistribution layer is performed on a first active surface 35 of the first chip 10 to form a bottom redistribution layer 14, and then a cavity etching operation is performed on a first back surface 34 of the first chip 10 to form a first cavity 30 for accommodating a second chip 20, and then the second chip 20 is soldered into the first cavity 30, wherein a second active surface 38 of the second chip 20 faces the first active surface 35 of the first chip 10, and then a secondary mold sealing and grinding operation is performed to facilitate the cavity etching operation on the first back surface 34 of the first chip 10 in fig. 40.

Referring to fig. 41, fig. 41 is a schematic view of the bonding operation of the plurality of fourth chips 29 performed on the basis of fig. 40, the plurality of fourth chips 29 are fixed in the third cavity 32 by the adhesive layer 19, and the fourth active surfaces 42 of the plurality of fourth chips 29 are opposite to the first active surfaces 35 of the first chip 10. And then the semiconductor package 9a is subjected to a molding and grinding operation.

Referring to fig. 42, fig. 42 is a schematic diagram of the fabrication of the rewiring layer of the fourth chip 29 based on the die grinding operation of fig. 41, in which the upper layer rewiring layer 17 is formed by fabricating the rewiring layer on the fourth active surface 42 of the fourth chip 29, and the connection between the fourth chip 29 and the upper layer rewiring layer 17 is achieved through the second connection pad 18. The ball attach operation may then be performed on the underlying rewiring layer 14 of the first active surface 35 of the first chip 10.

Referring to fig. 43 to 45, fig. 43 to 45 are schematic views of manufacturing steps of one embodiment 10a of a semiconductor package structure according to the present application.

Referring to fig. 43, fig. 43 is a schematic operation diagram of soldering the second chip 20 to the first cavity 30 of the first chip 10, wherein the second chip 20 needs to be subjected to cavity etching in advance on the second back surface 39 of the second chip 20, and the third through silicon via 36 is formed, and the second active surface 38 of the second chip 20 faces the first active surface 35 of the first chip 10. Before this, the first chip 10 after the pretreatment needs to be fixed on the carrier plate 26 by the adhesive layer 27. After the second chip 20 is soldered to the first cavity 30 of the first chip 10.

Referring to fig. 44, fig. 44 is a schematic diagram of the operation of soldering the fourth chip 29 to the third cavity 32 of the second chip 20, wherein the fourth active surface 42 of the fourth chip 20 faces the first active surface 35 of the first chip 10. The semiconductor package 10a is then subjected to a molding operation and ground.

Referring to fig. 45, fig. 45 is a schematic diagram of the fabrication of the rewiring layer based on the foregoing operations, so as to form the upper layer rewiring layer 17, and connection of the fourth chip 29 to the second chip 20 and the first chip 10 is performed through the upper layer rewiring layer 17 and the fourth through-silicon vias 37. And then carrying out carrier removal operation, and carrying out ball implantation operation on the bottom layer rewiring layer 14 of the first active surface 35 of the first chip 10, so as to facilitate subsequent operation.

While the application has been described and illustrated with reference to specific embodiments thereof, the description and illustration is not intended to limit the application. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments thereof without departing from the true spirit and scope of the application as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between technical reproduction and actual implementation in the present application due to variables in the manufacturing process, etc. Other embodiments of the application not specifically illustrated may exist. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present application. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Thus, the order and grouping of the operations is not a limitation of the present application unless specifically indicated herein.

Claims

1. A semiconductor package structure, comprising:

the first chip is provided with a first active surface and a first back surface opposite to the first active surface, and the first back surface is provided with a first cavity;

2. The semiconductor package according to claim 1, wherein the second chip has a second active surface facing away from the first active surface, the semiconductor package further comprising:

3. The semiconductor package according to claim 2, wherein the first chip has a through silicon via for connecting the first active surface of the first chip and the redistribution layer.

4. The semiconductor package according to claim 1, wherein the second chip has a second active surface facing the first active surface of the first chip, and the first chip has a through silicon via for connecting the first active surface of the first chip with the second active surface of the second chip.

5. The semiconductor package according to claim 3 or 4, wherein the through silicon via overlaps with a projection of the second chip in a horizontal direction.

6. The semiconductor package according to claim 1, wherein the first back surface of the first chip has a second cavity, the semiconductor package further comprising: and a third chip accommodated in the second cavity, the third chip having a third active surface and a third back surface opposite to the third active surface.

7. The semiconductor package according to claim 6, further comprising:

8. The semiconductor package according to claim 1, further comprising:

9. The semiconductor package according to claim 8, wherein the first active surface of the first chip is electrically connected to the fourth active surface of the fourth chip.

10. The semiconductor package according to claim 9, wherein the fourth active surface of the fourth chip faces the first active surface of the first chip, wherein the fourth chip has through silicon vias for connecting the first active surface of the first chip and the fourth active surface of the fourth chip.