CN219611745U

CN219611745U - Output self-locking device in low voltage state

Info

Publication number: CN219611745U
Application number: CN202320122405.7U
Authority: CN
Inventors: 刘孟辉; 林燕娟; 张涛; 张吉明; 汤爱苹
Original assignee: Intelligent Automation Equipment Zhuhai Co Ltd
Current assignee: Intelligent Automation Equipment Zhuhai Co Ltd
Priority date: 2023-02-06
Filing date: 2023-02-06
Publication date: 2023-08-29
Anticipated expiration: 2033-02-06

Abstract

The utility model aims to provide the output self-locking device which has the advantages of high response speed and low cost and does not influence the low-voltage state of the output environment of the product to be tested. The utility model comprises a control module, a judging module and a latch module which are sequentially connected, wherein the judging module comprises a comparator and a feedback resistor, the negative electrode input end of the comparator is connected with a loop to be tested through the feedback resistor, the positive electrode input end of the comparator is connected with a communication port of the control module, the output end of the comparator is connected with a controlled end through the latch module, the control module is communicated with an upper computer to output a control signal to the comparator, and when the comparator and the feedback resistor monitor the voltage of the loop, the latch module carries out level latching. The utility model is applied to the technical field of electronic equipment testing.

Description

Output self-locking device in low voltage state

Technical Field

The utility model is applied to the technical field of electronic equipment testing, and particularly relates to an output self-locking device in a low-voltage state.

Background

Along with the progress of technology, semiconductor components are generally supplied with power in a wide range in order to fully meet the requirements of different power scenes, so that engineers can design and simplify the model selection of system components, however, designers easily ignore the protection of abnormal or under-voltage power supply paths, and further the system works in an unstable state. Fuses are typically placed on a stable and continuous power supply path to avoid sudden voltage drops across the path, causing current changes to shut off the power supply. When the voltage on the continuous and stable power supply path is abnormally reduced, the characteristic that the current becomes large is utilized, and then the fuse is utilized to cut off power supply, so that the fuse is low in precision and is not applicable to some paths with small currents. And the fuse is a thermal de-fusing path by current, the response is slower, and the risk that the fuse can be cut off after the damage of circuit components exists. There is also a risk of repeated power supply if a self-healing fuse is used.

In energy efficiency utilization scenarios, importance is increasingly highlighted for low voltage condition monitoring applications when power storage is reduced. When the voltage of the electric quantity is lower than a threshold value, a power consumption module with unnecessary functions is closed, so that long-time endurance of system functions is ensured, the MCU directly monitors the voltage of the electric quantity storage, however, the MCU directly monitors the voltage of the electric quantity storage, and when the voltage range accords with the TTL level, the MCU acquires the external voltage in real time, thus occupying the internal resources of the MCU and having slower response. When a large voltage range is encountered, a resistor voltage division mode is needed to meet TTL level, leakage current exists at the moment, and the energy utilization rate is reduced.

In some application scenarios of state monitoring, in order to avoid the disadvantage that the input signal is unstable and causes multiple inversions to the output state, a state latch scheme is used. Typically, when a circuit detects an under-voltage condition, a flip-flop is used to latch the condition at the TTL level until the flip-flop receives a clear instruction. However, the flip-flop latches the state at a high cost and is complicated to operate. Therefore, it is necessary to provide an output self-locking device with high response speed, low cost and low voltage state, which does not affect the output environment of the product to be tested.

Disclosure of Invention

The utility model aims to solve the technical problem of overcoming the defects of the prior art and providing the output self-locking device which has the advantages of high response speed, low cost and no influence on the low-voltage state of the output environment of a product to be tested.

The technical scheme adopted by the utility model is as follows: the utility model comprises a control module, a judging module and a latch module which are sequentially connected, wherein the judging module comprises a comparator and a feedback resistor, the negative electrode input end of the comparator is connected with a loop to be detected through the feedback resistor, the positive electrode input end of the comparator is connected with a communication port of the control module, the output end of the comparator is connected with a controlled end through the latch module, the control module is communicated with an upper computer to output a control signal or a voltage threshold value to the comparator, and when the comparator and the feedback resistor monitor the voltage of the loop, the latch module carries out level latching.

The scheme shows that the output self-locking device in the low voltage state has small volume, convenient integration, simpler circuit structure, low cost and better compatibility, when other systems apply the circuit, the control module and the comparator can be adjusted according to the actual measurement accuracy requirement, and the low-resolution comparator is used, so that the cost can be reduced, the replaced scheme can be completely used in other application systems, the latch module has more pertinence and functionality, and the latch module is built by using the most basic and common transistors, so that the cost is saved; the response speed is high, and the response speed is within 0.01mS by adopting the comparator with quick response and the simple latch module; the circuit is high in reliability, stable and reliable, and has strong anti-interference performance in state judgment and state maintenance; the precision is high, and the threshold voltage for state judgment is ensured to be within 0.00001V by adopting a 16 bit-control module and a high-resolution comparator; the resolution of 400uV can be achieved through the control module, the response time of the comparator 1uS and the latch module can completely control the response of the whole system within millisecond, and the risk of repeated power supply is avoided after the power supply is cut off through the latch module.

In one preferred scheme, the control module comprises a processor and an analog-to-digital converter, wherein an i2c_scl port and an i2c_sda port of the processor are connected with ports corresponding to the analog-to-digital converter, and a dac_ocp_limit port of the analog-to-digital converter is connected with ports corresponding to the judging module.

In one preferred scheme, the feedback resistor comprises a first resistor and a second resistor, the positive input end of the comparator is divided into two paths, one path is connected to the DAC_OCP_LIMIT port of the analog-to-digital converter through the first resistor, the other path is connected to the OUTPUT end of the comparator through the second resistor, the negative input end of the comparator is connected to the port of the loop to be tested, and the OUTPUT end of the comparator is connected to the SCHMITT_TRIGGER_OUTPUT port of the latch module.

The latch module comprises a first triode, a second triode, a field effect tube, a third resistor and a fourth resistor, wherein an emitter of the first triode is connected with 5V voltage, a base electrode of the first triode is connected with a collector of the second triode, the collector of the first triode is divided into two paths, one path is connected with a port connected with a controlled end, the other path is connected with one end of the fourth resistor through the third resistor and the base electrode of the second triode together, the other end of the fourth resistor is connected with a SCHMITT_TRIGGER_OUTPUT port of the comparator, an emitter of the second triode is grounded, a source electrode of the field effect tube is connected with a node of the fourth resistor, a grid electrode of the field effect tube is connected with a UVP_RST_EN port of the processor, and a source electrode of the field effect tube is grounded.

Drawings

FIG. 1 is a block diagram of the structure of the present utility model;

FIG. 2 is a schematic circuit diagram of the processor;

FIG. 3 is a schematic circuit diagram of the analog-to-digital converter;

FIG. 4 is a schematic circuit diagram of the decision module;

fig. 5 is a schematic circuit diagram of the latch module.

Detailed Description

As shown in fig. 1, in this embodiment, the present utility model includes a control module 1, a determination module 2, and a latch module 3 that are sequentially connected, where the determination module 2 includes a comparator U1 and a feedback resistor, the negative input end of the comparator U1 is connected to a loop to be tested through the feedback resistor, the positive input end of the comparator U1 is connected to a communication port of the control module 1, the output end of the comparator U1 is connected to a controlled end through the latch module 3, the control module 1 communicates with an upper computer to output a control signal to the comparator U1, and when the comparator U1 and the feedback resistor monitor the loop voltage, the latch module 3 performs level latching. The comparator U1 can avoid the complexity of the control module 1 to collect the voltage in real time, only one interrupt or direct output result of the comparator U1 is needed, the operational amplifier has wide input voltage range and high input impedance, the electric leakage problem of the voltage in a wide range is avoided, and the common hysteresis scheme built by the comparator U1 can avoid the damage of unstable input signals or bad environments to the comparator.

As shown in fig. 1 to 3, in the present embodiment, the control module 1 includes a processor U2 and an analog-to-digital converter U3, where an i2c_scl port and an i2c_sda port of the processor U2 are connected to ports corresponding to the analog-to-digital converter U3, and a dac_ocp_limit port of the analog-to-digital converter U3 is connected to ports corresponding to the determination module 2. The chip model of the processor U2 is STM32F103TBU6, the chip model of the analog-to-digital converter U3 is AD5667RBRMZ-1REEL7, and the control module 1 mainly comprises the processor U2, the analog-to-digital converter U3 and other peripheral circuits meeting the minimum system of the singlechip. The processor U2 completes communication of the analog-to-digital converter U3 through the I2C, zero clearing control of the latch module 3 is achieved through the GPIO pin of the processor U3, and the analog-to-digital converter U3 is used for outputting voltage so as to meet threshold voltage required by a system for judging undervoltage.

In this embodiment, as shown in fig. 4, the feedback resistor includes a first resistor R1 and a second resistor R2, the positive input end of the comparator U1 is divided into two paths, one path is connected to the dac_ocp_limit port of the analog-to-digital converter U3 through the first resistor R1, the other path is connected to the OUTPUT end of the comparator U1 through the second resistor R2, the negative input end of the comparator U1 is connected to the port of the loop to be tested, and the OUTPUT end of the comparator U1 is connected to the schmitt_trigger_output port of the latch module 3. The chip model of the comparator U1 is LM393DR, the judging module 2 mainly comprises a Schmidt trigger composed of the comparator U1, the first resistor R1 and the second resistor R2, the output end of the comparator U1 is connected with a fifth resistor R3, the fifth resistor R3 is connected with 5V voltage, the output inside the comparator U1 is an OC gate circuit, the fifth resistor R3 is required to be pulled up, and the high and low output of the state is completed. When the voltage of the inverting terminal of the comparator U1 is larger than that of the non-inverting terminal, the output is low; and when the output of the inverting terminal is smaller than that of the non-inverting terminal and is high, judging that the voltage is low. The positive feedback formed by the first resistor R1 and the second resistor R2 at the same phase end forms a hysteresis function of the comparator, and is used for eliminating noise influence of an input signal near a zero point of the comparator and avoiding high-low oscillation of the output of the comparator.

As shown in fig. 5, in this embodiment, the latch module 3 includes a first triode Q1, a second triode Q2, a field effect transistor Q3, a third resistor R33, and a fourth resistor R9, where an emitter of the first triode Q1 is connected to a 5V voltage, a base of the first triode Q1 is connected to a collector of the second triode Q2, the collector of the first triode Q1 is divided into two paths, one path is connected to a port connected to a controlled terminal, the other path is connected to one end of the fourth resistor R9 together via the third resistor R33 and a base of the second triode Q2, the other end of the fourth resistor R9 is connected to a schmitt_trigger_outport of the comparator U1, an emitter of the second triode Q2 is grounded, a source of the field effect transistor Q3 is connected to a node of the fourth resistor R9 and the third resistor R33, and a gate of the field effect transistor Q3 is connected to a port of the processor p_u2_ujfet RST. The chip model of the first triode Q1 is MMBT4403, the chip model of the second triode Q2 is MMBT2222ALT1G, the chip model of the field effect tube Q3 is 2N7002-7-F, and the latch module 3 mainly comprises state latch formed by the first triode Q1 and the second triode Q2, zero clearing control for the field effect tube Q3 and other current limiting resistors. The gate of the field effect transistor Q3 is connected to a switch S1, when the comparator U1 determines that the under-voltage state outputs a high level, the second triode Q2 will be turned on, at this time, the base (Q1-B) of the first triode Q1 is pulled down, the emitter (Q1-E) and the collector are turned on to enter the amplifying region, and the latch module 3 outputs a high level. Due to the third resistor R33, the high level output by the latch module 3 is fed back to the base of the second transistor Q2, and the level thereof is pulled up. Due to the isolation of the fourth resistor R9, the latch module 3 maintains the high level output to realize the state latch even when the output voltage of the comparator U1 is low again. The zero clearing control of the state is realized by receiving the high level of the processor U2 by the grid electrode of the field effect transistor Q3 or manually pressing the switch S1, and when the source electrode and the drain electrode of the field effect transistor Q3 are conducted, the base electrode voltage of the second triode Q2 is pulled down to realize zero clearing of the state. In addition, the state can be latched by only using the first triode Q1 and the second triode Q2, the cost is very low, the use is convenient in some severe environments, and the post-maintenance and the simple maintenance are easy.

The working principle of the utility model is as follows:

the control module is communicated with the upper computer, and then outputs a control signal or a voltage threshold to the comparator, and when the comparator and the feedback resistor monitor loop voltage, the latch module performs level latch. When the comparator and the feedback resistor are judged to be in an undervoltage state, the latch module carries out level latching, and the latch is not released until the latch module receives a zero clearing instruction; when the voltage of the inverting terminal of the comparator is larger than that of the non-inverting terminal, the output is low; when the output of the inverting terminal is smaller than that of the non-inverting terminal and is high, the undervoltage state is judged; when the comparator judges that the undervoltage state outputs high level, the second triode is conducted, at the moment, the base electrode of the first triode is pulled down, the emitter electrode and the collector electrode are conducted into the amplifying region, and the latch module outputs high level. Because of the third resistor, the high level output by the latch module is fed back to the base electrode of the second triode, and the level of the high level is pulled up. Due to the isolation of the fourth resistor, even when the output voltage of the comparator is low again, the latch module maintains high level output to realize state latch. The zero clearing control of the state is realized by receiving the high level of the processor by the grid electrode of the field effect transistor or manually pressing the switch, and when the source electrode and the drain electrode of the field effect transistor are conducted, the base electrode voltage of the second triode is pulled down, so that the zero clearing of the state is realized.

Claims

1. An output self-locking device in a low voltage state is characterized in that: the automatic level-locking device comprises a control module (1), a judging module (2) and a locking module (3) which are sequentially connected, wherein the judging module (2) comprises a comparator (U1) and a feedback resistor, the negative electrode input end of the comparator (U1) is connected with a loop to be detected through the feedback resistor, the positive electrode input end of the comparator (U1) is connected with a communication port of the control module (1), the output end of the comparator (U1) is connected with a controlled end through the locking module (3), the control module (1) is communicated with an upper computer to output a control signal to the comparator (U1), and the locking module (3) is used for carrying out level locking.

2. The low voltage state output self-locking device of claim 1, wherein: the control module (1) comprises a processor (U2) and an analog-to-digital converter (U3), wherein an I2C_SCL port and an I2C_SDA port of the processor (U2) are connected with ports corresponding to the analog-to-digital converter (U3), and a DAC_OCP_LIMIT port of the analog-to-digital converter (U3) is connected with ports corresponding to the judging module (2).

3. The low voltage state output self-locking device of claim 2, wherein: the feedback resistor comprises a first resistor (R1) and a second resistor (R2), wherein the positive input end of the comparator (U1) is divided into two paths, one path is connected with the DAC_OCP_LIMIT port of the analog-digital converter (U3) through the first resistor (R1), the other path is connected with the OUTPUT end of the comparator (U1) through the second resistor (R2), the negative input end of the comparator (U1) is connected with the port of the loop to be tested, and the OUTPUT end of the comparator (U1) is connected with the SCHMITT_TRIGGER_OUTPUT port of the latch module (3).

4. The low voltage state output self-locking device of claim 2, wherein: the latch module (3) comprises a first triode (Q1), a second triode (Q2), a field effect tube (Q3), a third resistor (R33) and a fourth resistor (R9), wherein an emitter of the first triode (Q1) is connected with 5V voltage, a base of the first triode (Q1) is connected with a collector of the second triode (Q2), the collector of the first triode (Q1) is divided into two paths, one path is connected with a port of a controlled end, the other path is connected with a base of the second triode (Q2) through the third resistor (R33) in a joint way, one end of the fourth resistor (R9) is connected with an SCHMITT_GGER_OUTPUT port of the comparator (U1), a source of the field effect tube (Q3) is connected with the fourth resistor (R9) in a joint way, and the source of the field effect tube (R3) is connected with a node of the third resistor (Q2) in a joint way.