CN216817236U

CN216817236U - MBUS main control unit receives detection circuitry

Info

Publication number: CN216817236U
Application number: CN202220366700.2U
Authority: CN
Inventors: 朱春雷; 陈潋平; 崔乃文; 马振华; 吕凯
Original assignee: Hohhot Ruicheng Technology Co ltd
Current assignee: Hohhot Ruicheng Technology Co ltd
Priority date: 2022-02-23
Filing date: 2022-02-23
Publication date: 2022-06-24
Anticipated expiration: 2032-02-23

Abstract

A MBUS master controller receiving detection circuit comprises a power module, a signal sending drive circuit, a receiving detection circuit and an overcurrent protection circuit; the MBUS-in the sending signal driving circuit is connected with the cathode of a power supply after sequentially passing through a protection turn-off MOS tube and a sampling resistor R14; the trigger end of the protection turn-off MOS tube is connected with an external main circuit after sequentially passing through the overcurrent protection circuit and the receiving detection circuit. Through the structure, the technical problem that detection precision and power consumption cannot be considered in the prior art is solved, and the MBUS main controller receiving detection circuit with high module loading capacity, good power efficiency and low cost is provided.

Description

MBUS main control unit receives detection circuitry

Technical Field

The utility model belongs to a communication module circuit design, and particularly relates to a MBUS main controller receiving detection circuit.

Background

In the field of consumption measuring instruments, due to a specific working environment, a bus used is required to have strong anti-interference capacity, and meanwhile, the bus has the characteristics of simplicity and convenience in installation and use and low cost. The M-BUS has the characteristics as a BUS structure, so that the M-BUS can be applied to the field of consumption measuring instruments.

However, in the field of consumption measurement instruments, a bus is also required to be able to connect many node devices and to enable long-distance communication. The MBUS bus is divided into a master controller module and a slave device module, most of the slave device modules are integrated at present due to the fact that the slave device modules work in a low-power state, and all communication and power feeding functions are integrated into one chip. However, in the aspect of the main control module, because the work current is large and the functions are more, the integration is not easy to carry out, and most of the main control module is built by adopting discrete elements. Because the traditional circuit structures are different, the main control module sends data by adopting voltage signals, and receives the data by adopting a 20mA current mode, and when the nodes are more, the quiescent current of the bus is greatly far greater than the current generated by the signals. Therefore, it is difficult to detect a small current change from a large quiescent current and to improve efficiency without increasing additional power consumption using the prior art.

Disclosure of Invention

In order to solve the above problems, the present invention provides a MBUS master controller receiving detection circuit, which overcomes the problems existing in the prior art. Through the controller, the purposes of improving the loading capacity of the module, improving the power supply efficiency and reducing the cost are achieved.

In order to achieve the purpose, the utility model provides the following technical scheme:

a MBUS master controller receiving detection circuit comprises a power module, a signal sending drive circuit, a receiving detection circuit and an overcurrent protection circuit;

the MBUS-in the sending signal driving circuit is connected with the cathode of a power supply after sequentially passing through a protection turn-off MOS tube and a sampling resistor R14; the trigger end of the protection turn-off MOS tube is connected with an external main circuit after sequentially passing through the overcurrent protection circuit and the receiving detection circuit;

the receiving detection circuit comprises a sampling part and a detection part; one current output end of a sampling resistor R14 in the sampling part is directly connected with the positive end of an operational amplifier U5A to form a direct current amplifier, and the other current output end of the sampling resistor R14 in the sampling part is connected with U7 after passing through a resistor R16 and a divider resistor; the detection part receives an output signal of the operational amplifier U5A, the output signal of the operational amplifier U5A is divided into two paths in the detection part, one path passes through a valley detector consisting of D4, C7 and R9, the other path passes through D5, and the two paths of signals are input into U5B for comparison.

The power supply module is formed by connecting a 36V switch type power supply boosting module and a 24V switch type power supply boosting module in parallel.

The over-current protection circuit compares the voltage sampled by the resistor R6 with a voltage reference source after the voltage is subjected to resistor voltage division.

The utility model has the beneficial effects that:

1. the high and low levels are realized by adopting two power supply modes, and the driving capability is very strong under each level.

2. The switch type booster circuit is adopted, so that the boosting efficiency is high, and the heat productivity of the circuit is low.

3. The valley detection and the through signal are adopted to compare and eliminate the inherent direct current component in the current, so that the reliability of the detection of the tiny change of the current is improved, and the accuracy of the communication is realized.

4. The bus overload protection is realized by adopting a mode of voltage reference comparison and switching-over control of an RS trigger on and off of an MOS (metal oxide semiconductor) tube, so that the circuit damage caused by overload is avoided.

Drawings

FIG. 1 is an overall block diagram of the MBUS master controller module circuit.

Fig. 2 is a receiving detection circuit diagram.

Fig. 3 is a circuit diagram of the overcurrent protection circuit.

Fig. 4 is a transmission signal driving circuit diagram.

Fig. 5 is a circuit diagram of a power module.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1:

as shown in fig. 1, the MBUS master controller receiving detection circuit includes a power module 1, a transmission signal driving circuit 2, a receiving detection circuit 3, and an overcurrent protection circuit 4.

The transmission signal driving circuit 2 is connected with the MBUS +, and is a signal modulation transmission part of the MBUS module; MBUS-in the sending signal driving circuit 2 is connected with the negative electrode of the power supply after sequentially passing through a protection turn-off MOS tube and a sampling resistor R14; the trigger end of the protection turn-off MOS tube is connected with an external main circuit after sequentially passing through the overcurrent protection circuit 4 and the receiving detection circuit 3.

The reception detection circuit 3 includes a sampling section and a detection section, as shown in fig. 2. One current output end of a sampling resistor R14 in the sampling part is directly connected with the positive end of an operational amplifier U5A to form a direct current amplifier, and the other current output end of the sampling resistor R14 in the sampling part is connected with a U7431 after passing through a resistor R16 and a divider resistor; the detection part receives an output signal of the operational amplifier U5A, the output signal of the operational amplifier U5A is divided into two paths in the detection part, one path passes through a valley detector consisting of D4, C7 and R9, the other path passes through D5, and the two paths of signals are input into U5B for comparison. Specifically, a circuit current signal is extracted through a 5.1 Ω sampling resistor R14 and is amplified by 10 times through a direct current amplifier U5A to be divided into two paths: one path of the voltage signal passes through R9, D4 and C7 to form a valley value integrating circuit, pulse components in the voltage signal are eliminated, static direct current components are extracted, and the valley value integrating circuit is connected to the negative end of U5B; the other path is directly connected with the positive terminal of U5B by reducing the potential of a proper amount through a diode D5. U5B constitutes a comparator, and when there is no pulse signal in the signal voltage, the positive terminal of U5B is slightly lower than the negative terminal potential, and the amplifier outputs a low level. When the positive terminal pulse peak of U5B is higher relative to the pulse valley voltage of the negative terminal of U5B when the signal voltage has a pulse signal, the comparator U5B outputs a high level. The pulse signal is isolated and shaped by an optical coupler U4 to output a digital pulse signal with 3.3V level. The circuit adopts a valley value integration method and compares pulse peak values with valley values to extract pulse signals in signal voltage stably and reliably. And then eliminate the influence of quiescent current to the pulse signal, can still normally work even when the quiescent component is several times as much as the pulse component.

The overcurrent protection circuit 4 is shown in fig. 3 and comprises U7, U6A, U6B, U6C and U6D, wherein the 9 ends and 11 ends and the 10 ends and 12 ends of U6C and U6D are connected to form a basic RS flip-flop, the 1 end and 2 end of U6A and the 5 end and 6 end of U6B are connected in parallel to serve as inputs, the 3 end and 4 end of U6A are connected in parallel to serve as outputs to improve the output driving capability, and the R16 and R15 serve as a divider U7 to serve as a comparator. Specifically, the overcurrent protection circuit is also taken from a sampling resistor R14, when the circuit is overloaded or short-circuited, and the sampling voltage is higher than the reference voltage 2.5V of 431 through the partial voltage of R16 and R15, a low level is output to enable AN RS trigger consisting of U6D and U6C to overturn, so that AN indicator light LM2 is lightened to indicate overload, meanwhile, the grid of a MOS tube is turned off to lose high voltage, AN MBUS loop is cut off to reduce the sampling voltage, but the RS trigger keeps the overload turn-off state of the circuit all the time, and the circuit can not be in a normal state until the RS trigger can be restored after the reset switch AN1 is pressed. The overload protection circuit is different from other circuits which are switched off when overload occurs, the situation that repeated triggering is automatically recovered due to loss of triggering conditions after switching off can not occur, the safety of the circuit is ensured, the circuit can be recovered to a normal working state only under the situation that overload and short circuit are eliminated, and the situation that the circuit is damaged by repeated triggering for a long time can not occur.

The transmission signal driving circuit 2 is shown in fig. 4. The transmitting signal passes through an optical coupling isolation control Q1 field effect transistor to realize the output of a modulation signal, and a logic high level voltage of 36V and a logic low level voltage of 24V are transmitted.

As shown in fig. 5, the power module 1 is formed by connecting a 36V switch-type power supply boost module and a 24V switch-type power supply boost module in parallel. The power input range is wider, and 12V electricity is input into the electric energy input end of the electric energy input branch circuit through optimization selection.

Claims

1. An MBUS master controller reception detection circuit, characterized by: the device comprises a power module (1), a sending signal driving circuit (2), a receiving detection circuit (3) and an overcurrent protection circuit (4);

the transmission signal driving circuit (2) is connected with the MBUS +, and the MBUS-in the transmission signal driving circuit (2) is connected with the negative electrode of the power supply after sequentially passing through the protection turn-off MOS tube and the sampling resistor R14; the trigger end of the protection turn-off MOS tube is connected with an external main circuit after sequentially passing through an overcurrent protection circuit (4) and a receiving detection circuit (3);

the receiving detection circuit (3) comprises a sampling part and a detection part; one current output end of a sampling resistor R14 in the sampling part is directly connected with the positive end of an operational amplifier U5A to form a direct current amplifier, and the other current output end of the sampling resistor R14 in the sampling part is connected with U7 after passing through a resistor R16 and a voltage dividing resistor; the detection part receives an output signal of the operational amplifier U5A, the output signal of the operational amplifier U5A is divided into two paths in the detection part, one path passes through a valley detector consisting of D4, C7 and R9, the other path passes through D5, and the two paths of signals are input into U5B for comparison.

2. A MBUS master controller receive detect circuit as claimed in claim 1, wherein: the power module (1) is formed by connecting a 36V switch type power supply boosting module and a 24V switch type power supply boosting module in parallel.

3. The MBUS master controller reception detection circuit of claim 1, wherein: the overcurrent protection circuit (4) compares the voltage sampled by the resistor R6 with a voltage reference source after the voltage is subjected to resistor voltage division.