CN219513965U - FPGA-based switching power supply boost circuit - Google Patents
FPGA-based switching power supply boost circuit Download PDFInfo
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- CN219513965U CN219513965U CN202320947876.1U CN202320947876U CN219513965U CN 219513965 U CN219513965 U CN 219513965U CN 202320947876 U CN202320947876 U CN 202320947876U CN 219513965 U CN219513965 U CN 219513965U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The utility model relates to the technical field of electronic circuits, in particular to a switching power supply booster circuit based on an FPGA, which comprises a booster circuit and a compensation circuit, wherein the booster circuit comprises a chip Q1, and an electrolytic capacitor group and a ceramic capacitor group are connected in parallel with the input end of a power supply and the output of the power supply; the chip Q1 is connected with an inductor L1 and a Schottky diode D1; the compensating circuit comprises a triode, a slide rheostat R2 and a resistor R5, and a resistor R6 and a capacitor C8 are arranged on the triode in parallel. According to the utility model, current flows through the inductor L1 and the Schottky diode D1, then flows into the output electrolytic capacitor group and the ceramic capacitor group, the voltage at two ends of the electrolytic capacitor C3 and the ceramic capacitor C4 is raised, the structure is simple, the efficiency is high, the resistor R6 and the capacitor C8 are arranged on the triode in parallel, the capacitor C7 is connected on the resistor R7 in series, the capacitor C9 is arranged on the resistor R6 in series, and the voltage after voltage regulation is further compensated, so that the stability of the voltage is ensured.
Description
Technical Field
The utility model relates to a switching power supply booster circuit based on an FPGA, in particular to a switching power supply booster circuit based on an FPGA, and belongs to the technical field of electronic circuits.
Background
The FPGA software is mainly realized by high-speed AD sampling control based on parallel processing under multiple clock frequencies and full output digitalization of PWM signals, and the realization method of PWM signal output digitalization comprises the following steps: the generation of the synchronous signal PWMSNYC is completed by utilizing the accumulation of the counter, the frequency of the synchronous signal is the switching frequency of the power electronic equipment, the structure of the existing booster circuit is complex, the booster circuit is not provided with a compensation circuit, the lack of the compensation circuit can cause the output voltage of the circuit to be unstable, and the output of the output voltage synchronous signal and the generation of the digitization are seriously influenced.
Therefore, there is a need for an improvement in the switching power supply boost circuit of an FPGA to solve the above-mentioned problems.
Disclosure of Invention
The utility model aims to provide a switching power supply boost circuit based on an FPGA, when current flows through an inductor L1 and a Schottky diode D1, the current flows into an output electrolytic capacitor group and a ceramic capacitor group, the voltages at two ends of an electrolytic capacitor C3 and a ceramic capacitor C4 are increased, the structure is simple, the efficiency is high, a resistor R6 and a capacitor C8 are arranged on a pin 1 and a pin 3 of a triode in parallel, a capacitor C7 is connected on the resistor R7 in series, a capacitor C9 is arranged on the resistor R6 in series, and the voltage after voltage regulation is further compensated, so that the stability of the voltage is ensured.
In order to achieve the above purpose, the main technical scheme adopted by the utility model comprises the following steps:
the switching power supply booster circuit based on the FPGA comprises a booster circuit and a compensation circuit, wherein the booster circuit comprises a chip Q1, two ends of the chip Q1 are respectively connected with an input end of a power supply or an output end of the power supply, and the input end of the power supply and the output end of the power supply are connected with an electrolytic capacitor group and a ceramic capacitor group in parallel;
an inductor L1 is connected between the pin 5 and the pin 6 on the chip Q1, the inductor L1 is electrically connected to the positive electrode of the power input end, and one side of the inductor L1 is electrically connected with a Schottky diode D1;
the output end of the power supply is electrically connected with a slide rheostat R2, a resistor R3 and a resistor R4, and a pin 2 on the chip Q1 is electrically connected between the resistor R3 and the resistor R4;
the compensation circuit comprises a triode and a resistor R5 arranged between the slide rheostat R2 and the triode, wherein a resistor R7 is arranged on the resistor R5 in parallel, and a resistor R6 and a capacitor C8 are arranged on a pin 1 and a pin 3 of the triode in parallel.
Preferably, the electrolytic capacitor group comprises an electrolytic capacitor C1 and an electrolytic capacitor C3, the ceramic capacitor group comprises a ceramic capacitor C2 and a ceramic capacitor C4, the model of the electrolytic capacitor group is 470uF, and the model of the ceramic capacitor is 10uF;
the electrolytic capacitor C1 and the ceramic capacitor C2 are arranged on one side of the chip Q1 in parallel;
the electrolytic capacitor C3 and the ceramic capacitor C4 are arranged on the other side of the chip Q1 in parallel.
Preferably, the sliding resistor R2 has a model of 10kΩ, and the resistor R3 and the resistor R4 have a model of 390 Ω, wherein the sliding resistor R2 is adjusted to 10kΩ.
Preferably, a capacitor C7 is connected in series with the resistor R7, a capacitor C9 is connected in series with the resistor R6, and a negative electrode pin of the triode is grounded.
Preferably, the chip Q1 is LT1370, and the schottky diode D1 is STPS5L60.
Preferably, the pin 3 of the chip Q1 is grounded.
Preferably, the pin 1 of the chip Q1 is connected in series with a capacitor C5 and a capacitor R1, and the capacitor C5 and the capacitor R1 are connected in parallel with a capacitor C6.
The utility model has at least the following beneficial effects:
1. when electric current flows through inductance L1 and schottky diode D1, then flow into and export on electrolytic capacitor group and the ceramic capacitor group, electrolytic capacitor C3 and the voltage at ceramic capacitor C4 both ends have risen, simple structure, and is efficient, and the triode participate in 1 and participate in 3 on parallelly connected be provided with resistance R6 and electric capacity C8, have established ties on the resistance R7 and have had electric capacity C7, are established ties on the resistance R6 and are provided with electric capacity C9, carry out further compensation to the voltage after the voltage regulation, ensure voltage's stability.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model and do not constitute a limitation on the utility model. In the drawings:
FIG. 1 is a schematic circuit diagram of the present utility model;
FIG. 2 is a boost circuit diagram of the present utility model;
FIG. 3 is a compensation circuit diagram of the present utility model.
Detailed Description
The following detailed description of embodiments of the present utility model will be given with reference to the accompanying drawings and examples, by which the implementation process of how the present utility model can be applied to solve the technical problems and achieve the technical effects can be fully understood and implemented.
As shown in fig. 1-3, the FPGA-based switching power supply boost circuit provided in this embodiment includes a boost circuit and a compensation circuit, where the boost circuit includes a chip Q1, two ends of the chip Q1 are respectively connected with an input end of a power supply or an output end of the power supply, the input end of the power supply and the output end of the power supply are both connected in parallel with an electrolytic capacitor group and a ceramic capacitor group, the model of the chip Q1 is LT1370, and the model of the schottky diode D1 is STPS5L60;
an inductor L1 is connected between the pin 5 and the pin 6 on the chip Q1, the inductor L1 is electrically connected to the positive electrode of the power input end, one side of the inductor L1 is electrically connected with a Schottky diode D1, the Schottky diode D1 is used, the lower the forward voltage drop is, the better the lower the forward voltage drop is, and the conversion efficiency is improved;
the output end of the power supply is electrically connected with a slide rheostat R2, a resistor R3 and a resistor R4, and a pin 2 on the chip Q1 is electrically connected between the resistor R3 and the resistor R4;
since the current does not change suddenly, when the current flows through the inductor L1 and the schottky diode D1, and then flows into the output electrolytic capacitor group and the ceramic capacitor group, that is, the current is transferred from the inductor L1 to the electrolytic capacitor group and the ceramic capacitor group, the voltage across the electrolytic capacitor C3 and the ceramic capacitor C4 is raised as the magnetic field collapses in the inductor L1, the flowing direction of electrons is opposite to the conventional current direction, negative charges are accumulated on the left side of the inductor L1 due to the flowing of the current, and correspondingly, high voltage occurs on the right side due to the flowing of the electrons, so that the voltage is raised:
the compensation circuit comprises a triode and a resistor R5 arranged between the slide rheostat R2 and the triode, wherein the resistor R5 is connected with a resistor R7 in parallel, and a resistor R6 and a capacitor C8 are connected with a pin 1 and a pin 3 of the triode in parallel;
in the compensation circuit, a resistor R7 is arranged on a resistor R5 in parallel, a resistor R6 and a capacitor C8 are arranged on a pin 1 and a pin 3 of the triode in parallel, a capacitor C7 is connected on the resistor R7 in series, a capacitor C9 is connected on the resistor R6 in series, and a negative pin of the triode is grounded;
the compensation algorithm is as follows:
the voltage after voltage regulation can be further compensated, and the stability of the voltage is ensured.
Further, as shown in fig. 1 and 2, the electrolytic capacitor group includes an electrolytic capacitor C1 and an electrolytic capacitor C3, the ceramic capacitor group includes a ceramic capacitor C2 and a ceramic capacitor C4, the model of the electrolytic capacitor group is 470uF, and the model of the ceramic capacitor is 10uF;
the electrolytic capacitor C1 and the ceramic capacitor C2 are arranged on one side of the chip Q1 in parallel;
the electrolytic capacitor C3 and the ceramic capacitor C4 are arranged on the other side of the chip Q1 in parallel, the electrolytic capacitor and the ceramic capacitor are connected to the input end of the power supply or the output end of the power supply, the electrolytic capacitor C1 and the ceramic capacitor C2 are in one group, the electrolytic capacitor C3 and the ceramic capacitor C4 are in the other group, high-frequency signals in the current can be filtered, and the stability of the circuit is improved;
the model of slide rheostat R2 is 10KΩ, and resistance R3 and resistance R4 are 390 Ω, and wherein slide rheostat R2 adjusts to 10KΩ when, through the resistance that changes R2, can provide the maximum output and be 34 volts of voltage, and voltage is adjustable, promotes the convenience of use, and wherein the algorithm is:
further, as shown in fig. 3, pin 3 of chip Q1 is grounded, pin 1 of chip Q1 is connected in series with capacitor C5 and capacitor R1, capacitor C5 and capacitor R1 are connected in parallel with capacitor C6, and capacitor C5, capacitor R1 and capacitor C6 are used to control local loop frequency compensation, basically they help the controller adapt to small changes of output voltage to output clean direct current.
As shown in fig. 1 to 3, the principle of the FPGA-based switching power supply boost circuit provided in this embodiment is as follows:
when current flows through the inductor L1 and the schottky diode D1, then flows into the output electrolytic capacitor bank and the ceramic capacitor bank, that is, the current is transferred from the inductor L1 to the electrolytic capacitor bank and the ceramic capacitor bank, the voltage across the electrolytic capacitor C3 and the ceramic capacitor C4 is raised as the magnetic field collapses in the inductor L1, the flow direction of electrons is opposite to the conventional current direction, negative charges are accumulated on the left side of the inductor L1 due to the current flow, and correspondingly, high voltage occurs on the right side due to the electron outflow, so that the voltage is raised.
Certain terms are used throughout the description and claims to refer to particular components. Those of skill in the art will appreciate that a hardware manufacturer may refer to the same component by different names. The description and claims do not take the form of an element differentiated by name, but rather by functionality. As used throughout the specification and claims, the word "comprise" is an open-ended term, and thus should be interpreted to mean "include, but not limited to. By "substantially" is meant that within an acceptable error range, a person skilled in the art can solve the technical problem within a certain error range, substantially achieving the technical effect.
It should be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a product or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such product or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude that an additional identical element is present in a commodity or system comprising the element.
While the foregoing description illustrates and describes the preferred embodiments of the present utility model, it is to be understood that the utility model is not limited to the forms disclosed herein, but is not to be construed as limited to other embodiments, and is capable of numerous other combinations, modifications and environments and is capable of changes or modifications within the scope of the inventive concept as described herein, either as a result of the foregoing teachings or as a result of the knowledge or technology in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the utility model are intended to be within the scope of the appended claims.
Claims (7)
1. The FPGA-based switching power supply boost circuit comprises a boost circuit and a compensation circuit, and is characterized in that the boost circuit comprises a chip Q1, wherein two ends of the chip Q1 are respectively connected with an input end of a power supply or an output end of the power supply, and the input end of the power supply and the output end of the power supply are connected with an electrolytic capacitor group and a ceramic capacitor group in parallel;
an inductor L1 is connected between the pin 5 and the pin 6 on the chip Q1, the inductor L1 is electrically connected to the positive electrode of the power input end, and one side of the inductor L1 is electrically connected with a Schottky diode D1;
the output end of the power supply is electrically connected with a slide rheostat R2, a resistor R3 and a resistor R4, and a pin 2 on the chip Q1 is electrically connected between the resistor R3 and the resistor R4;
the compensation circuit comprises a triode and a resistor R5 arranged between the R2 and the triode, wherein a resistor R7 is arranged on the resistor R5 in parallel, and a resistor R6 and a capacitor C8 are arranged on a pin 1 and a pin 3 of the triode in parallel.
2. The FPGA-based switching power supply boost circuit of claim 1, wherein: the electrolytic capacitor group comprises an electrolytic capacitor C1 and an electrolytic capacitor C3, the ceramic capacitor group comprises a ceramic capacitor C2 and a ceramic capacitor C4, the model of the electrolytic capacitor group is 470uF, and the model of the ceramic capacitor is 10uF;
the electrolytic capacitor C1 and the ceramic capacitor C2 are arranged on one side of the chip Q1 in parallel;
the electrolytic capacitor C3 and the ceramic capacitor C4 are arranged on the other side of the chip Q1 in parallel.
3. The FPGA-based switching power supply boost circuit of claim 1, wherein: the type of the sliding rheostat R2 is 10KΩ, the type of the resistor R3 and the type of the resistor R4 are both 390 KΩ, and the sliding rheostat R2 is adjusted to 10KΩ.
4. The FPGA-based switching power supply boost circuit of claim 1, wherein: the resistor R7 is connected with a capacitor C7 in series, the resistor R6 is connected with a capacitor C9 in series, and the negative electrode pin of the triode is grounded.
5. The FPGA-based switching power supply boost circuit of claim 1, wherein: the chip Q1 is of the type LT1370, and the Schottky diode D1 is of the type STPS5L60.
6. The FPGA-based switching power supply boost circuit of claim 1, wherein: pin 3 of the chip Q1 is grounded.
7. The FPGA-based switching power supply boost circuit of claim 4, wherein: the pin 1 of the chip Q1 is connected with a capacitor C5 and a capacitor R1 in series, and the capacitor C5 and the capacitor R1 are connected with a capacitor C6 in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320947876.1U CN219513965U (en) | 2023-04-25 | 2023-04-25 | FPGA-based switching power supply boost circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320947876.1U CN219513965U (en) | 2023-04-25 | 2023-04-25 | FPGA-based switching power supply boost circuit |
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| Publication Number | Publication Date |
|---|---|
| CN219513965U true CN219513965U (en) | 2023-08-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320947876.1U Active CN219513965U (en) | 2023-04-25 | 2023-04-25 | FPGA-based switching power supply boost circuit |
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| CN (1) | CN219513965U (en) |
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- 2023-04-25 CN CN202320947876.1U patent/CN219513965U/en active Active
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