CN219513112U

CN219513112U - Diode device

Info

Publication number: CN219513112U
Application number: CN202320626951.4U
Authority: CN
Inventors: 张景超; 戚丽娜; 林茂; 井亚会; 俞义长; 赵善麒
Original assignee: Macmic Science & Technology Holding Co ltd
Current assignee: Macmic Science & Technology Holding Co ltd
Priority date: 2023-03-27
Filing date: 2023-03-27
Publication date: 2023-08-11
Anticipated expiration: 2033-03-27

Abstract

The present utility model provides a diode device comprising: a cathode metal layer; an n+ substrate located over the cathode metal layer; an N-drift region epitaxially formed over the n+ substrate; the high-impedance cell structures are arranged at the upper part of the N-drift region at intervals, and each high-impedance cell structure comprises two P+ type ion implantation regions and an impedance region positioned between the two P+ type ion implantation regions; and the anode metal layer is positioned on the N-drift region. The utility model can enhance the surge capacity of the diode device.

Description

Diode device

Technical Field

The utility model relates to the technical field of diode chips, in particular to a diode device.

Background

Compared with other semiconductor materials such as silicon, the silicon carbide material has wider forbidden bandwidth, higher critical breakdown electric field, higher saturation drift speed and higher thermal conductivity, and the superior material characteristics lead the silicon carbide device to have extremely wide application prospect in the fields of high frequency, high temperature resistance, radiation resistance and the like. So far, due to the application of charging piles, photovoltaics and the like in production and living, the silicon carbide schottky diode is required to have high enough forward surge capability, and one of the main bottlenecks faced by the current silicon carbide schottky diode is how to improve the surge capability of the device.

Disclosure of Invention

The utility model provides a diode device for solving the technical problems, which can enhance the surge capacity of the diode device.

The technical scheme adopted by the utility model is as follows:

a diode device, comprising: a cathode metal layer; an n+ substrate located over the cathode metal layer; an N-drift region epitaxially formed over the n+ substrate; the high-impedance cell structures are arranged at the upper part of the N-drift region at intervals, and each high-impedance cell structure comprises two P+ type ion implantation regions and an impedance region positioned between the two P+ type ion implantation regions; and the anode metal layer is positioned on the N-drift region.

The impedance region is an N-region, the doping concentration of the impedance region is smaller than that of the N-drift region, and the depth of the impedance region is the same as that of the P+ type ion implantation region.

The impedance region comprises an upper layer and a lower layer of P+ type ion layers, the upper layer of P+ type ion layers and the lower layer of P+ type ion layers are positioned in the N-drift region, a certain interval is reserved between the upper layer of P+ type ion layers and the lower layer of P+ type ion layers, wherein the upper layer of P+ type ion layers is connected with the first one of the two P+ type ion implantation regions and is not connected with the second one of the two P+ type ion implantation regions, and the lower layer of P+ type ion layers is connected with the second one of the two P+ type ion implantation regions and is not connected with the first one of the two P+ type ion implantation regions.

The utility model has the beneficial effects that:

according to the utility model, the N+ substrate is fixed on the cathode metal layer, and the N-drift region is formed by epitaxy, so that a plurality of high-impedance cell structures are arranged at the upper part of the N-drift region at intervals, each high-impedance cell structure comprises two P+ type injection regions and an impedance region positioned between the two P+ type injection regions, and then the anode metal layer is fixed on the N-drift region, therefore, the resistance of a current path of a part of a diode device can be increased through the arrangement of the high-impedance cell structures, and the surge capacity of the diode device can be enhanced.

Drawings

Fig. 1 is a schematic structural diagram of a diode device according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of a diode device with an N-region as an impedance region according to one embodiment of the present utility model;

fig. 3 is a schematic structural diagram of a diode device with an upper p+ ion layer and a lower p+ ion layer in an impedance region according to another embodiment of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

As shown in fig. 1, a diode device according to an embodiment of the present utility model includes: the device comprises a cathode metal layer 10, an N+ substrate 20, an N-drift region 30, a high-impedance cell structure 40 and an anode metal layer 50, wherein the N+ substrate 20 is positioned above the cathode metal layer 10, the N-drift region 30 is epitaxially formed on the N+ substrate 20, the high-impedance cell structure 40 is a plurality of high-impedance cell structures 40, the high-impedance cell structures 40 are arranged at the upper part of the N-drift region 30 at intervals, each high-impedance cell structure 40 comprises two P+ type ion implantation regions 41 and an impedance region 42 positioned between the two P+ type ion implantation regions 41, and the anode metal layer 50 is positioned above the N-drift region 30.

In one embodiment of the present utility model, only the high-impedance cell structure 40 may be present within the N-drift region 30, with a plurality of high-impedance cell structures 40 being repeated adjacently within the N-drift region 30. In another embodiment of the present utility model, a common cell may be present within the N-drift region 30, i.e. there may be one or more common cells spaced between at least two high impedance cell structures 40. The structure of the common cell is a common cell structure in the prior art.

In one embodiment of the present utility model, the implantation depth of the p+ type ion implantation region 41 in the high-resistance cell structure 40 is substantially the same as the implantation depth of the p+ type ion implantation region 41 in the normal cell, and the width of the interval between every two p+ type ion implantation regions 41 is substantially the same.

In one embodiment of the present utility model, as shown in fig. 2, the resistive region 42 may be an N-region with a low doping concentration, the doping concentration of the resistive region 42 is less than that of the N-drift region 30, which may be indicated as N-in fig. 2, and the depth of the resistive region 42 is the same as that of the p+ type ion implantation region 41, so that the resistance of the path of the current flowing from the anode metal layer 50 to the bottom of the p+ type ion implantation region 41 may be increased, and the resistance ratio of the resistive region to the N-drift region 30 may be increased, so that the voltage difference at both sides of the bottom of the p+ type ion implantation region 41 may reach the barrier height for opening the PN junction more quickly in the case of a large current, thereby enhancing the surge capability of the diode device. Wherein, the depth of the impedance region 42 is the same as the depth of the p+ type ion implantation region 41 can be confirmed by using a simulation means.

In another embodiment of the present utility model, as shown in fig. 3, the resistive region 42 may further include an upper p+ type ion layer and a lower p+ type ion layer, where the upper p+ type ion layer and the lower p+ type ion layer may be denoted by p+u and p+d, respectively, and the upper p+ type ion layer and the lower p+ type ion layer are located in the N-drift region 30 with a certain interval therebetween, where the upper p+ type ion layer p+u is connected to a first one of the two p+ type ion implantation regions 41 and not connected to a second one of the two p+ type ion implantation regions 41, and the lower p+ type ion layer p+d is connected to a second one of the two p+ type ion implantation regions 41 and not connected to the first one of the two p+ type ion implantation regions 41.

In one embodiment of the present utility model, the implantation energy of the p+ type ion layer p+d of the lower layer is greater than the implantation energy of the p+ type ion layer p+u of the upper layer.

In one embodiment of the present utility model, the upper surface of N-drift region 30 forms a schottky contact with anode metal layer 50, the upper surface of p+ type ion implantation region 41 forms an ohmic contact with anode metal layer 50, and the lower surface of n+ substrate 20 forms an ohmic contact with cathode metal layer 10.

According to the diode device provided by the embodiment of the utility model, the N+ substrate is fixed on the cathode metal layer, the N-drift region is formed by epitaxy, a plurality of high-impedance cell structures are arranged at the upper part of the N-drift region at intervals, each high-impedance cell structure comprises two P+ type injection regions and an impedance region positioned between the two P+ type injection regions, and then the anode metal layer is fixed on the N-drift region, so that the resistance of a current path of a part of the diode device can be increased through the arrangement of the high-impedance cell structures, and the surge capacity of the diode device can be enhanced.

In the description of the present utility model, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The meaning of "a plurality of" is two or more, unless specifically defined otherwise.

In the present utility model, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

In the present utility model, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

While embodiments of the present utility model have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the utility model, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the utility model.

Claims

1. A diode device, comprising:

a cathode metal layer;

an n+ substrate located over the cathode metal layer;

an N-drift region epitaxially formed over the n+ substrate;

the high-impedance cell structures are arranged at the upper part of the N-drift region at intervals, and each high-impedance cell structure comprises two P+ type ion implantation regions and an impedance region positioned between the two P+ type ion implantation regions;

and the anode metal layer is positioned on the N-drift region.

2. The diode device of claim 1, wherein the resistive region is an N-region having a doping concentration less than a doping concentration of the N-drift region, and wherein the resistive region has a depth equal to a depth of the p+ -type ion implantation region.

3. The diode device of claim 1, wherein the resistive region comprises upper and lower p+ -type ion layers within the N-drift region with a space therebetween, wherein the upper p+ -type ion layer is connected to a first of the two p+ -type ion implantation regions and not connected to a second of the two p+ -type ion implantation regions, and the lower p+ -type ion layer is connected to a second of the two p+ -type ion implantation regions and not connected to the first of the two p+ -type ion implantation regions.