CN219420581U - Overvoltage and reverse connection protection circuit of double MOS (metal oxide semiconductor) tube - Google Patents
Overvoltage and reverse connection protection circuit of double MOS (metal oxide semiconductor) tube Download PDFInfo
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- CN219420581U CN219420581U CN202320560616.9U CN202320560616U CN219420581U CN 219420581 U CN219420581 U CN 219420581U CN 202320560616 U CN202320560616 U CN 202320560616U CN 219420581 U CN219420581 U CN 219420581U
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Abstract
The utility model discloses an overvoltage and reverse connection protection circuit of a double MOS (metal oxide semiconductor) tube, which comprises an NMOS (N-channel metal oxide semiconductor) tube Q1, a PMOS tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a triode Q2, a first diode D1 and a second diode D2. In the circuit, when the power supply is reversely connected, the NMOS tube Q1 is in a closed state, and the voltage cannot enter the inside to protect the internal circuit, so that the reverse connection protection function is realized; when the power supply does not exceed a specific voltage, the second diode D2 is in a closed state, and the PMOS tube Q3 can be normally conducted through the voltage division of the resistors R6 and R7; when the input power exceeds a specific voltage, the second diode D2 is turned on, so that the triode Q2 is turned on, and the PMOS transistor Q3 is turned off, so that the voltage cannot enter the interior to protect the internal circuit.
Description
Technical Field
The utility model belongs to the technical field of overvoltage and reverse connection protection, and particularly relates to an overvoltage and reverse connection protection circuit of a double MOS tube.
Background
In the field of electronic applications, in view of an external power supply and some instabilities during use, some circuits are required to be designed to protect the internal circuits from damage caused by external interference. Some devices typically operate at voltages within a specified range, such as within 36V, but many times internal circuit damage occurs due to excessive or reverse connection of external voltages.
Disclosure of Invention
In order to solve the technical problems in the prior art, the utility model provides an overvoltage and reverse connection protection circuit for a double MOS tube, which solves the problem of internal circuit damage caused by overvoltage or reverse connection of external voltage.
The technical scheme adopted by the utility model for solving the technical problems is as follows:
the overvoltage and reverse connection protection circuit of the double MOS tube comprises an NMOS tube Q1, a PMOS tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a triode Q2, a first diode D1 and a second diode D2;
the drain electrode of the NMOS tube Q1 is connected with the input cathode, the grid electrode of the NMOS tube Q1 is connected with the input anode through a first resistor R1, and the source electrode of the NMOS tube Q1 is connected with the output cathode; the drain electrode of the NMOS tube Q1 is connected with the source electrode of the NMOS tube Q1 through a first capacitor C1 and a second resistor R2; the second capacitor C2, the third resistor R3 and the first diode D1 are connected in parallel between the grid electrode of the NMOS tube Q1 and the source electrode of the NMOS tube Q1, wherein the positive electrode of the first diode D1 is connected with the source electrode of the NMOS tube Q1; the sixth resistor R6 and the seventh resistor R7 are connected in series between the input positive electrode and the output negative electrode; the source electrode of the PMOS tube Q3 is connected with the input positive electrode, the drain electrode of the PMOS tube Q3 is connected with the output positive electrode, and the grid electrode of the PMOS tube Q3 is connected with the connection point of the sixth resistor R6 and the seventh resistor R7; the fourth resistor R4 and the second diode D2 are connected in series between the input positive electrode and the output negative electrode, wherein the positive electrode of the second diode D2 is connected with the output negative electrode; the collector of the triode Q2 is connected with the connection point of the sixth resistor R6 and the seventh resistor R7, the base of the triode Q2 is connected with the connection point of the fourth resistor R4 and the second diode D2 through the fifth resistor R5, and the emission set of the triode Q2 is connected with the input positive electrode.
Further, the first diode D1 is a zener diode, and the model is SMB3Z12A.
Further, the second diode D2 is a transient suppression diode, and the model is SMAJ33A.
Further, the triode Q2 is a PNP triode, and the model is 2SB1188-Q.
Further, the model of the PMOS tube Q3 is YJG40GP06A.
Further, the model of the NMOS transistor Q1 is YJG30N06A.
Compared with the prior art, the utility model has the following advantages:
in the overvoltage and reverse connection protection circuit of the double MOS tube, the NMOS tube Q1 is used for power supply reverse connection protection, when the power supply is reversely connected, the NMOS tube Q1 is in a closed state, and voltage cannot enter the inside to protect an internal circuit, so that the reverse connection protection function is realized; the second diode D2, the triode Q2, the PMOS tube Q3 and the triode D1 finish overvoltage protection of the power supply; when the power supply does not exceed a specific voltage, the second diode D2 is in a closed state, and the PMOS tube Q3 can be normally conducted through the voltage division of the resistors R6 and R7; when the input power exceeds a specific voltage, as the second diode D2 is conducted, the triode Q2 is conducted, the PMOS tube Q3 is in a closed state, the voltage cannot enter the inside to protect an internal circuit, and the voltage stabilizing tube D1 protects the NMOS tube Q1 from being damaged; after the voltage is recovered to be normal, the device can work normally and has strong adaptability.
Drawings
Fig. 1 is a diagram of an overvoltage and reverse connection protection circuit for a dual MOS transistor according to the present utility model.
Detailed Description
The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the detailed description is presented herein to illustrate the utility model and not to limit the utility model. In addition, the technical features of the embodiments of the present utility model described below may be combined with each other as long as they do not collide with each other.
The utility model provides a protection circuit with good safety and simple realization for overvoltage and reverse connection of an MOS tube, which comprises an NMOS tube Q1, a PMOS tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a triode Q2, a first diode D1 and a second diode D2;
wherein: the drain electrode of the NMOS tube Q1 is connected with the input cathode, the grid electrode of the NMOS tube Q1 is connected with the input anode through a first resistor R1, and the source electrode of the NMOS tube Q1 is connected with the output cathode; the drain electrode of the NMOS tube Q1 is connected with the source electrode of the NMOS tube Q1 through a first capacitor C1 and a second resistor R2; the second capacitor C2, the third resistor R3 and the first diode D1 are connected in parallel between the grid electrode of the NMOS tube Q1 and the source electrode of the NMOS tube Q1, wherein the positive electrode of the first diode D1 is connected with the source electrode of the NMOS tube Q1; the sixth resistor R6 and the seventh resistor R7 are connected in series between the input positive electrode and the output negative electrode; the source electrode of the PMOS tube Q3 is connected with the input positive electrode, the drain electrode of the PMOS tube Q3 is connected with the output positive electrode, and the grid electrode of the PMOS tube Q3 is connected with the connection point of the sixth resistor R6 and the seventh resistor R7; the fourth resistor R4 and the second diode D2 are connected in series between the input positive electrode and the output negative electrode, wherein the positive electrode of the second diode D2 is connected with the output negative electrode; the collector of the triode Q2 is connected with the connection point of the sixth resistor R6 and the seventh resistor R7, the base of the triode Q2 is connected with the connection point of the fourth resistor R4 and the second diode D2 through the fifth resistor R5, and the emission set of the triode Q2 is connected with the input positive electrode.
When the power supply is reversely connected, the NMOS tube Q1 is in a closed state, and voltage cannot enter the interior so as to protect an internal circuit, so that a reverse connection protection function is realized; when the power supply does not exceed a specific voltage, the second diode D2 is in a closed state, and the PMOS tube Q3 can be normally conducted through the voltage division of the resistors R6 and R7; when the input power exceeds a specific voltage, the second diode D2 is turned on, so that the triode Q2 is turned on, and the PMOS transistor Q3 is turned off, so that the voltage cannot enter the interior to protect the internal circuit.
Specifically, as shown in fig. 1, the overvoltage and reverse connection protection circuit for the double MOS transistor according to the embodiment of the present utility model includes an NMOS transistor Q1, a PMOS transistor Q3, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a capacitor C1, a capacitor C2, a triode Q2, a diode D1 and a diode D2; the drain electrode of the NMOS tube Q1 is connected with the input cathode, the grid electrode of the NMOS tube Q1 is connected with the input anode through a resistor R1, and the source electrode of the NMOS tube Q1 is connected with the output cathode; after the capacitor C1 and the resistor R2 are connected in series, one end of the capacitor C is connected with the source electrode of the NMOS tube Q1, and the other end of the capacitor C is connected with the drain electrode of the NMOS tube Q1; the capacitor C2, the resistor R3 and the diode D1 are connected in parallel between the grid electrode of the NMOS tube Q1 and the source electrode of the NMOS tube Q1; the source electrode of the PMOS tube Q3 is connected with the input positive electrode, and the drain electrode of the PMOS tube Q3 is connected with the output positive electrode; the resistor R6 and the resistor R7 are connected in series between the input anode and the output cathode; the grid electrode of the PMOS tube Q3 is connected with one end of a resistor R6, one end of a resistor R7 and the collector electrode of a triode Q2; the diode D2 and the resistor R4 are connected in series between the input anode and the output cathode; one end of the resistor R5 is connected with the base electrode of the triode Q2, and the other end of the resistor R5 is connected with R4 and D2; the triode Q2 emission set is connected with the positive electrode of the power supply input.
In one embodiment, the diode D1 is a zener diode, so as to ensure the on of the NMOS transistor under normal connection and the protection of the NMOS transistor Q1 under excessive pressure, and the model of the diode D1 is SMB3Z12A.
In one embodiment, the capacitor C1 and the resistor R2 implement bleeder protection for the NMOS transistor when power is off.
In one embodiment, transistor Q2 is a PNP transistor, model 2SB1188-Q.
In one embodiment, diode D2 is a transient suppression diode, model SMAJ33A.
In one embodiment, the PMOS transistor is model YJG40GP06A.
In one embodiment, the model of the NMOS tube is YJG40GP06A.
In the double-MOS tube protection circuit, the NMOS tube Q1 is used for power supply reverse connection protection, when the power supply is in reverse connection, a diode between the source electrode and the drain electrode prevents current from flowing, so that the NMOS tube Q1 is in a closed state, and voltage cannot enter the inside to protect an internal circuit, and the reverse connection protection function is realized.
The diode D2, the triode Q2, the PMOS tube Q3 and the triode D1 finish overvoltage protection of the power supply; when the power supply does not exceed 36V, the diode D2 is in an off state, and the voltage of the grid electrode and the source electrode of the PMOS tube Q3 meets the starting condition through the voltage division of the resistors R6 and R7, so that the PMOS tube can be normally conducted; the voltage stabilizing diode D1 stabilizes the starting voltage of the NMOS tube within a specified range, and ensures the normal operation of the NMOS tube.
When the input power exceeds 36V, the diode D2 is conducted, so that the emission voltage of the triode Q2 is larger than the base voltage and is conducted, the grid and source voltages of the PMOS tube Q3 are zero at the moment, the PMOS tube is in a closed state, the voltage cannot enter the inside to protect an internal circuit, and the voltage stabilizing tube D1 protects the NMOS tube Q1 from being damaged.
After the voltage is recovered to be normal, the device can work normally and has strong adaptability.
Although embodiments of the present utility model have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. The overvoltage and reverse connection protection circuit for the double MOS tube is characterized by comprising an NMOS tube Q1, a PMOS tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a triode Q2, a first diode D1 and a second diode D2;
the drain electrode of the NMOS tube Q1 is connected with the input cathode, the grid electrode of the NMOS tube Q1 is connected with the input anode through a first resistor R1, and the source electrode of the NMOS tube Q1 is connected with the output cathode; the drain electrode of the NMOS tube Q1 is connected with the source electrode of the NMOS tube Q1 through a first capacitor C1 and a second resistor R2; the second capacitor C2, the third resistor R3 and the first diode D1 are connected in parallel between the grid electrode of the NMOS tube Q1 and the source electrode of the NMOS tube Q1, wherein the positive electrode of the first diode D1 is connected with the source electrode of the NMOS tube Q1; the sixth resistor R6 and the seventh resistor R7 are connected in series between the input positive electrode and the output negative electrode; the source electrode of the PMOS tube Q3 is connected with the input positive electrode, the drain electrode of the PMOS tube Q3 is connected with the output positive electrode, and the grid electrode of the PMOS tube Q3 is connected with the connection point of the sixth resistor R6 and the seventh resistor R7; the fourth resistor R4 and the second diode D2 are connected in series between the input positive electrode and the output negative electrode, wherein the positive electrode of the second diode D2 is connected with the output negative electrode; the collector of the triode Q2 is connected with the connection point of the sixth resistor R6 and the seventh resistor R7, the base of the triode Q2 is connected with the connection point of the fourth resistor R4 and the second diode D2 through the fifth resistor R5, and the emission set of the triode Q2 is connected with the input positive electrode.
2. The overvoltage and reverse connection protection circuit for a double MOS transistor according to claim 1, wherein the first diode D1 is a zener diode, and the model is SMB3Z12A.
3. The double-MOS-tube overvoltage and reverse-junction protection circuit according to claim 1, wherein the second diode D2 is a transient suppression diode, and is of the type SMAJ33A.
4. The double-MOS transistor overvoltage and reverse connection protection circuit according to claim 1, wherein the triode Q2 is a PNP type triode with the model number of 2SB1188-Q.
5. The overvoltage and reverse connection protection circuit for a double-MOS transistor according to claim 1, wherein the model of the PMOS transistor Q3 is YJG40GP06A.
6. The overvoltage and reverse connection protection circuit for a double-MOS transistor according to claim 1, wherein the NMOS transistor Q1 is of the type YJG30N06A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320560616.9U CN219420581U (en) | 2023-03-21 | 2023-03-21 | Overvoltage and reverse connection protection circuit of double MOS (metal oxide semiconductor) tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320560616.9U CN219420581U (en) | 2023-03-21 | 2023-03-21 | Overvoltage and reverse connection protection circuit of double MOS (metal oxide semiconductor) tube |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219420581U true CN219420581U (en) | 2023-07-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320560616.9U Active CN219420581U (en) | 2023-03-21 | 2023-03-21 | Overvoltage and reverse connection protection circuit of double MOS (metal oxide semiconductor) tube |
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| Country | Link |
|---|---|
| CN (1) | CN219420581U (en) |
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2023
- 2023-03-21 CN CN202320560616.9U patent/CN219420581U/en active Active
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