CN219394482U

CN219394482U - Power supply switching trigger circuit, power supply switching circuit, chip and electronic equipment

Info

Publication number: CN219394482U
Application number: CN202320048504.5U
Authority: CN
Inventors: 叶学锋; 刘帅锋
Original assignee: Hefei Chipsea Electronics Technology Co Ltd
Current assignee: Hefei Chipsea Electronics Technology Co Ltd
Priority date: 2023-01-06
Filing date: 2023-01-06
Publication date: 2023-07-21
Anticipated expiration: 2033-01-06

Abstract

The embodiment of the application provides a power supply switching trigger circuit, a power supply switching circuit, a chip and electronic equipment, and the power supply switching trigger circuit comprises: an output node for outputting a trigger signal; a first control unit for initializing the trigger signal to a low level; the second control unit is used for enabling the trigger signal to be low level when the power-on reset signal of the first power supply is high level; a third control unit for making the trigger signal be high level when the power-on reset signal is low level; the delay unit is used for delaying the power-on reset signal; the fourth control unit is used for closing the third control unit when the trigger signal and the power-on reset signal are both in low level; and the fifth control unit is used for closing the first control unit and opening the third control unit when the delayed power-on reset signal is at a high level. The trigger signal can be output to be high level when the first power supply is powered down, and the power supply is triggered to be switched from the first power supply to the second power supply.

Description

Power supply switching trigger circuit, power supply switching circuit, chip and electronic equipment

Technical Field

The application relates to the technical field of electronic circuits, in particular to a power supply switching trigger circuit, a power supply switching circuit, a chip and electronic equipment.

Background

In the related art, the real-time clock module is powered by a plurality of power supplies, but the technical scheme in the related art cannot ensure quick switching when the power supplies are powered down.

Disclosure of Invention

In view of the above problems, embodiments of the present application provide a power switching trigger circuit, a power switching circuit, a chip, and an electronic device, so as to solve the above technical problems.

In a first aspect, an embodiment of the present application provides a power switching trigger circuit, including: the output node is used for outputting a trigger signal, wherein when the trigger signal is in a high level, the power supply is triggered to be switched from the first power supply to the second power supply; the first control unit is connected with the output node and is used for enabling the trigger signal to be in a low level initially; the second control unit is connected with the output node and is used for enabling the trigger signal to be low level when the power-on reset signal of the first power supply is high level; the third control unit is connected with the output node and is used for enabling the trigger signal to be in a high level when the power-on reset signal is in a low level; the delay unit is used for delaying the power-on reset signal; the fourth control unit is connected with the third control unit and is used for closing the third control unit when the trigger signal and the power-on reset signal are both in low level; the fifth control unit is connected with the first control unit and the third control unit and is used for closing the first control unit and opening the third control unit when the delayed power-on reset signal is at a high level; wherein, the power-on reset signal is high level to represent the release state, and the power-on reset signal is low level to represent the reset state. According to the embodiment of the application, according to the power-on reset signal of the first power supply, before the first power supply is powered on for the first time and does not reach the power-on threshold voltage, the output trigger signal is of a low level; after reaching the power-on threshold voltage, the output trigger signal is kept at a low level; if the first power supply is powered down, the output trigger signal is changed into a high level, and the power supply is triggered to be switched from the first power supply to the second power supply, so that the first power supply can be quickly switched to the second power supply when the first power supply is powered down.

Optionally, the fourth control unit is configured to close the third control unit when the trigger signal and the delayed power-on reset signal are both at low levels.

Optionally, the above circuit further includes: and a sixth control unit for disconnecting the third control unit from the fourth control unit when either one of the power-on reset signal and the trigger signal is at a high level and the other is at a low level.

Optionally, the second control unit includes: the first switch is connected between the reference end and the output node, is turned on when the power-on reset signal is at a high level, and is turned off when the power-on reset signal is at a low level.

Optionally, the third control unit includes: the second switch and the third switch are connected in series between the output node and the third power supply, wherein the third power supply is the larger one of the first power supply and the second power supply; the second switch is turned on when the power-on reset signal is at a low level and turned off when the power-on reset signal is at a high level; the control end of the third switch is connected with the fourth control unit and the fifth control unit.

Optionally, the fourth control unit includes: the fourth switch and the fifth switch are connected in series between the third power supply and the control end of the third switch; the fourth switch is turned on when the trigger signal is at a low level and turned off when the trigger signal is at a high level; the fifth switch is turned on when the delayed power-on reset signal is at a low level, and turned off when the delayed power-on reset signal is at a high level.

Optionally, the fifth control unit includes: the sixth switch is connected between the reference end and the control end of the third switch; the sixth switch is turned on when the delayed power-on reset signal is at a high level, and turned off when the delayed power-on reset signal is at a low level; the third switch is turned on when the voltage of the control terminal thereof is at a low level.

Optionally, the above circuit further includes: exclusive OR logic for exclusive OR operating the power-on reset signal and the trigger signal; the seventh switch is connected between the control ends of the fourth control unit and the third switch, and is disconnected when the exclusive OR logic outputs a high level so as to disconnect the fourth control unit from the third control unit; the seventh switch is turned on when the exclusive or logic outputs a low level.

Optionally, the first control unit includes: an eighth switch connected between the output node and the reference terminal; a coupling unit for coupling the third power supply to the control terminal of the eighth switch; the eighth switch is turned on when the voltage of the control terminal is at a high level; the sixth switch is also connected between the reference terminal and the control terminal of the eighth switch.

Optionally, the fifth control unit further includes: and the ninth switch is connected between the control end of the third switch and the control end of the eighth switch and the first end of the sixth switch, wherein the second end of the sixth switch is connected with the reference end.

Optionally, the first end of the fourth switch is connected with the third power supply, and the second end of the fourth switch is connected with the first end of the fifth switch; wherein the fifth control unit further comprises: a tenth switch connected between the first end of the sixth switch and the second end of the fifth switch; the tenth switch is turned on when the power-on reset signal is at a high level and turned off when the power-on reset signal is at a low level.

Optionally, the above circuit further includes: an eleventh switch, the first end of the eleventh switch is connected with the reference end, and the second end of the eleventh switch is connected with the control end of the third switch and the control end of the eighth switch; the eleventh switch is turned on when the trigger signal is at a high level, and turned off when the trigger signal is at a low level.

In a second aspect, embodiments of the present application provide a power supply switching circuit, including: the above-described circuit; and the switching circuit is used for switching the power supply from the first power supply to the second power supply when the trigger signal is at a high level.

In a third aspect, an embodiment of the present application provides a chip including the above-described circuit.

In a fourth aspect, an embodiment of the present application provides an electronic device, including a device main body and the above-mentioned chip disposed on the device main body.

According to the power supply switching trigger circuit, the chip and the electronic equipment, according to the power-on reset signal of the first power supply, the trigger signal is output to be in a low level before the first power supply is electrified for the first time and does not reach the power-on threshold voltage; after reaching the power-on threshold voltage, the output trigger signal is kept at a low level; if the first power supply is powered down, the output trigger signal is changed into a high level, and the power supply is triggered to be switched from the first power supply to the second power supply, so that the first power supply can be quickly switched to the second power supply when the first power supply is powered down.

These and other aspects of the present application will be more readily apparent from the following description of the embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 shows a schematic structural diagram of a micro control unit according to an embodiment of the present application.

Fig. 2 shows a schematic structural diagram of a power supply switching circuit according to an embodiment of the present application.

Fig. 3 shows a schematic structural diagram of a power switching trigger circuit according to an embodiment of the present application.

Fig. 4 is a schematic diagram illustrating a trigger signal timing provided in an embodiment of the present application.

Fig. 5 shows a schematic structural diagram of a power switching trigger circuit according to an embodiment of the present application.

Fig. 6 shows a circuit diagram of a power supply switching trigger circuit provided in an embodiment of the present application.

Fig. 7 is a schematic diagram illustrating a trigger signal timing provided in an embodiment of the present application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

In order to better understand the solution of the present application, the following description will make clear and complete descriptions of the technical solution of the embodiment of the present application with reference to the accompanying drawings in the embodiment of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the embodiment of the application, at least one refers to one or more; plural means two or more. In the description of the present application, the words "first," "second," "third," and the like are used solely for the purpose of distinguishing between descriptions and not necessarily for the purpose of indicating or implying a relative importance or order.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, the terms "comprising," "including," "having," and variations thereof herein mean "including but not limited to," unless expressly specified otherwise.

It should be noted that, in the embodiment of the present application, "and/or" describe the association relationship of the association object, which means that three relationships may exist, for example, a and/or B may be represented: a exists alone, A and B exist together, and B exists alone.

It should be noted that in the embodiments of the present application, "connected" is understood to mean electrically connected, and two electrical components may be connected directly or indirectly between two electrical components. For example, a may be directly connected to B, or indirectly connected to B via one or more other electrical components.

The power switching circuit 100 provided by the present application may be applied to a micro control unit (Microcontroller Unit, MCU) 200 as shown in fig. 1, wherein the micro control unit 200 includes a processor 21 and a Real Time Clock (RTC) circuit 22, wherein the power switching circuit 100 selects a power source for supplying power to the real time clock circuit 22. The power sources may include, but are not limited to, a first power source that may be the primary power source and a second power source that may be the backup power source. For example, the first power source may be derived from the power module processing an external power source and the second power source may be a battery.

The embodiment of the application provides a power supply switching circuit.

Fig. 2 shows a schematic structural diagram of a power switching circuit provided in an embodiment of the present application, and as shown in fig. 2, the power switching circuit 100 includes: a power supply switching trigger circuit 110 and a switching circuit 120. The power switching trigger circuit 110 generates a trigger signal Vsel based on a power-on reset signal RST of the first power supply VDD1 to switch the power supply from the first power supply VDD1 to the second power supply VDD2 when the first power supply VDD1 is powered down.

As one embodiment, as shown in fig. 2, the Power-On Reset signal RST is output by a Power-On Reset (POR) module. And a POR module configured to detect the voltage of the first power supply VDD1 and output a power-on reset signal RST, wherein a low level is output when the voltage of the first power supply VDD1 does not reach a threshold value, and a high level is output when the voltage of the first power supply VDD1 reaches the threshold value. The low level of the power-on reset signal RST of the first power supply VDD1 indicates a reset state, and the high level of the power-on reset signal RST indicates a release state.

The power switching trigger circuit 110 outputs a trigger signal Vsel to be at a low level according to the power-on reset signal of the first power supply VDD1 before the first power supply VDD1 is powered on for the first time and does not reach the power-on threshold voltage; after reaching the power-on threshold voltage, the output trigger signal Vsel is kept at a low level; if the first power supply VDD1 is powered down, the output trigger signal Vsel becomes high level, triggering the switching of the power supply from the first power supply VDD1 to the second power supply VDD2. The switching circuit 120 switches the power supply source to the second power supply VDD2 when the trigger signal Vsel is at a high level.

It should be understood that the terms "high" and "low" in this specification are generally relative to the voltage at the reference terminal. As an example, the reference terminal may be the ground terminal GND, which may be regarded as the reference voltage 0, and the low level may be 0. As an example, the reference terminal may receive a non-0 reference voltage in which the low level may not be 0.

The power supply switching trigger circuit 110 of the present embodiment is described below.

Fig. 3 shows a schematic block diagram of a power switching trigger circuit 110 provided in an embodiment of the present application, and as shown in fig. 3, the power switching trigger circuit 110 includes: an output node Q1 for outputting a trigger signal Vsel, wherein when the trigger signal Vsel is at a high level, the trigger signal is used for triggering the switching of the power supply from the first power supply VDD1 to the second power supply VDD2; a delay unit 117 for delaying the power-on reset signal RST; a first control unit 111 connected to the output node Q1 for initializing the trigger signal Vsel to a low level; a second control unit 112 connected to the output node Q1 for setting the trigger signal Vsel to a low level when the power-on reset signal RST of the first power supply VDD1 is at a high level; a third control unit 113 connected to the output node Q1 for setting the trigger signal Vsel to a high level when the power-on reset signal RST is at a low level; a fourth control unit 114 connected to the third control unit 113 for turning off the third control unit 113 when the trigger signal Vsel and the power-on reset signal RST are both at low levels; the fifth control unit 115 is connected to the first control unit 111 and the third control unit 113, and is configured to turn off the first control unit 111 and turn on the third control unit 113 when the delayed power-on reset signal RST is at a high level. The high level of the power-on reset signal RST indicates a released state, and the low level of the power-on reset signal RST indicates a reset state.

Next, the operation of the power switching flip-flop circuit 110 will be described with reference to the timing chart of the power-on reset signal RST and the trigger signal Vsel shown in fig. 4.

In the initial state, as shown in fig. 4, the first power supply VDD1 is not powered up, the power-on reset signal RST is at a low level, and the first control unit 111 makes the trigger signal Vsel be at a low level initially, that is, the output node Q1 is at a low level. Meanwhile, since the power-on reset signal RST is at a low level and the second control unit 112 makes the trigger signal Vsel at a low level when the power-on reset signal RST of the first power supply VDD1 is at a high level, the output node Q1 is not controlled by the second control unit 112; since the power-on reset signal RST and the trigger signal Vsel are both low, the fourth control unit 114 turns off the third control unit 113 when the trigger signal Vsel and the delayed power-on reset signal RST are both low, and thus the output node Q1 is not controlled by the third control unit 113. Therefore, as shown in fig. 4, the trigger signal Vsel is low in the initial state.

When the first power supply VDD1 is powered up and the voltage does not reach the power-up threshold voltage, the power-up reset signal RST is at a low level and the trigger signal Vsel is also kept at a low level as shown in fig. 4.

When the first power supply VDD1 is powered up and reaches a power-up threshold voltage, the power-up reset signal RST is inverted from a low level to a high level as shown in fig. 4. The second control unit 112 sets the trigger signal Vsel to a low level when the power-on reset signal RST of the first power supply VDD1 is a high level. Meanwhile, when the delayed power-on reset signal RST is at a high level, the fifth control unit 115 turns off the first control unit 111, and the output node Q1 is not controlled by the first control unit 111. The fifth control unit 115 turns on the third control unit 113 when the delayed power-on reset signal RST is at a high level, and the third control unit 113 turns on the trigger signal Vsel at a high level when the power-on reset signal RST is at a low level, so that the output node Q1 is not controlled by the third control unit 113. Therefore, as shown in fig. 4, the power-on reset signal RST is at a high level, and the trigger signal Vsel is maintained at a low level.

In some examples, after the first power supply VDD1 is powered up and reaches a power-up threshold voltage, either one of the first power supply VDD1 and the second power supply VDD2 may be used as a power supply.

When the first power supply VDD1 is powered down below the power-down threshold voltage, the power-on reset signal RST is inverted from a high level to a low level as shown in fig. 4. At this time, since the delay unit 117 delays the power-on reset signal RST, the delayed power-on reset signal RST remains at a high level, and the fifth control unit 115 keeps turning off the first control unit 111 and keeps turning on the third control unit 113. Accordingly, the output node Q1 is controlled by the third control unit 113. The third control unit 113 sets the trigger signal Vsel to a high level when the power-on reset signal RST is at a low level. Accordingly, as shown in fig. 4, the power-on reset signal RST is inverted from a high level to a low level, and the trigger signal Vsel is inverted to a high level.

The third control unit 113 takes a certain time to change the trigger signal Vsel from the low level to the high level, while the fourth control unit 114 turns off the third control unit 113 when both the trigger signal Vsel and the power-on reset signal RST are at the low level, and thus may cause the third control unit 113 to be turned off in a case where the trigger signal Vsel does not change from the low level to the high level, thereby causing a trigger failure. For this reason, the fourth control unit 114 turns off the third control unit 113 when the trigger signal Vsel and the delayed power-on reset signal RST are both low. Accordingly, when the power-on reset signal RST is inverted from the high level to the low level, the delayed power-on reset signal RST is kept at the high level, and the condition that both the trigger signal Vsel and the delayed power-on reset signal RST are at the low level is not satisfied, the fourth control unit 114 does not turn off the third control unit 113, and when the delayed power-on reset signal RST becomes the low level, the fourth control unit 114 turns off the third control unit 113.

Referring to fig. 4 and the above description, in the embodiment of the present application, before the first power VDD1 is powered up for the first time and does not reach the power-up threshold voltage, the output trigger signal Vsel is at a low level; after reaching the power-on threshold voltage, the output trigger signal Vsel is kept at a low level; if the first power supply VDD1 is powered down, the output trigger signal Vsel becomes high level, and the switching of the power supply from the first power supply VDD1 to the second power supply VDD2 is triggered, so that the fast switching to the second power supply VDD2 when the first power supply VDD1 is powered down can be realized.

In some embodiments, as shown in fig. 5, the power switching trigger circuit 110 further includes: the sixth control unit 116 is configured to disconnect the third control unit 113 from the fourth control unit 114 when either one of the power-on reset signal RST and the trigger signal Vsel is at a high level and the other is at a low level. In conjunction with the foregoing description, in the initial state, the power-on reset signal RST and the trigger signal Vsel are both at low level, the sixth control unit 116 communicates the third control unit 113 with the fourth control unit 114, and the third control unit 113 is controlled by the fourth control unit 114; after the first power supply VDD1 is powered up to reach the power-on threshold voltage, the power-on reset signal RST is turned from the low level to the high level, and the trigger signal Vsel is at the low level, the sixth control unit 116 disconnects the third control unit 113 from the fourth control unit 114, the third control unit 113 is not controlled by the fourth control unit 114, and the third control unit 113 may be turned on by the fifth control unit 115. After the power-on reset signal RST is turned from the high level to the low level and the trigger signal Vsel is turned to the high level, the sixth control unit 116 disconnects the third control unit 113 from the fourth control unit 114, and the third control unit 113 is not controlled by the fourth control unit 114.

Considering both the first power supply VDD1 and the second power supply VDD2, in some embodiments, the power-on reset signal RST is power-domain-converted, and the power-on reset signal RST is converted to the larger one of the first power supply VDD1 and the second power supply VDD2. The power switching trigger circuit 110 operates in the larger one of the first power supply VDD1 and the second power supply VDD2.

In consideration of the driving capability of the power-on reset signal RST, in some embodiments, the power-on reset signal RST is processed by 2N non-logic units, and the power-on reset signal RST is processed by 2N non-logic units, so that the driving capability of the power-on reset signal RST can be provided.

Considering the driving capability of the trigger signal Vsel of the output node Q1, in some embodiments, the trigger signal Vsel output by the output node Q1 is processed and then output.

An example of an embodiment of the present application is described below in conjunction with fig. 6 and 7.

Fig. 6 shows a circuit diagram of a power supply switching trigger circuit provided in the embodiment of the present application, as shown in fig. 6, a power-on reset signal RST of a first power supply VDD1 is converted into a VMAX voltage domain, which is called a power-on reset signal rst_m, and is the larger one of the first power supply VDD1 and a second power supply VDD2. The power-on reset signal RST_M is processed by two NOT gates connected in series, the output node of the first NOT gate is STB, and the output node of the second NOT gate is STA. The signal output by STA is logically equivalent to the power-on reset signal rst_m.

As shown in fig. 6, the power supply switching trigger circuit 600 includes: node L1; a first control unit 601 connected to the node L1 for initializing the trigger signal Vsel to a low level; a second control unit 602 connected to the node L1, for making the trigger signal Vsel low when the power-on reset signal rst_m of the first power supply VDD1 is high; a third control unit 603 connected to the node L1 for making the trigger signal Vsel high when the power-on reset signal rst_m is low; the fourth control unit 604 is connected to the third control unit 603, and is configured to close the third control unit 603 when the trigger signal Vsel and the delayed power-on reset signal rst_m are both at low levels; the fifth control unit 605 is connected to the first control unit 601 and the third control unit 603, and is configured to turn off the first control unit 601 and turn on the third control unit 603 when the delayed power-on reset signal rst_m is at a high level. The high level of the power-on reset signal rst_m indicates a release state, and the low level of the power-on reset signal rst_m indicates a reset state.

In fig. 6, a control unit implemented by a MOS transistor is taken as an example for illustration, and it should be understood that the control unit in the embodiment of the present application is not limited to implementation by a MOS transistor.

As shown in fig. 6, the first control unit 601 includes a MOS transistor M8 and a capacitor C3. The MOS tube M8 is connected between the node L1 and the reference end GND, and the capacitor C3 couples the VMAX to the control end of the MOS tube M8; the MOS transistor M8 is turned on when the voltage of the control terminal is high. When the MOS transistor M8 is turned on, the voltage of the node L1 is pulled down to the voltage of the reference terminal GND, and the node L1 outputs the trigger signal Vsel to be at a low level.

As shown in fig. 6, the second control unit 602 includes: the MOS transistor M11 is connected between the reference end GND and the node L1, and the MOS transistor M11 is turned on when the power-on reset signal RST_M is at a high level and turned off when the power-on reset signal RST_M is at a low level.

As shown in fig. 6, the third control unit 603 includes: MOS tube M9 and MOS tube M10 are connected in series between node L1 and VMAX. The MOS transistor M9 is turned on when the power-on reset signal rst_m is low, and turned off when the power-on reset signal rst_m is high. The control end of the MOS transistor M10 is connected to the fourth control unit 604 and the fifth control unit 605.

As shown in fig. 6, the fourth control unit 604 includes: MOS pipe M4 and MOS pipe M3 are connected in series between VMAX and the control end of MOS pipe M10. The MOS transistor M4 is turned on when the trigger signal Vsel is at a low level, and turned off when the trigger signal Vsel is at a high level. The MOS transistor M3 is turned on when the delayed power-on reset signal RST_M is at a low level, and turned off when the delayed power-on reset signal RST_M is at a high level.

As shown in fig. 6, the fifth control unit 605 includes: MOS tube M1 connects between reference end GND and the control end of MOS tube M10. The MOS transistor M1 is turned on when the delayed power-on reset signal RST_M is at a high level, and turned off when the delayed power-on reset signal RST_M is at a low level. The MOS transistor M10 is turned on when the voltage of the control terminal is low.

Optionally, a sixth control unit 606 is also included, including: an exclusive-or logic XOR for exclusive-or-operating the power-on reset signal rst_m and the trigger signal Vsel; the MOS transistor M5 is connected between the fourth control unit 604 and the control end of the MOS transistor M10. The MOS transistor M5 is turned off when the exclusive or logic XOR outputs a high level to disconnect the fourth control unit 604 from the third control unit 603. MOS transistor M5 is turned on when the exclusive-or logic XOR outputs a low level.

Optionally, as shown in fig. 6, the fifth control unit 605 further includes: MOS pipe M6 connects between the control end of MOS pipe M10 and the control end of MOS pipe M8 and the first end of MOS pipe M1, and wherein, the second end of MOS pipe M1 is connected with reference end GND. The fifth control unit 605 further includes: MOS pipe M2 connects between MOS pipe M1's first end and MOS pipe M3's second end. The MOS transistor M2 is turned on when the power-on reset signal rst_m is at a high level, and turned off when the power-on reset signal rst_m is at a low level.

As shown in fig. 6, the power supply switching trigger circuit 600 further includes: a delay unit 607. The delay unit 607 includes a circuit R2 and a capacitor C2. The output node ST1 of the delay unit 607 is connected to the control end of the MOS transistor M1 and the control end of the MOS transistor M3, and the control ends of the MOS transistor M1 and the MOS transistor M3 receive the delayed power-on reset signal rst_m.

Optionally, as shown in fig. 6, the power switching trigger circuit 600 further includes: resistor R1 and capacitor C1, resistor R1 and capacitor C1 filter VMAX. The node L1 is also connected with a MOS tube M12, a MOS tube M13, a MOS tube M14 and a MOS tube M15, the MOS tube M12 and the MOS tube M13 form a first inverter, the MOS tube M14 and the MOS tube M15 form a second inverter, the first inverter and the second inverter are connected in series to form a buffer, the buffer is used for further processing the trigger signal Vsel and then outputting the trigger signal Vsel, and the quality of the trigger signal Vsel is improved.

The operation of the power switching trigger circuit 600 is described below with reference to fig. 6 and 7.

When VDD2 is powered up first and VDD1 is powered up later, VMAX is powered up before rst_m signal is released and STA node is low. The L2 node is coupled to a high level through a capacitor C3, so that the MOS transistor M8 is turned on, L1 is pulled down to a low level, the Vsel output is low level, and the MOS transistors M3 and M4 are turned on. In addition, STA and L1 output STY signal to low level through exclusive-or logic XOR, so that MOS transistor M5 is turned on, and MOS transistors M3, M4, M5, M8 and exclusive-or logic XOR form a positive feedback path.

When VDD1 is powered up to a power-up threshold voltage, the rising edge of rst_m comes, the STA signal jumps from low level to high level, the MOS transistors M1, M2, M6, M11 are turned on, the MOS transistors M3 and M9 are turned off, the L2 node and the L1 node are pulled down to low level, and Vsel is kept at low level. The STY signal jumps from low level to high level, the MOS tube M5 is disconnected, and the positive feedback loop is disconnected.

When VDD1 is powered down to below the power-down threshold, the rst_m signal jumps from high level to low level, the MOS transistors M1, M2, M6 and M11 are turned off, the MOS transistor M9 is turned on, the L1 node is pulled up to high level, and the output Vsel jumps from low level to high level. The STY signal is kept at a high level, the MOS transistor M5 is disconnected, and the positive feedback loop is kept in a disconnected state.

The voltage at the control end (gate end) of the MOS transistor M9 is STA, and the voltage at the control end (gate end) of the MOS transistor M3 is ST1, so that the positive feedback path is kept in an off state when the rst_m falling edge is triggered, otherwise, the node voltage of the L2 may be pulled up to a high level when the L1 node is not yet established to a high level, resulting in false triggering. Specifically, when the STA signal falls, the MOS transistor M9 is turned on, and a certain time is required for the L1 to establish a high level, so that a burr that the high level jumps to a low level may occur before the L1 is not completely established, resulting in the opening of the MOS transistor M5. If the gate terminal of the MOS transistor M3 is voltage-connected to the STA signal, the L2 node may be pulled up to a high level before the L1 node is not completely established, which causes the MOS transistor M10 to be disconnected, and the channel of the MOS transistor M8 may not be pulled up to a high level, resulting in a trigger failure. Therefore, the gate end of the MOS tube M3 is controlled by the signal ST1 after the STA is delayed, so that the L1 can be completely established to a high level, the MOS tube M4 is turned off, and the positive feedback loop is disconnected.

The MOS transistor M7 is used for weak pull-down, so that L2 node floating (floating) is avoided after the falling edge is triggered. If L2 is in a floating state, it is easily disturbed by power supply fluctuation.

The embodiment of the application also provides a chip, which comprises the circuit. Chips are also known as integrated circuits (Integrated Circuit, ICs). The Chip may be, but is not limited to, a SOC (System on Chip) Chip, a SIP (System in package ) Chip. The chip outputs a trigger signal Vsel to be low level before the first power supply VDD1 is electrified for the first time and does not reach the electrified threshold voltage; after reaching the power-on threshold voltage, the output trigger signal Vsel is kept at a low level; if the first power supply VDD1 is powered down, the output trigger signal Vsel becomes high level, and the switching of the power supply from the first power supply VDD1 to the second power supply VDD2 is triggered, so that the fast switching to the second power supply VDD2 when the first power supply VDD1 is powered down can be realized.

The embodiment of the application also provides electronic equipment, which comprises an equipment main body and the chip arranged in the equipment theme. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutritional scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a quick charger, an on-board charger, an adapter, a display, a USB (Universal Serial Bus ) docking station, a stylus, a real wireless headset, an automotive center control screen, an automobile, an intelligent wearable device, a mobile terminal, an intelligent home device. The intelligent wearing equipment comprises, but is not limited to, an intelligent watch, an intelligent bracelet and a cervical vertebra massage instrument. Mobile terminals include, but are not limited to, smartphones, notebook computers, tablet computers, POS (point of sales terminal, point of sale terminal) machines. The intelligent household equipment comprises, but is not limited to, an intelligent socket, an intelligent electric cooker, an intelligent sweeper and an intelligent lamp. The electronic device outputs a trigger signal Vsel to be low level before the first power supply VDD1 is powered on for the first time and does not reach a power-on threshold voltage; after reaching the power-on threshold voltage, the output trigger signal Vsel is kept at a low level; if the first power supply VDD1 is powered down, the output trigger signal Vsel becomes high level, and the switching of the power supply from the first power supply VDD1 to the second power supply VDD2 is triggered, so that the fast switching to the second power supply VDD2 when the first power supply VDD1 is powered down can be realized.

The foregoing description is not intended to limit the preferred embodiments of the present application, but is not intended to limit the scope of the present application, and any such modifications, equivalents and adaptations of the embodiments described above in accordance with the principles of the present application should and are intended to be within the scope of the present application, as long as they do not depart from the scope of the present application.

Claims

1. A power switching trigger circuit, comprising:

the output node is used for outputting a trigger signal, wherein when the trigger signal is in a high level, the trigger signal triggers the switching of the power supply from the first power supply to the second power supply;

the first control unit is connected with the output node and is used for enabling the trigger signal to be in a low level initially;

the second control unit is connected with the output node and is used for enabling the trigger signal to be low level when the power-on reset signal of the first power supply is high level;

the third control unit is connected with the output node and is used for enabling the trigger signal to be in a high level when the power-on reset signal is in a low level;

the delay unit is used for delaying the power-on reset signal;

the fourth control unit is connected with the third control unit and is used for closing the third control unit when the trigger signal and the power-on reset signal are both in low level;

the fifth control unit is connected with the first control unit and the third control unit and is used for closing the first control unit and opening the third control unit when the delayed power-on reset signal is at a high level;

wherein, the power-on reset signal is high level to represent a release state, and the power-on reset signal is low level to represent a reset state.

2. The circuit of claim 1, wherein,

the fourth control unit is configured to close the third control unit when the trigger signal and the delayed power-on reset signal are both at low levels.

3. The circuit of claim 1, wherein the circuit further comprises:

and a sixth control unit configured to disconnect the third control unit from the fourth control unit when either one of the power-on reset signal and the trigger signal is at a high level and the other is at a low level.

4. The circuit of claim 1, wherein the second control unit comprises:

the first switch is connected between the reference end and the output node, is turned on when the power-on reset signal is in a high level, and is turned off when the power-on reset signal is in a low level.

5. The circuit of claim 1, wherein the third control unit comprises:

the second switch and the third switch are connected in series between the output node and a third power supply, wherein the third power supply is the larger one of the first power supply and the second power supply;

the second switch is turned on when the power-on reset signal is in a low level, and turned off when the power-on reset signal is in a high level; and the control end of the third switch is connected with the fourth control unit and the fifth control unit.

6. The circuit of claim 5, wherein the fourth control unit comprises:

the fourth switch and the fifth switch are connected in series between the third power supply and the control end of the third switch;

the fourth switch is turned on when the trigger signal is in a low level, and turned off when the trigger signal is in a high level; the fifth switch is turned on when the delayed power-on reset signal is at a low level, and turned off when the delayed power-on reset signal is at a high level.

7. The circuit of claim 6, wherein the fifth control unit comprises:

the sixth switch is connected between the reference end and the control end of the third switch;

the sixth switch is turned on when the delayed power-on reset signal is at a high level, and turned off when the delayed power-on reset signal is at a low level; the third switch is turned on when the voltage of the control terminal thereof is at a low level.

8. The circuit of claim 7, wherein the circuit further comprises:

exclusive-or logic configured to exclusive-or the power-on reset signal and the trigger signal;

a seventh switch connected between the fourth control unit and the control terminal of the third switch, the seventh switch being turned off when the exclusive or logic outputs a high level to disconnect the fourth control unit from the third control unit; the seventh switch is turned on when the exclusive or logic outputs a low level.

9. The circuit of claim 7, wherein the first control unit comprises:

an eighth switch connected between the output node and the reference terminal;

a coupling unit, configured to couple the third power supply to a control terminal of the eighth switch; the eighth switch is turned on when the voltage of the control end of the eighth switch is high level;

wherein the sixth switch is further connected between the reference terminal and the control terminal of the eighth switch.

10. The circuit of claim 9, wherein the fifth control unit further comprises:

and a ninth switch connected between the control end of the third switch and the control end of the eighth switch and the first end of the sixth switch, wherein the second end of the sixth switch is connected with the reference end.

11. The circuit of claim 10, wherein a first terminal of the fourth switch is connected to the third power supply, and a second terminal of the fourth switch is connected to a first terminal of the fifth switch;

wherein, the fifth control unit further includes: a tenth switch connected between a first end of the sixth switch and a second end of the fifth switch; the tenth switch is turned on when the power-on reset signal is at a high level, and turned off when the power-on reset signal is at a low level.

12. The circuit of claim 9, wherein the circuit further comprises:

an eleventh switch, a first end of which is connected with the reference end, and a second end of which is connected with the control end of the third switch and the control end of the eighth switch;

wherein the eleventh switch is turned on when the trigger signal is at a high level and turned off when the trigger signal is at a low level.

13. A power switching circuit, comprising:

the circuit of any one of the preceding claims 1 to 12;

and the switching circuit is used for switching the power supply from the first power supply to the second power supply when the trigger signal is at a high level.

14. A chip comprising a circuit as claimed in any one of claims 1 to 13.

15. An electronic device comprising a device body and a chip as claimed in claim 14 provided on the device body.