CN219372993U

CN219372993U - Memory cell structure

Info

Publication number: CN219372993U
Application number: CN202223235936.1U
Authority: CN
Inventors: 毕津顺
Original assignee: Tianjin Binhai New Area Microelectronics Research Institute
Current assignee: Tianjin Binhai New Area Microelectronics Research Institute
Priority date: 2022-11-24
Filing date: 2022-11-24
Publication date: 2023-07-18
Anticipated expiration: 2032-11-24

Abstract

The utility model provides a memory cell structure, which comprises a transistor M1, a transistor M2, a transistor M3, a write bit line WBL, a write word line WWL, a read word line RWL and a read bit line RBL, wherein the drain electrode of the transistor M1 is connected with the write bit line WBL, the grid electrode is connected with the write word line WWL, and the source electrode is connected with the grid electrode of the transistor M2; the source electrode of the transistor M2 is grounded, and the drain electrode of the transistor M2 is connected with the source electrode of the transistor M3; a gate of the transistor M3 is connected with the read word line RWL, and a drain is connected with the read bit line RBL; the write bit line WBL, the write word line WWL, the read word line RWL, and the read bit line RBL are connected to first, second, third, and fourth power supply modules, respectively. The memory cell is simple in structure, and the write path is separated from the read path, so that the interference between writing and reading is reduced.

Description

Memory cell structure

Technical Field

The utility model relates to the technical field of semiconductor devices, in particular to a memory cell structure.

Background

Memory chips, also known as semiconductor memories, are the primary components of electronic digital devices for storage, and are very important in the whole integrated circuit market. The memory can store program codes to process various data, and can also store generated intermediate data and final results in the process of processing the stored data, so that the memory is a basic universal integrated circuit product with the widest application range at present.

According to the functions of the Memory chip, the data reading mode and the data storage principle, the Memory chip can be roughly divided into a Volatile Memory (Volatile Memory) and a Non-Volatile Memory (Non-Volatile Memory), wherein the Non-Volatile Memory can still keep stored contents after an external power supply is cut off, and the Memory chip has slower reading speed but larger storage capacity and mainly comprises an EEPROM (electrically erasable programmable read-only Memory), a Flash Memory chip, a PROM (programmable read-only Memory), an EPROM (erasable programmable read-only Memory) and the like. Volatile memory is classified into DRAM and SRAM. As the main technology of the current nonvolatile memory, flash memories mainly have two main types: floating gate (Floating gate) based and defect (Trap) based.

The storage medium constituting the memory is mainly a semiconductor device and a magnetic material. The smallest unit of memory in a memory is a bistable semiconductor circuit or a CMOS transistor or memory cell of magnetic material that can store a binary code. A memory unit is composed of a plurality of memory cells, and then a memory is composed of a plurality of memory cells. A memory contains a plurality of memory cells, each of which can hold a byte, and each of which has a number, i.e., address, generally represented in hexadecimal. The sum of all memory locations in a memory that can hold data is referred to as its storage capacity, and assuming that the address code of a memory is composed of 20-bit binary numbers (i.e., 5-bit hexadecimal numbers), 220, i.e., 1M memory location addresses, each memory location holds one byte, the storage capacity of the memory is 1KB.

The existing memory transistors are many and complicated, have complex structures, and have serious path interference between reading and writing, and aiming at the problem, it is necessary to provide a memory cell structure which has a simple structure and has no path interference between reading and writing.

Disclosure of Invention

Technical problem to be solved

In view of the foregoing drawbacks of the prior art, the present utility model provides a memory cell structure that is simple and has a write path that is separate from a read path, reducing the interference between writing and reading.

Technical proposal

In order to achieve the above purpose, the utility model is realized by the following technical scheme:

the utility model relates to a memory cell structure, which comprises a transistor M1, a transistor M2, a transistor M3, a write bit line WBL, a write word line WWL, a read word line RWL and a read bit line RBL, wherein the drain electrode of the transistor M1 is connected with the write bit line WBL, the grid electrode is connected with the write word line WWL, and the source electrode is connected with the grid electrode of the transistor M2; the source electrode of the transistor M2 is grounded, and the drain electrode of the transistor M2 is connected with the source electrode of the transistor M3; a gate of the transistor M3 is connected with the read word line RWL, and a drain is connected with the read bit line RBL; the write bit line WBL, the write word line WWL, the read word line RWL, and the read bit line RBL are connected to first, second, third, and fourth power supply modules, respectively.

Further, the first, second, third and fourth power supply modules are respectively for maintaining a high level, a low level and a low level when the memory cell structure performs a write operation.

Further, the first, second, third and fourth power supply modules are respectively for maintaining a low level, a high level and a high level when the memory cell structure performs a read operation.

Further, a sensitive node SN is disposed between the transistor M1 and the transistor M2, and the sensitive node SN is connected to a capacitor.

Further, the transistor M1, the transistor M2 and the transistor M3 are implemented by a planar process or manufactured by a three-dimensional process.

Further, the transistor M1, the transistor M2 and the transistor M3 adopt a single gate, a double gate, a triple gate or a surrounding gate structure.

Further, the transistor M1, the transistor M2, and the transistor M3 employ a silicon-based process or a non-silicon process.

Advantageous effects

The memory cell structure designed by the utility model adopts a 3-transistor structure, is far smaller than a 6-transistor or 4-transistor memory cell structure in an SRAM, has simple structure, and has higher integration level and memory capacity under the same chip area; in addition, the write path and the read path of the memory cell structure are separated, so that the interference between writing and reading is reduced, the memory cell data can be read at any moment, including the writing moment, and the memory data is not damaged.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present utility model and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a schematic diagram of a memory cell according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of a memory cell structure according to an embodiment of the present utility model;

FIG. 3 is a schematic diagram illustrating a memory cell structure reading operation according to an embodiment of the present utility model.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present utility model more clear, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. It will be apparent that the described embodiments are some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not intended to be limiting with respect to time sequence, number, or importance, but are not to be construed as indicating or implying a relative importance or implicitly indicating the number of features indicated, but merely for distinguishing one feature from another in the present disclosure. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly specified otherwise. Likewise, the appearances of the phrase "a" or "an" in this document are not meant to be limiting, but rather describing features that have not been apparent from the foregoing. Likewise, unless a particular quantity of a noun is to be construed as encompassing both the singular and the plural, both the singular and the plural may be included in this disclosure. Likewise, modifiers similar to "about" and "approximately" appearing before a number in this document generally include the number, and their specific meaning should be understood in conjunction with the context.

Referring to fig. 1, a memory cell structure includes a transistor M1, a transistor M2, a transistor M3, a write bit line WBL, a write word line WWL, a read word line RWL, and a read bit line RBL, wherein a drain electrode of the transistor M1 is connected to the write bit line WBL, a gate electrode is connected to the write word line WWL, and a source electrode is connected to the gate electrode of the transistor M2; the source electrode of the transistor M2 is grounded, and the drain electrode of the transistor M2 is connected with the source electrode of the transistor M3; a gate of the transistor M3 is connected with the read word line RWL, and a drain is connected with the read bit line RBL; the write bit line WBL, the write word line WWL, the read word line RWL, and the read bit line RBL are connected to first, second, third, and fourth power supply modules, respectively. The memory cell structure adopts a 3-transistor structure, is far smaller than a 6-transistor or 4-transistor memory cell structure in the SRAM, has a simple structure, and has higher integration level and memory capacity under the same chip area; and, through the first, second, third and fourth power modules, connect said write bit line WBL, said write word line WWL, said read word line RWL and said read bit line RBL separately, have realized writing the route and read the route to separate, have reduced the interference between reading and writing, can be at any moment, including writing the moment, read the memory cell data, and do not destroy the memory data.

In this embodiment, referring to fig. 2 and 3, the first, second, third and fourth power modules are respectively used to maintain high level, low level and low level when the memory cell structure performs a write operation. And, the first, second, third and fourth power supply modules are respectively for maintaining a low level, a high level and a high level when the memory cell structure performs a read operation.

In this embodiment, a sensing node SN is disposed between the transistor M1 and the transistor M2, and the sensing node SN is connected to a capacitor. The transistor M1, the transistor M2 and the transistor M3 are implemented by a planar process or manufactured by a three-dimensional process. The transistor M1, the transistor M2 and the transistor M3 adopt a single gate, double gate, triple gate or surrounding gate structure. The transistor M1, the transistor M2 and the transistor M3 adopt a silicon-based process or a non-silicon process.

Specifically, if the transistors M1, M2, M3 are silicon-based, the charge stored in the sensitive node SN will dissipate in a shorter time due to background leakage, and therefore refresh compensation is required; if the transistors M1, M2, M3 employ IGZO thin film transistor technology with ultra-low leakage, the charge stored by the SN node of the sensing node can be stored for a long time within hundreds of seconds to thousands of seconds, and refresh compensation is almost negligible. The memory cell structure of the utility model belongs to a volatile memory, namely, data is not saved after power failure.

Referring to fig. 2, the write operation is: the first, second, third and fourth power supply modules respectively maintain a high level, a low level and a low level; writing data 0 to the memory cell structure when the write word line WWL is high and the write bit line WBL is low; writing data 1 into a memory cell when the write word line WWL is high and the write bit line WBL is high; thereby completing the operation of write 0 or write 1 to the memory cell structure.

Referring to fig. 3, the read operation is: the first, second, third and fourth power supply modules respectively maintain a low level, a high level and a high level; when the read word line RWL is at a high level and the read bit line RBL is at a high level, if the stored data is 0, the transistor M2 is turned off, the transistor M3 is turned on, and no direct current path exists between the high-potential read bit line RBL and the ground of the source electrode of the transistor M2, so that the read bit line RBL is in a low-current state, and the read data is 0; when the read word line RWL is at a high level and the read bit line RBL is at a high level, if the stored data is 1, the sensing node SN is at a high level, the transistor M2 is turned on, the transistor M3 is turned on, and a dc path is formed from the high-potential read bit line RBL to the ground of the source of the transistor M2, so that the read bit line RBL exhibits a high-current state, and the read data is 1. Thus, the operation of reading 0 or reading 1 of the memory cell structure is completed.

The utility model has the advantages that the structure of 3 transistors is adopted, which is far smaller than the structure of 6 transistors or 4 transistors memory cells in SRAM, the structure is simple, and the utility model has higher integration level and memory capacity under the same chip area; in addition, the write path and the read path of the memory cell structure are separated, so that the interference between writing and reading is reduced, the memory cell data can be read at any moment, including the writing moment, and the memory data is not damaged.

The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; these modifications or substitutions do not depart from the essence of the corresponding technical solutions from the protection scope of the technical solutions of the embodiments of the present utility model.

Claims

1. The memory cell structure is characterized by comprising a transistor M1, a transistor M2, a transistor M3, a write bit line WBL, a write word line WWL, a read word line RWL and a read bit line RBL, wherein the drain electrode of the transistor M1 is connected with the write bit line WBL, the gate electrode is connected with the write word line WWL, and the source electrode is connected with the gate electrode of the transistor M2; the source electrode of the transistor M2 is grounded, and the drain electrode of the transistor M2 is connected with the source electrode of the transistor M3; a gate of the transistor M3 is connected with the read word line RWL, and a drain is connected with the read bit line RBL; the write bit line WBL, the write word line WWL, the read word line RWL and the read bit line RBL are respectively connected with a first power module, a second power module, a third power module and a fourth power module; the first, second, third and fourth power supply modules are respectively used for maintaining a high level, a low level and a low level when the memory cell structure performs a write operation; the first, second, third and fourth power supply modules are respectively for maintaining a low level, a high level and a high level when the memory cell structure performs a read operation.

2. The memory cell structure of claim 1, wherein a sensing node SN is provided between the transistor M1 and the transistor M2, the sensing node SN being connected to a capacitor.

3. The memory cell structure of claim 1, wherein the transistor M1, the transistor M2, and the transistor M3 are implemented using a planar process or are manufactured using a three-dimensional process.

4. The memory cell structure of claim 1, wherein the transistor M1, the transistor M2, and the transistor M3 are in a single gate, double gate, triple gate, or surrounding gate structure.

5. The memory cell structure of claim 1, wherein the transistor M1, the transistor M2, and the transistor M3 are formed using a silicon-based process or a non-silicon process.