CN219350206U - Power semiconductor module - Google Patents

Power semiconductor module Download PDF

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Publication number
CN219350206U
CN219350206U CN202320211373.8U CN202320211373U CN219350206U CN 219350206 U CN219350206 U CN 219350206U CN 202320211373 U CN202320211373 U CN 202320211373U CN 219350206 U CN219350206 U CN 219350206U
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substrate
area
power semiconductor
package
semiconductor module
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CN202320211373.8U
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Chinese (zh)
Inventor
M·马利基
F·菲舍尔
H·拜尔
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Hitachi Energy Co ltd
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Hitachi Energy Switzerland AG
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    • H—ELECTRICITY
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

According to one embodiment, a power semiconductor module (100) has a package (2) and a plurality of semiconductor chips (1) based on a wide bandgap semiconductor material. The semiconductor chip is embedded in the package. The package is laterally delimited by an outer contour (21) when viewed in top view. The area surrounded by the outer contour forms the base area of the package. The semiconductor chips are arranged such that when the semiconductor chips are projected onto the base region, the projected semiconductor chips together occupy at least 7% of the area of the base region.

Description

Power semiconductor module
Technical Field
A power semiconductor module is presented.
Background
Power semiconductor modules are used on a large scale in power conversion equipment (such as industrial motor drives, embedded motor drives, uninterruptible power supplies, AC-DC power supplies) and in welding power supplies. Power semiconductor modules are also widely used in inverters for renewable energy sources (such as wind turbines, solar cells, tidal power plants) and in electric vehicles.
One object to be solved is to provide an improved power semiconductor module, in particular a power semiconductor module having a high power density or a high current carrying capacity, respectively.
Disclosure of Invention
Embodiments of the present disclosure relate to an improved power semiconductor module.
According to one embodiment, a power semiconductor module has a package and a plurality of semiconductor chips based on a wide bandgap semiconductor material. The semiconductor chip is embedded in the package. The package is laterally delimited by an outer contour when viewed in top view. The area surrounded by the outer contour forms the base area of the package. The semiconductor chips are arranged such that when the semiconductor chips are projected onto the base region, the projected semiconductor chips have an area that together occupies at least 6% of the area of the base region.
The development of power semiconductor modules has focused mainly on high power density, current carrying capacity and power conversion efficiency. Other important goals are lifetime, cost and quality. To achieve high power density in a power module, a wide bandgap device such as a silicon carbide MOSFET may be used instead of a conventional silicon IGBT. The use of wide band gap devices is associated with higher electrical, electromagnetic and thermal requirements.
In particular, fast switching is a key feature of wide bandgap devices. Fast switching results in overvoltage due to leakage inductance of the commutation loop, resulting in higher switching losses and EMI emissions.
Silicon carbide chips with edge lengths exceeding 6mm are generally less likely to be produced due to, for example, the high price of silicon carbide wafers and the relatively high yield loss in wafer processing. This is necessary to keep the percent yield loss in production low. Thus, the available chip size and thus the size of the effective active area and thus the current carrying capacity of a single silicon carbide chip is smaller compared to silicon IGBT chips where the edge length may be up to 20 mm. Therefore, a plurality of silicon carbide chips must be arranged electrically in parallel in order to achieve a sufficiently high current carrying capacity of the power semiconductor module.
The use of multiple chips (e.g., electrically connected in parallel) results in a larger area requirement than a power module having only a few chips with a relatively large total active area. In particular, in standard power semiconductor modules, in which the chips are embedded in a dielectric gel on a substrate, there must be relatively large space between the chips to ensure adequate electrical isolation and/or positional tolerances. However, the larger power semiconductor module size in turn leads to higher leakage inductances in the commutation loop and higher conduction and switching losses. Furthermore, larger module sizes result in higher weight and higher material costs for the package, but also in disadvantages when integrating the power semiconductor module into the customer application, which makes the customer acceptance lower.
The proposed design is characterized by a lower leakage inductance and a higher current density, or in other words, a higher power density due to the higher density of the semiconductor chips, which is one of the most important reference criteria in the market.
A wide bandgap semiconductor is generally understood to be a semiconductor whose bandgap is at the high end of the semiconductor range, for example at least 3eV or at least 3.2eV. For example, the semiconductor material is silicon carbide (SiC) (such as 4H-SiC), gallium nitride (GaN), indium gallium nitride (InGaN), or diamond (C).
The power semiconductor module may be designed to handle currents greater than 10A. The power semiconductor module may be a low voltage module designed for voltages below 1kV or a medium voltage module designed for voltages between 1kV and 30 kV. For example, the power semiconductor module has a rated voltage between 650V and 1300V (inclusive).
The semiconductor chip is embedded in a package which is at least partially surrounded by the package in a form-fitting manner. For example, the semiconductor chip is laterally surrounded by at least the package. The package may also cover the top side of the semiconductor chip.
The semiconductor chips are arranged without overlapping, for example, with respect to a cross-sectional plane (hereinafter also referred to as an arrangement plane) passing through the package. That is, when all semiconductor chips are projected onto this arrangement plane, no two projected semiconductor chips overlap each other, or all projected semiconductor chips are spaced apart from each other in pairs. The semiconductor chips may be arranged such that the arrangement plane passes through all semiconductor chips. The main extension plane of the semiconductor chip may be parallel to the arrangement plane.
The package may have a top side and a bottom side. For example, the top side and/or the bottom side may be flat surfaces and/or may be parallel to each other. The top side of the package may form part or all of the top side of the power semiconductor module. For example, the bottom side of the package is in contact with the substrate.
The thickness of the package (i.e. the extent of the package between the top side and the bottom side) is for example smaller than the smallest lateral extent of the top side and/or the bottom side. The main extension plane of the package is for example parallel to the top side and/or the bottom side of the package. The top side and/or the bottom side and/or the main extension plane of the package may be parallel to the arrangement plane.
The above-mentioned top views are in particular views with a viewing direction perpendicular to the arrangement plane and/or to the main extension plane of the package and/or onto the top or bottom side of the package. Thus, the indication "lateral" here and hereinafter refers to a direction parallel to the arrangement plane and/or to the main extension plane of the package and/or to the top side and/or bottom side of the package, for example. Such a direction is also referred to as a lateral direction, for example.
As seen in top view, the outer contour of the package defines the base area of the package, also referred to as the footprint (footprint) of the package. The base region is for example a surface parallel to the plane of the arrangement and/or to the main extension plane of the package and/or to the top side and/or bottom side of the package. In particular, the base region is a continuous surface without discontinuities. The outer contour may be a polygonal contour, such as a rectangle or square. The base region may coincide with the top and/or bottom side of the package.
When the semiconductor chips are projected onto the base region, the projected semiconductor chips collectively cover at least 6% or at least 6.5% or at least 7% or at least 7.3% or at least 7.8% of the area of the base region. That is, the projected semiconductor chip covers the portion of the base region. For example, the area of a single projected semiconductor chip is given by the area of the projected semiconductor body of the semiconductor chip.
Projection onto a surface or side is understood here and hereinafter as perpendicular projection.
According to a further embodiment, the semiconductor chip is an electronic switch, such as a transistor or a thyristor. The semiconductor chip may also include one or more diodes.
According to a further embodiment, the semiconductor chip is or comprises an IGBT or MOSFET or JFET or HEMT or thyristor.
According to a further embodiment, the semiconductor chip is based on SiC or GaN or diamond.
According to a further embodiment, at least some of the semiconductor chips are electrically connected in parallel.
According to a further embodiment, the semiconductor chips are connected in a half-bridge arrangement.
For example, a half-bridge is a circuit comprising two switching structures connected in series between two DC connection points (a positive connection point and a negative connection point) and providing an AC connection point or an output connection point between them. The DC connection point and the AC connection point may be electrically connected to terminals of the power semiconductor module. For example, each switching structure may have one or more semiconductor chips electrically connected in parallel. Each switching structure may have one or more electronic switches and optionally one or more diodes.
The power semiconductor module may be used for an electrical converter (e.g. a rectifier) that converts an AC voltage to a DC voltage, which is then supplied to, for example, a DC link or a battery, for example, a battery of an electric vehicle. It is also possible that the converter is an inverter that generates an AC voltage from a DC voltage, which AC voltage is supplied to an electric motor, for example an electric motor of an electric vehicle. Such inverters are used, for example, in solar energy systems. The power semiconductor module may be used in a motor vehicle, such as an electric car, a motorcycle, a bus, an off-road work vehicle, a truck, or a charging station or a frequency converter that converts the frequency of an incoming current/voltage to another frequency.
According to a further embodiment, the semiconductor chips are connected in at least two groups. For example, the first group is available for loads in the high side. For example, it forms at least part of the high side of the half bridge. For example, the second group is available for loads in the low side. For example, it forms at least a part of the lower side of the half bridge. In particular, the group includes a plurality of semiconductor chips. For example, within a group, the semiconductor chips or at least some of the semiconductor chips are connected in parallel. The first and second groups may each form one of the aforementioned switch structures. In particular, the first and second groups may be connected in series.
For example, the first group is divided into two rows. In each row of the first group, a plurality of semiconductor chips are arranged one after another and connected in parallel in the respective rows. Here, "one after the other" refers to the longitudinal direction. For example, the rows are parallel to each other.
For example, the second group is also divided into two rows. In each row of the second group, a plurality of semiconductor chips are arranged one after another and connected in parallel in the respective rows. For example, the rows are parallel to each other.
The two rows of the second group may be arranged in a lateral direction between the two rows of the first group, perpendicular to the respective extension direction (longitudinal direction) of the rows. The longitudinal direction and the transverse direction are in particular directions parallel to the plane of arrangement and/or to the main extension plane and/or to the upper side and/or the lower side of the package. The semiconductor chips may be arranged mirror-symmetrically with respect to a mirror plane or mirror axis extending between the two rows of the second group.
This particular arrangement may allow for a reduced number of electrical connections and improved current balancing and switching uniformity. By means of simulation, it can be shown that the above-described arrangement of semiconductor chips in two groups (each group having at least two rows in a coaxial arrangement) results in a lower leakage inductance and enables a higher power density.
According to a further embodiment, the package is a transfer molded body or an injection molded body. In particular, the package may be produced by a transfer molding process, such as a film assisted transfer molding or injection molding process.
According to further embodiments, the package comprises or consists of one or more of the following materials: thermoset materials, thermoplastic materials.
The package may comprise or consist of a polymeric material, for example one or more of the following group: filled or unfilled molding material, filled or unfilled thermoplastic material, filled or unfilled thermoset material, filled or unfilled laminate, fiber reinforced polymer laminate with filler particles.
The thermoset material may comprise or consist of a resin, such as an epoxy resin. The thermoplastic may comprise or consist of one or more materials selected from the group consisting of: polyetherimide (PEI), polyethersulfone (PES), polyphenylene sulfide (PPS) or Polyamideimide (PAI), or other thermoplastic materials such as polybutylene terephthalate (PBT) or polyethylene terephthalate (PET). Thermoplastic materials melt during molding or lamination due to the action of pressure and heat and solidify reversibly after cooling and release of pressure.
For example, the encapsulation member includes at least one base material selected from the group consisting of phenolic resin, brominated resin, amino resin, epoxy phenolic resin. Phenolic resins are low molecular weight polymers derived from phenol and formaldehyde (e.g., formaldehyde to phenol ratio less than 1).
Due to the higher dielectric strength of the above-mentioned materials, a smaller distance between the semiconductor chips, in particular between semiconductor chips at different potentials, can be achieved. In addition, high reliability at high temperature and high humidity, for example, higher reliability than encapsulation using gel, can be achieved.
According to a further embodiment, the active areas of the semiconductor chip together occupy at least 4% or at least 4.3% or at least 4.7% or at least 5.2% of the area of the base area when projected onto the base area.
The active region of a semiconductor chip refers to a region where semiconductor activity occurs during operation, such as a region where charge carriers flow through or a switching process occurs. The active region is defined, for example, by a region of the semiconductor body of the semiconductor chip which is electrically contacted, for example, by a topside contact. The area or volume of the active region may be at least 0.5 or at least 2/3 of the area or volume of the semiconductor chip for each semiconductor chip.
According to a further embodiment, a power semiconductor module includes a substrate. The substrate is for example a carrier part of a power semiconductor module. For example, the substrate is self-supporting, i.e. mechanically stable in nature.
According to a further embodiment, the semiconductor chip is mounted on the top side of the substrate and electrically connected on the top side. For example, the semiconductor die is soldered, sintered or glued to the top side. For example, the top view mentioned above is a top view to the top side of the substrate. For example, the base area of the package is larger in area than the total area of the substrate and/or larger than the top side of the substrate. For example, a portion of the bottom side of the package rests on, mimics and contacts the top side of the substrate in a form-fitting manner. Another portion of the bottom side of the package may be flush with the bottom side of the substrate.
According to a further embodiment, the semiconductor chips together cover at least 7.0% or at least 7.5% or at least 8% or at least 9% or at least 9.5% of the top side of the substrate. The remainder or most of the remainder of the top side may be covered by the package.
According to a further embodiment, the active areas of the semiconductor chips together cover at least 4.5% or at least 5% or at least 5.5% or at least 5.9% or at least 6.4% of the area of the top side of the substrate. This means that this ratio is covered when the active area is projected onto the top side.
According to a further embodiment, the semiconductor chip is arranged and electrically connected on the metallization at the top side of the substrate. The metallization may be a layer at the top side of the substrate. For example, the metallization includes all metal regions at the top side of the substrate. For example, the metallization at the top side is patterned and includes a plurality of regions that are isolated or spaced apart from each other. That is, the top side of the substrate may be formed partially of metal, and partially of insulating material.
According to a further embodiment, the semiconductor chips together cover at least 7.5% or at least 8% or at least 9.5% or at least 10% of the area of the metallization.
According to a further embodiment, the active regions of the semiconductor chip or the corresponding projections together cover at least 5.0% or at least 5.5% or at least 6.2% or at least 6.7% of the area of the metallization, respectively.
For example, the metallization comprises at least five main metallization strips, each extending in the longitudinal direction. That is, the lengths of the primary metallized tape measured parallel to the longitudinal direction are each greater than the width measured perpendicular to the longitudinal direction in the transverse direction.
The primary metallization strips may be arranged one after the other and spaced apart from each other in the transverse direction and overlap each other along the longitudinal direction. That is, in projection into the longitudinal direction, the main metallization strips partially or completely overlap each other. For example, two external main metallization strips with respect to the lateral direction are associated with a first group of semiconductor chips. On each of the two outer main metallization strips, a row of semiconductor chips of the first group, for example exactly one row, may be mounted and electrically connected.
For example, the two main metallization strips closest to the outer main metallization strip are assigned to the second group of semiconductor chips. On each of these main metallization strips, a row of semiconductor chips of the second group, for example exactly one row, may be arranged and electrically connected. The innermost main metallization strip may be devoid of semiconductor chips. For example, the innermost primary metallization strip is used for contacting the semiconductor chips of the second group and for connecting the load terminals.
This coaxial arrangement of the primary metallization strips may reduce leakage inductance. But leakage inductance is also reduced by the high integration density and associated short current path. In particular, the main metallization strips may be arranged mirror-symmetrically with respect to the aforementioned mirror plane or mirror axis. This symmetry ensures a more uniform switching behaviour.
According to a further embodiment, the substrate is a multilayer substrate. Between the metallization on the top side and the metallization on the opposite bottom side of the substrate, the substrate may comprise an electrically insulating layer, for example made of ceramic or filled plastic material. The ceramic may be AlN, si3N4, siO2. The metallizations of the top and bottom sides may be or comprise copper, aluminum or a corresponding alloy.
For example, the metallization at the bottom side is electrically isolated from the metallization at the top side. For example, during expected operation of the power semiconductor module, the metallization at the bottom side does not carry any current. For example, the metallization at the bottom side may be dedicated to cooling and/or heat dissipation of the substrate or the semiconductor chip, respectively. For example, the metallization at the bottom side is for connection to a heat sink, such as a substrate.
According to further embodiments, the substrate is an AMB substrate or a DBC substrate or a DBA substrate or an IMS substrate. AMB stands for "active metal brazing (Active Metal Brazing)", DBC and DBA stands for "direct copper plating" and "direct aluminum plating". IMS stands for "insulating metal substrate", wherein a filled plastic layer is used in particular as insulating layer.
According to a further embodiment, the power semiconductor module comprises a substrate. For example, the substrate is formed from or includes one or more of a metal or a composite material. For example, the substrate comprises or consists of one or more of the following: copper, aluminum silicon carbide (AlSiC), magnesium silicon carbide (MgSiC). For example, during expected operation of the power semiconductor module, no current flows through the substrate. For example, the substrate is electrically isolated from the semiconductor chip, e.g., by the substrate. The substrate may be a heat sink. For example, the substrate is provided only for cooling and/or mounting the power semiconductor module.
According to a further embodiment, the substrate is mounted on a base plate. In particular, the bottom side of the substrate faces the substrate. For example, the substrate is soldered or glued or sintered to the substrate.
According to a further embodiment, the substrate is at least partially formed on the bottom side of the power semiconductor module. The bottom side of the power semiconductor module may also be formed at least partially from the substrate if the substrate is not present.
According to at least one embodiment, the power semiconductor module comprises at least 16 or at least 20 semiconductor chips. For example, the power semiconductor module comprises at most 100 or at most 50 semiconductor chips.
According to a further embodiment, the semiconductor chips each have an area of at most 6x 6mm 2 or at most 5x 5mm 2. Alternatively or additionally, the semiconductor chips each have an area of at least 2x2 mm2. The surface areas here are the areas of the semiconductor chips in plan view or the projected areas of the semiconductor chips. For example, the semiconductor chip has a maximum edge length of 6mm or 5 mm.
According to a further embodiment, the base region of the package has an area of at most 80x80 mm2, for example an area of 69x74 mm2. The top side of the substrate has an area of, for example, at most 75x75 mm2, for example, 75x75 mm2. The substrate (e.g. the bottom side of the substrate) has, for example, substantially the same area as the base area, e.g. has a variation of at most 5% or at most 10% or at most 20% or at most 25%.
Drawings
Hereinafter, the power semiconductor module will be explained in more detail by way of exemplary embodiments with reference to the accompanying drawings. The accompanying drawings are included to provide a further understanding. In the drawings, elements having the same structure and/or the same function may be provided with the same reference numerals. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. Insofar as elements or components in different drawings are functionally corresponding, their description will not be repeated in the respective drawings below. For purposes of clarity, not all illustrated elements may be provided with corresponding reference numerals.
In the drawings:
fig. 1 to 3 show embodiments of a power semiconductor module in different views.
Detailed Description
In fig. 1, an exemplary embodiment of a power semiconductor module 100 is shown in a side cross-sectional view. The power semiconductor module 100 comprises a substrate 4, which is made of copper or aluminum or a composite material such as aluminum silicon carbide (AlSiC) or magnesium silicon carbide (MgSiC), for example. The substrate 4 serves as a heat sink for the power semiconductor module 100. The substrate 3 is mounted on the upper surface 40 of the base plate 4, for example glued or soldered or sintered. In the present case, the substrate 3 has three layers 31, 32, 33. Layer 33 forms the bottom side of the substrate and faces the top side 40 of the substrate 4, in particular being thermally connected thereto. For example, the layer 33 is metallic, for example made of copper or aluminum or a corresponding alloy. Layer 31 is a metallization of substrate 3 and is arranged on top side 30 of substrate 3. An electrically insulating layer 32, for example made of porcelain or filled plastic material, is provided between the metallization 31 and the layer 33. The metallization 31 and the layer 33 may be electrically insulated from each other. The substrate is, for example, an AMB substrate, a DBC substrate, a DBA substrate, or an IMS substrate.
A plurality of semiconductor chips 1 are mounted on the top side 30 of the substrate 30. The semiconductor chip 1 is electrically and mechanically connected to the metallization 31. The semiconductor chip 1 is a semiconductor chip based on a semiconductor material having a wide band gap or a large band gap, respectively. For example, the bandgap of the semiconductor material is greater than or equal to 3.5eV. The semiconductor material may be SiC or GaN or C. For example, the semiconductor chip is a MOSFET or an IGBT or a JFET or a HEMT or a thyristor.
Furthermore, the package 2 is applied to the top side 30 of the substrate 3. The semiconductor chips 1 are embedded in the encapsulation 2 such that they are positively enclosed by the encapsulation 2 both laterally and on their respective top sides. The package 2 may be a thermoplastic or a thermosetting plastic. For example, the package 2 is an epoxy resin. In order to surround the semiconductor chip 1 with the package 2, for example, an injection molding process or a transfer molding process is employed.
The electrical connectors 5 extend laterally from the package 2. The electrical connection 5 is led to the top side 30 of the substrate 3, where it is electrically connected to the metallization 31. The power semiconductor module 100 may be electrically connected to, for example, a power supply via the connection 5.
Fig. 2 shows a top view of the power semiconductor module 100 of fig. 1, i.e. onto the top side 101 of the power semiconductor module 100. The horizontal dashed line represents the cross-sectional plane S for the illustration of fig. 1.
The top side 101 of the power semiconductor module 100 is formed by the package 2. The opposite bottom side 102 of the power semiconductor module 100 is formed by the substrate 4. In the top view of fig. 2, a main portion of the substrate 3 and the base plate 4 is covered by the package 2 (the substrate 3 is indicated by a broken line). Fig. 3 shows the same top view except that the package 2 is omitted to clarify the arrangement of the semiconductor chips 1 on the substrate 3.
In the top view shown in fig. 2, the package 2 is laterally surrounded and delimited by an outer contour 21. The outer contour 21 encloses a flat area, which is referred to as the base area or footprint of the package 2, respectively. For example, the base area is at most 80x80 mm2. Also shown is a projection of the semiconductor chip 1 onto the base region (dashed box). The area of each semiconductor chip 1 is at most 6×6mm2, and is arranged such that each pair of semiconductor chips 1 does not overlap. For example, the projected semiconductor chips 1 in total occupy at least 7.8% of the base area. For example, the active area of the semiconductor chip 1 in total occupies at least 5.2% of the base area.
Referring to fig. 3, the semiconductor chip 1 here covers, for example, at least 9.5% of the area of the top side 30 of the substrate 3. The top side 30 of the substrate 3 is for example at most 75x75 mm2. The active areas of the semiconductor chips 1 together cover, for example, at least 6.4% of the area of the top side 30. In addition, the semiconductor chips 1 together cover, for example, at least 10% of the area of the metallization 31 and/or the active areas of the semiconductor chips 1 together cover at least 6.7% of the area of the metallization 31.
As shown in fig. 2 and 3, the semiconductor chips 1 are arranged in four rows on four main metallization strips. The main metallized tape extends in a longitudinal direction and is arranged one after the other in a transverse direction perpendicular to the longitudinal direction. The fifth main metallization strip is centrally disposed. This is not covered by the semiconductor chip 1.
The outer two rows of semiconductor chips 1 are associated with a first group 10. This first group 10 is, for example, the high side of a half bridge. In each of the outer rows, the respective semiconductor chips 1 are connected in parallel.
Two inner rows of semiconductor chips 1 are assigned to a second group 11, which forms the underside of the half-bridge. Within each of the inner rows, the individual semiconductor chips 1 are also connected in parallel. The fifth main metallization stripe is used to contact the second group 11.
The main metallization strips assigned to the two outer rows of the semiconductor chip 1 can be contacted from the outside via the respective first terminals 5. The first terminals 5 protrude laterally from the package 2. For example, the first terminal 5 forms a DC (+) terminal. The main metallization strips associated with the inner rows of the semiconductor chip 1 are electrically conductively connected to each other via a third terminal 7. As with the first terminals 5, third terminals 7 are led out laterally from the package 2 for external electrical contact. The third terminal 7 forms, for example, an AC terminal or an output terminal of the power semiconductor module 100.
The inner main metallization is electrically connected to the second terminal 6. The second terminals 6 are led out laterally from the package 2 on the same side as the first terminals 5, and can be electrically contacted from the outside. The second terminal 6 forms, for example, the DC (-) terminal of the power semiconductor module 100.
Fig. 3 also shows bonding wires 9 via which the front contacts of the semiconductor chip 1 are conductively connected to adjacent main metallization strips or gate metallization strips. The gate metallization is electrically connected to gate terminals 8 which are also led out laterally from the package 2.
As shown in fig. 3, the stray inductance of the power semiconductor module 100 is reduced by the mirror-symmetrical, coaxial arrangement of the semiconductor chip 1 and the main metallization strip. However, due to the high integration density and associated short current paths, stray inductances and thus conduction and switching losses are also reduced. In addition, symmetry ensures a significantly more uniform switching behavior.
The embodiments shown in fig. 1 to 3 represent exemplary embodiments of a power semiconductor module. Thus, it does not represent a complete list of all embodiments of the power semiconductor module. The actual power semiconductor modules may differ from the exemplary embodiments shown, for example in terms of arrangement and components.
List of reference numerals
1. Semiconductor chip
2. Package piece
3. Substrate and method for manufacturing the same
4. Substrate board
5. First terminal
6. Second terminal
7. Third terminal
8. Gate terminal
9. Bonding wire
10. First group of
11. Second group of
21. External profile
30 topside of substrate 3
31. Metallization part
32. Electrically insulating layer
33. Layer(s)
40. Topside of substrate
100. Power semiconductor module
101. Top side of power semiconductor module
102. Bottom side of power semiconductor module
S cross-section plane

Claims (15)

1. A power semiconductor module (100), characterized by comprising:
a package (2),
-a plurality of semiconductor chips (1) based on a wide bandgap semiconductor material, wherein
-the semiconductor chip (1) is embedded in the package (2), wherein
Viewed in top plan, the package (2) being laterally delimited by an outer contour (21), the area enclosed by the outer contour (21) forming a base area of the package (2),
-the semiconductor chip (1) is arranged such that when the semiconductor chip (1) is projected onto the base region, the projected semiconductor chips together occupy at least 6% of the area of the base region.
2. The power semiconductor module (100) according to claim 1, characterized in that:
-the semiconductor chip (1) is a MOSFET or an IGBT or a JFET or a HEMT or a thyristor.
3. The power semiconductor module (100) according to claim 1 or 2, characterized in that:
-the semiconductor chip (1) is based on SiC or GaN or diamond.
4. The power semiconductor module (100) according to claim 1 or 2, characterized in that:
-at least some of the semiconductor chips (1) are electrically connected in parallel.
5. The power semiconductor module (100) according to claim 1 or 2, characterized in that:
-the semiconductor chips (1) are connected in a half-bridge configuration.
6. The power semiconductor module (100) of claim 5, wherein:
-the semiconductor chips (1) are divided into at least two groups (10, 11) such that:
the first group (10) is available for loads in the high side,
-the second group (11) is available for loads in the low side.
7. The power semiconductor module (100) according to any one of claims 1 to 2 and 6, characterized in that:
-the package (2) is a transfer or injection molded body.
8. The power semiconductor module (100) according to any one of claims 1 to 2 and 6, characterized in that:
-the package (2) comprises or consists of a thermosetting or thermoplastic material.
9. The power semiconductor module (100) according to any one of claims 1 to 2 and 6, characterized in that:
-the active area of the semiconductor chip (1) when projected onto the base area together occupies at least 4% of the area of the base area.
10. The power semiconductor module (100) according to any one of claims 1 to 2 and 6, further comprising:
-a substrate (3), wherein
-the semiconductor chip (1) is mounted on a top side (30) of the substrate (3) and is electrically connected on the top side (30).
11. The power semiconductor module (100) of claim 10, wherein:
-the semiconductor chips (1) together cover at least 7.0% of the area of the top side (30) of the substrate (3), and/or
-the active areas of the semiconductor chips (1) together cover at least 4.5% of the area of the top side (30).
12. The power semiconductor module (100) of claim 10, wherein:
the semiconductor chip (1) is arranged and electrically connected on a metallization (31) at a top side (30) of the substrate (3) and on the metallization,
-the semiconductor chip (1) together covers at least 7.5% of the area of the metallization (31), and/or
-the active areas of the semiconductor chips (1) together cover at least 5% of the area of the metallization (31).
13. The power semiconductor module (100) of claim 10, wherein:
-the substrate (3) is an AMB substrate, a DBC substrate, a DBA substrate or an IMS substrate.
14. The power semiconductor module (100) of claim 10, further comprising:
-a substrate (4), wherein
-the substrate (3) is mounted on the base plate (4).
15. The power semiconductor module (100) of claim 10, wherein:
the power semiconductor module (100) comprises at least 16 semiconductor chips (1),
the semiconductor chips (1) each have an area of at most 6x 6mm 2,
the base region of the package (2) has an area of at most 80x80 mm2,
-the top side (30) of the substrate (3) has an area of at most 75x75 mm2.
CN202320211373.8U 2022-02-14 2023-02-14 Power semiconductor module Active CN219350206U (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE202022100811.6U DE202022100811U1 (en) 2022-02-14 2022-02-14 power semiconductor module
DE202022100811.6 2022-02-14

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Publication Number Publication Date
CN219350206U true CN219350206U (en) 2023-07-14

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JP3242736U (en) 2023-07-07

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