CN219321343U - Bonding pad structure of chip, chip and electronic equipment - Google Patents
Bonding pad structure of chip, chip and electronic equipment Download PDFInfo
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- CN219321343U CN219321343U CN202320260296.5U CN202320260296U CN219321343U CN 219321343 U CN219321343 U CN 219321343U CN 202320260296 U CN202320260296 U CN 202320260296U CN 219321343 U CN219321343 U CN 219321343U
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Abstract
The utility model discloses a bonding pad structure of a chip, the chip and electronic equipment, wherein the bonding pad structure of the chip comprises: the chip comprises an edge bonding pad, a central bonding pad and a solder mask layer, wherein the edge bonding pad, the central bonding pad and the solder mask layer are manufactured on a chip body in a protruding mode, the edge bonding pad is arranged in an edge area of the chip body, and the central bonding pad is arranged in a middle area of the chip body; the center bonding pad comprises a plurality of separated sub bonding pads, the solder mask is arranged between any two sub bonding pads, and the protrusion height of the solder mask is larger than that of all the sub bonding pads; the solder mask layer can be contacted with an external circuit board at first, a certain support is provided, and the chip is prevented from inclining in the welding process, so that the distances between each sub-bonding pad and the edge bonding pad on the chip and the external circuit board are equal, the tin quantity of each edge bonding pad is consistent, and the false welding or short circuit fault in the welding process is avoided.
Description
Technical Field
The present utility model relates to the field of chip bonding pad manufacturing technologies, and in particular, to a bonding pad structure of a chip, and an electronic device.
Background
At present, the grounding pad of a printed circuit board (Printed circuit boards, PCB) of a grid array packaged chip is designed into a whole large pad, and the periphery of the grounding pad is designed into small pads, for example, a MALD-37030B chip; the PCB with the bonding pad structure has the advantages that during reflow soldering, the shapes of the surrounding small bonding pads are irregular, solder paste is in a molten state in the reflow process, the stress of the solder paste on the middle grounding bonding pad and the solder paste on the surrounding small bonding pads is unbalanced, the chip body is inclined, the balance of the tin amounts of the middle grounding large bonding pad and the surrounding small bonding pads cannot be ensured in the soldering process, the tin amounts of the surrounding small bonding pads are inconsistent, and the chip adopting the bonding pad structure generates a virtual soldering or short circuit fault in the soldering process.
Disclosure of Invention
Based on this, it is necessary to provide a bonding pad structure of a chip, a chip and an electronic device to solve the problem that the existing bonding pad structure of the chip generates a cold joint or a short circuit fault in the process of bonding.
In a first aspect, an embodiment of the present utility model provides a pad structure of a chip, including:
the chip comprises an edge bonding pad, a central bonding pad and a solder mask layer, wherein the edge bonding pad, the central bonding pad and the solder mask layer are manufactured on a chip body in a protruding mode, the edge bonding pad is arranged in an edge area of the chip body, and the central bonding pad is arranged in a middle area of the chip body;
the center pad comprises a plurality of separated sub-pads, the solder mask layer is arranged between any two sub-pads, and the protrusion height of the solder mask layer is larger than that of all the sub-pads.
The scheme has the following beneficial effects:
according to the bonding pad structure of the chip, the solder mask layer with a certain height is arranged between the sub bonding pads, and when the chip with the bonding pad structure is welded with an external circuit board, the solder mask layer can be contacted with the external circuit board first to provide a certain support to prevent the chip from tilting in the welding process, so that the distances between the sub bonding pads and the edge bonding pads on the chip and the external circuit board are equal, the tin amount of the edge bonding pads is consistent, and the false welding or short circuit fault in the welding process is avoided.
Optionally, the sub-pads are rectangular, and a preset distance is formed between the sub-pads.
Optionally, each of the sub-pads is disposed in parallel along the first direction and the second direction on one side of the chip body.
Optionally, the pitch of each sub-pad in the first direction is a first pitch, and the pitch of each sub-pad in the second direction is a second pitch.
Optionally, the solder mask layer includes a plurality of solder mask branches, and each solder mask branch is respectively disposed in a space of each sub-pad along the first direction.
Optionally, the solder mask layer includes a plurality of solder mask branches, and each solder mask branch is respectively disposed in a space of each sub-pad along the second direction.
Optionally, the solder mask layer includes a plurality of solder mask branches, and each solder mask branch is respectively disposed in a space between each sub-pad along the first direction and the second direction.
Optionally, the edge pad is circular, and an area of the edge pad is smaller than an area of the sub-pad.
In a second aspect, an embodiment of the present utility model provides a chip, including a chip body, where a pad structure of the chip in the first aspect is disposed on the chip body.
The scheme has the following beneficial effects:
according to the chip, the solder mask layer protruding the chip body to a certain height is arranged between the sub-bonding pads of the chip, the solder mask layer with the bonding pad structure can be firstly contacted with an external circuit board when being welded with the external circuit board, a certain support is provided, the chip is prevented from tilting in the welding process, the distances between the sub-bonding pads and the edge bonding pads on the chip and the external circuit board are ensured to be equal, the tin amount of the edge bonding pads is consistent, and the occurrence of false welding or short circuit fault in the welding process of the chip is avoided.
In a third aspect, an embodiment of the present utility model provides an electronic device, including a printed circuit board, on which the chip according to the second aspect is soldered.
The scheme has the following beneficial effects:
according to the electronic equipment, the solder mask layer with the certain height of the convex chip body is arranged between the sub-bonding pads of the chip on the printed circuit board, and the solder mask layer with the structure of the bonding pad can be firstly contacted with the external circuit board when being welded with the external circuit board, so that certain support is provided for preventing the chip from inclining in the welding process, the distances between the sub-bonding pads and the edge bonding pads on the chip and the external circuit board are ensured to be equal, the tin amount of the edge bonding pads is consistent, the occurrence of false welding or short circuit fault in the welding process of the chip is avoided, and the working stability of the electronic equipment is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments of the present utility model will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a bonding pad structure of a first chip according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of a solder joint with an external circuit board according to an embodiment of the present utility model;
FIG. 3 is a schematic diagram of a bonding pad structure of a second chip according to an embodiment of the present utility model;
FIG. 4 is a schematic diagram of a pad structure of a third chip according to an embodiment of the present utility model;
the symbols are as follows:
100. a chip body; 101. a center pad; 1011. a sub-pad; 102. an edge pad; 103. a solder mask layer; 200. a printed circuit board; 201, edge pad solder paste; 202. and (5) sub-pad solder paste.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects solved by the utility model more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments.
It is to be understood that the embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be further understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
It will be further understood that the terms "upper," "lower," "left," "right," "front," "rear," "bottom," "middle," "top," and the like may be used herein to describe various elements and that the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings merely to facilitate describing the utility model and simplifying the description, and do not indicate or imply that the devices or elements being referred to must have a particular orientation, be constructed and operate in a particular orientation, and that these elements should not be limited by these terms.
These terms are only used to distinguish one element from another element. For example, a first element could be termed a "upper" element, and, similarly, a second element could be termed a "upper" element, depending on the relative orientation of the elements, without departing from the scope of the present disclosure.
It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In one embodiment, there is provided a pad structure of a chip as shown in fig. 1, the pad structure of the chip including: an edge pad 102, a center pad 101 and a solder resist layer 103, which are raised on the chip body 100, wherein the edge pad 102 is disposed in an edge region of the chip body 100, and the center pad 101 is disposed in a middle region of the chip body 100; the center pad 101 includes a plurality of separated sub-pads 1011, the solder resist layer 103 is disposed between any two sub-pads 1011, and the height of the bump chip body 100 of the solder resist layer 103 is greater than the height of the bump chip body 100 of the sub-pad 1011, so that the solder resist layer 103 provides support during chip bonding, so that the chip body 100 remains balanced and the amount of tin attached to the edge pads is uniform.
The solder mask layer with a certain height is arranged between the sub-pads, and the solder mask layer with the structure can be contacted with an external circuit board at first when being welded with the external circuit board, so that the chip is prevented from tilting in the welding process, the distances between the sub-pads and the edge pads on the chip and the external circuit board are equal, the tin amount of the edge pads is consistent, and the false welding or short circuit fault is avoided in the welding process.
Further, as shown in fig. 1, the sub-pads 1011 have a rectangular shape, and the sub-pads 1011 are spaced apart from each other by a predetermined distance, thereby providing a certain arrangement space for the solder resist layer 103.
As an example, the sub-pads 1011 may also be circular, or any shape tailored to the actual design requirements, to achieve the same function as the rectangular sub-pads 1011.
Further, as shown in fig. 1, each sub-pad 1011 is disposed in parallel along the first direction and the second direction on one side of the chip body 100, that is, each sub-pad 1011 is disposed in parallel along the horizontal direction and is disposed in parallel along the vertical direction, so as to form a grid-shaped central pad 101, and the grid-shaped central pad 101 can provide a relatively uniform supporting force during welding, so that the amount of tin attached to the edge pad 102 is uniform, and a false welding or a short circuit fault is avoided during welding.
Further, as shown in fig. 1, the pitch of each sub-pad 1011 in the first direction is a first pitch, the pitch of each sub-pad 1011 in the second direction is a second pitch, that is, the pitch of each sub-pad 1011 in the horizontal direction is a first pitch, and the pitch in the vertical direction is a second pitch, where the first pitch and the second pitch may be equal or unequal, and the effect of providing the solder resist layer 103 may be achieved.
Further, as shown in fig. 1, the solder mask layer 103 includes a plurality of solder mask branches, each of the solder mask branches is disposed in a space along the first direction of each of the sub-pads 1011, that is, each of the solder mask branches is in a strip-shaped structure, and each of the strip-shaped solder mask branches is disposed in a space along the horizontal direction of each of the sub-pads 1011.
As shown in fig. 2, when the pad structure of the chip is soldered to the external printed circuit board 200, the solder mask layer 103 is first in contact with the external printed circuit board, so as to provide a certain support for the chip body 100, so that the chip body 100 is in a balanced state, the left edge pad 102 and the right edge pad 102 of the chip body 100 are in contact with the corresponding edge pad solder paste 201, the sub-pads 1011 are in contact with the sub-pad solder paste 202, and the thicknesses of the two solder paste solder pastes are the same, i.e. the amount of solder paste attached to each solder pad is uniform, so that the occurrence of a cold solder or a short circuit fault in the soldering process is avoided.
Further, as shown in fig. 3, the solder mask layer 103 includes a plurality of solder mask branches, each of the solder mask branches is disposed in a space along the second direction of each of the sub-pads 1011, that is, each of the solder mask branches is in a strip-shaped structure, and each of the strip-shaped solder mask branches is disposed in a space along the vertical direction of each of the sub-pads 1011; the arrangement mode of the solder mask can also play a role of balancing the chip.
Further, as shown in fig. 4, the solder mask layer 103 includes a plurality of solder mask branches, each of the solder mask branches is disposed in a space between each of the sub-pads 1011 along the first direction and the second direction, that is, each of the solder mask branches is in a strip-shaped structure, and each of the strip-shaped solder mask branches is disposed in a space between each of the sub-pads 1011 along the horizontal direction and the vertical direction; the arrangement mode of the solder mask layer can lead the chip to be more balanced during welding because the solder mask branches are respectively arranged in the horizontal direction and the vertical direction.
Further, as shown in fig. 1, each edge pad 102 is circular, the area of each edge pad is smaller than the area of the sub pad 1011, the sub pad 1011 is used as a ground pad, the larger area can pass a larger current, and the edge pad 102 is used as a signal pad of a chip to communicate with an external circuit.
The pad structure of the chip of this embodiment has the following characteristics:
(1) The strip-shaped solder resist branches in the horizontal direction are arranged between the sub-bonding pads, and the inclination is prevented when the chip is welded, so that the distances between the sub-bonding pads and the edge bonding pads on the chip and an external circuit board are equal, the tin quantity of the edge bonding pads is consistent, and the false bonding or short circuit fault is avoided in the welding process.
(2) The strip-shaped solder resist branches in the vertical direction are arranged between the sub-bonding pads, and the inclination is prevented when the chip is welded, so that the distances between the sub-bonding pads and the edge bonding pads on the chip and an external circuit board are equal, the tin quantity of the edge bonding pads is consistent, and the false bonding or short circuit fault is avoided in the welding process.
(3) The strip-shaped solder resist branches in the horizontal direction and the vertical direction are arranged between the sub-bonding pads, and when a chip is welded, the supporting force of the bottom of the chip is improved, and the inclination is prevented, so that the distances between the sub-bonding pads and the edge bonding pads on the chip and an external circuit board are equal, the tin quantity of the edge bonding pads is consistent, and the false welding or short circuit fault is avoided in the welding process.
In one embodiment, a chip is provided, the chip comprising: and the chip body is provided with the bonding pad structure of the chip in the embodiment.
The chip of this embodiment samples the pad structure in above-mentioned embodiment, sets up the solder mask of protruding chip body certain height between each sub-pad, and the chip of this pad structure can be at first with external circuit board contact when welding of external circuit board, provides certain support, prevents that this chip from taking place the slope at welded in-process to guarantee that each sub-pad on this chip and interval between edge pad and the external circuit board are equal, make the tin volume of each edge pad unanimous, avoid the chip welding in-process to produce rosin joint or short circuit trouble.
In one embodiment, an electronic device is provided that includes a printed circuit board on which the chips of the above embodiments are soldered, and other electronic components that make up the electronic device circuit, such as resistors, capacitors, switching tubes, and the like.
The solder mask layer with a certain height is arranged between each sub-bonding pad of the chip on the printed circuit board, the chip with the bonding pad structure can be firstly contacted with the external circuit board when being welded with the external circuit board, a certain support is provided, the chip is prevented from inclining in the welding process, the distances between each sub-bonding pad on the chip and the edge bonding pad and the external circuit board are equal, the tin amount of each edge bonding pad is consistent, the occurrence of false welding or short circuit faults in the welding process of the chip is avoided, and the working stability of the electronic equipment is improved.
The above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model, and are intended to be included in the scope of the present utility model.
Claims (10)
1. A bonding pad structure of a chip, comprising:
the chip comprises an edge bonding pad, a central bonding pad and a solder mask layer, wherein the edge bonding pad, the central bonding pad and the solder mask layer are manufactured on a chip body in a protruding mode, the edge bonding pad is arranged in an edge area of the chip body, and the central bonding pad is arranged in a middle area of the chip body;
the center pad comprises a plurality of separated sub-pads, the solder mask layer is arranged between any two sub-pads, and the protrusion height of the solder mask layer is larger than that of all the sub-pads.
2. The bonding pad structure of claim 1, wherein the sub-bonding pads are rectangular, and each of the sub-bonding pads is spaced apart from each other by a predetermined distance.
3. The pad structure of claim 2, wherein each of the sub-pads is disposed in parallel along both the first direction and the second direction at one side of the chip body.
4. A pad structure of a chip according to claim 3, wherein a pitch of each of the sub-pads in the first direction is a first pitch, and a pitch of each of the sub-pads in the second direction is a second pitch.
5. The die pad structure of claim 4, wherein the solder mask layer comprises a plurality of solder mask branches, each of the solder mask branches being disposed within a space of each of the sub-pads along the first direction.
6. The die pad structure of claim 4, wherein the solder mask layer comprises a plurality of solder mask branches, each of the solder mask branches being disposed within a space of each of the sub-pads along the second direction.
7. The die pad structure of claim 4, wherein the solder mask layer comprises a plurality of solder mask branches, each of the solder mask branches being disposed within a respective one of the sub-pads along the first and second directions.
8. The die pad structure of claim 1, wherein the edge pads are circular, and wherein the area of the edge pads is smaller than the area of the sub-pads.
9. A chip comprising a chip body, wherein the chip body is provided with a pad structure of the chip according to any one of claims 1-8.
10. An electronic device comprising a printed circuit board having the chip of claim 9 soldered thereto.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320260296.5U CN219321343U (en) | 2023-02-09 | 2023-02-09 | Bonding pad structure of chip, chip and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320260296.5U CN219321343U (en) | 2023-02-09 | 2023-02-09 | Bonding pad structure of chip, chip and electronic equipment |
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| Publication Number | Publication Date |
|---|---|
| CN219321343U true CN219321343U (en) | 2023-07-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320260296.5U Active CN219321343U (en) | 2023-02-09 | 2023-02-09 | Bonding pad structure of chip, chip and electronic equipment |
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| CN (1) | CN219321343U (en) |
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- 2023-02-09 CN CN202320260296.5U patent/CN219321343U/en active Active
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