CN219303670U

CN219303670U - 4H-SiC-based super junction power MOSFET

Info

Publication number: CN219303670U
Application number: CN202221986452.8U
Authority: CN
Inventors: 谢速
Original assignee: Jiefang Semiconductor Shanghai Co ltd
Current assignee: Jiefang Semiconductor Shanghai Co ltd
Priority date: 2022-07-29
Filing date: 2022-07-29
Publication date: 2023-07-04
Anticipated expiration: 2032-07-29

Abstract

The utility model discloses a 4H-SiC-based super-junction power MOSFET, the cell structure of which comprises a drain electrode, a source electrode and a grid electrode, wherein a pressure-resistant layer is arranged above a buffer barrier layer, a semiconductor body region is arranged on the upper side of the pressure-resistant layer, the semiconductor source region is positioned in the semiconductor body region, the grid electrode covers part of the pressure-resistant layer, part of the semiconductor body region and part of the surface of the semiconductor source region, a sedimentation tank is further formed in the semiconductor body region, the source electrode is arranged in the sedimentation tank, the source electrode is further connected with the semiconductor source region through a conductor, a semiconductor substrate layer covers the lower surface of the buffer barrier layer, and the lower surface of the semiconductor substrate layer covers the conductor to form the drain electrode; the buffer barrier layer is composed of at least one semiconductor buffer region and at least one semiconductor minority carrier block region buried in the semiconductor buffer region. The current path is effectively shortened, the cell size of the device is reduced, and the UIS avalanche capacity of the MOSFET device is improved; the specific on-resistance of the device is reduced, and the chip area is reduced.

Description

4H-SiC-based super junction power MOSFET

Technical Field

The utility model relates to the technical field of semiconductor power devices, in particular to a 4H-SiC-based super-junction power MOSFET.

Background

Superjunction power MOSFETs (i.e., metal-oxide-semiconductor field effect transistors) are used to improve Breakdown Voltage (BV) and specific on-resistance (R) _ON,SP ) The relation between breakdown voltage and specific on-resistance is rewritten from 2.5 times of the traditional power MOSFET to 1.3 times, so that the on-resistance of the power MOSFET is greatly reduced, the area of a chip is reduced, and the power MOSFET is widely applied to medium-low power supply equipment.

The 4H-SiC-based super-junction power MOSFET is a minority carrier conduction device, and only one carrier participates in conduction when the MOSFET is turned on, for example, in an n-type channel device, only electrons participate in conduction, and the electrons flow in an n column of a super-junction structure; meanwhile, the p column in the super junction structure does not contribute to the current conducting capacity of the device, and the p column has the function of providing ionized acceptor impurities during forward blocking so as to absorb power lines emitted by ionized donor impurities in the n column, thereby improving the breakdown voltage of the device. Therefore, how to utilize p-pillar conduction to further improve the device on-current capability, reduce the specific on-resistance of the device, and reduce the chip area becomes a new research direction.

Disclosure of Invention

Aiming at the defects of the prior art, the utility model aims to provide a 4H-SiC-based super-junction power MOSFET which can reduce the specific on-resistance of a device, reduce the cell size area of the device and improve the UIS avalanche resistance of the device.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

the cell structure of the 4H-SiC-based super-junction power MOSFET comprises a drain electrode, a source electrode, a grid electrode, a pressure-resistant layer, a buffer barrier layer, a semiconductor body region, a semiconductor source region and a semiconductor substrate layer, wherein the pressure-resistant layer is arranged above the buffer barrier layer, the semiconductor body region is arranged on the upper side of the pressure-resistant layer, the semiconductor source region is positioned in the semiconductor body region, the grid electrode covers the surfaces of part of the pressure-resistant layer, part of the semiconductor body region and part of the semiconductor source region, a sedimentation tank is further formed in the semiconductor body region, the source electrode is arranged in the sedimentation tank, the source electrode is connected with the semiconductor source region through a conductor, the semiconductor substrate layer covers the lower surface of the buffer barrier layer, and the lower surface of the semiconductor substrate layer covers the conductor to form the drain electrode;

the buffer barrier layer is composed of at least one semiconductor buffer region and at least one semiconductor minority carrier block region buried in the semiconductor buffer region.

Further, the voltage-resistant layer is composed of a first semiconductor drift region having a certain conductivity type and a second semiconductor drift region having a conductivity type opposite to that of the first semiconductor drift region, which are in contact with each other, wherein an upper surface of the first semiconductor drift region is in contact with the gate electrode and a part of a lower surface of the semiconductor body region, and an upper surface of the second semiconductor drift region is in contact with the semiconductor body region.

Further, the first semiconductor drift region has a vertical height that is less than the second semiconductor drift region.

Further, the arrangement mode of the super junction structure formed by the first semiconductor drift region and the second semiconductor drift region includes, but is not limited to, any one of a bar shape, a hexagon shape, a rectangle shape or a circle shape.

Further, the left end of the semiconductor minority carrier block region is flush with the semiconductor buffer region and the first semiconductor drift region, and the other end of the semiconductor minority carrier block region extends into the lower portion of the second semiconductor drift region.

Further, the gate is composed of a gate insulating layer, a semiconductor polysilicon gate layer and a conducting layer, wherein the gate insulating layer covers part of the voltage-resistant layer, part of the semiconductor body region and part of the semiconductor source region, and the semiconductor polysilicon gate layer and the conducting layer cover the upper surface of the gate insulating layer in sequence.

The utility model has the remarkable effects that:

1. the semiconductor body is sunk, and the source electrode is arranged at the sunk position, so that a current path is effectively shortened, the cell size of the device is reduced, the area of the device is further reduced, and the UIS avalanche tolerance capacity of the MOSFET device is improved; meanwhile, the turn-off time can be effectively shortened, and the power consumption of the switch is reduced;

2. carriers of a first conductivity type and a second conductivity type are respectively caused to flow in the semiconductor first drift region and the semiconductor second drift region by a MOSFET gate structure and a bipolar junction transistor driven by the MOSFET, while carriers of the second conductivity type are blocked from entering the semiconductor first drift region by the semiconductor minority carrier blocking region buried in a semiconductor buffer region, so that the semiconductor minority carrier blocking region is directly in contact with the semiconductor buffer region and is not directly in contact with a voltage-resistant layer and a semiconductor substrate region, thereby avoiding formation of conductivity modulation in the voltage-resistant layer; the specific on-resistance of the device is reduced, and the chip area is reduced.

Drawings

Fig. 1 is a schematic structural view of the present utility model.

Detailed Description

The following describes the embodiments and working principles of the present utility model in further detail with reference to the drawings.

As shown in fig. 1, a 4H-SiC-based super-junction power MOSFET is formed by mutually splicing a plurality of repeated cell structures, wherein the cell structures include a drain electrode 10, a source electrode 20, a gate electrode 30, a voltage-resistant layer 40, a buffer barrier layer 50, a semiconductor body region 60, a semiconductor source region 70 and a semiconductor substrate layer 80, the voltage-resistant layer 40 is disposed above the buffer barrier layer 50, the semiconductor body region 60 is disposed on the upper side of the voltage-resistant layer 40, the semiconductor source region 70 is disposed in the semiconductor body region 60, the drain electrode 30 covers the surfaces of a part of the voltage-resistant layer 40, a part of the semiconductor body region 60 and a part of the semiconductor source region 70, a sedimentation tank is further formed in the semiconductor body region 60, the source electrode 20 is further connected with the semiconductor source region 70 through a conductor, the semiconductor substrate layer 80 covers the lower surface of the buffer barrier layer 50, and the drain electrode 10 is formed on the lower surface of the semiconductor substrate layer 80.

The gate 30 is composed of a gate insulating layer 31, a semiconductor polysilicon gate layer 32 and a conductive layer 33, wherein the gate insulating layer 31 covers a part of the voltage-resistant layer 40, a part of the semiconductor body region 60 and a part of the semiconductor source region 70, and the semiconductor polysilicon gate layer 32 and the conductive layer 33 cover the upper surface of the gate insulating layer 31 in sequence.

In this example, the voltage-resistant layer 40 is composed of a first semiconductor drift region 41 having a first conductivity type and a second semiconductor drift region 42 having a second conductivity type opposite to the conductivity type of the first semiconductor drift region 41, wherein the first conductivity type is N-type and the second conductivity type is P-type; the upper surface of the first semiconductor drift region 41 is in contact with the gate electrode 30 and a part of the lower surface of the semiconductor body region 60, and the upper surface of the second semiconductor drift region 42 is in contact with the semiconductor body region 60, and the height of the first semiconductor drift region 41 in the vertical direction is smaller than that of the second semiconductor drift region 42.

Optionally, the arrangement manner of the superjunction structure formed by the first semiconductor drift region 41 and the second semiconductor drift region 42 includes, but is not limited to, any one of a stripe shape, a hexagon shape, a rectangle shape, or a circle shape.

In this example, the buffer barrier layer 50 is formed by at least one semiconductor buffer region 51 and at least one semiconductor minority carrier block region 52 buried in the semiconductor buffer region 51, the left end of the semiconductor minority carrier block region 52 is flush with the semiconductor buffer region 51 and the first semiconductor drift region 41, and the other end of the semiconductor minority carrier block region 52 extends below the second semiconductor drift region 42.

The semiconductor minority carrier blocking region 52 buried in the semiconductor buffer region 51 makes the semiconductor minority carrier blocking region 52 directly contact with the semiconductor buffer region 51 but not directly contact with the voltage-resistant layer 40 and the semiconductor substrate region 80, thereby avoiding the formation of conductivity modulation in the voltage-resistant layer 40, further reducing the specific on-resistance of the device and reducing the chip area.

In this embodiment, the conductivity type of the semiconductor buffer region 51 is N-type, the conductivity type of the semiconductor minority carrier block region 52 is N-type, the conductivity type of the semiconductor body region 60 is P-type, the conductivity type of the semiconductor source region 70 is N-type, and the conductivity type of the semiconductor substrate layer 80 is P-type.

A portion of the source 20 and the gate 30, the first semiconductor drift region 41, the semiconductor minority carrier block region 52, the semiconductor substrate layer 80, and the drain 10 constitute a MOSFET of a conductivity type N-type such that carriers of a first conductivity type flow mainly in the MOSFET; a portion of the source 20 and the semiconductor body 60, the second semiconductor drift region 42, the semiconductor buffer region 51, a portion of the semiconductor substrate layer 80 and the drain 10 form a bipolar junction transistor-BJT of a P-type conductivity type such that carriers of a second conductivity type flow mainly in the BJT.

In this embodiment, the semiconductor body 60 is sunk, and the source 20 is disposed at the sunk position, so that the current path is effectively shortened, the cell size of the device is reduced, the device area is further reduced, the UIS avalanche resistance of the MOSFET device is improved, the turn-off time is also effectively shortened, and the switching power consumption is reduced.

The technical scheme provided by the utility model is described in detail. The principles and embodiments of the present utility model have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present utility model and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the utility model can be made without departing from the principles of the utility model and these modifications and adaptations are intended to be within the scope of the utility model as defined in the following claims.

Claims

1. The cell structure of the 4H-SiC-based super-junction power MOSFET comprises a drain electrode, a source electrode and a grid electrode, and is characterized in that: the semiconductor source region is arranged on the upper side of the pressure-resistant layer, the semiconductor source region is positioned in the semiconductor body region, the grid electrode covers part of the pressure-resistant layer, part of the semiconductor body region and part of the surface of the semiconductor source region, a sedimentation tank is further formed in the semiconductor body region, the source electrode is arranged in the sedimentation tank and is connected with the semiconductor source region through a conductor, the semiconductor substrate layer covers the lower surface of the buffer barrier layer, and the lower surface of the semiconductor substrate layer covers the conductor to form the drain electrode;

2. The 4H-SiC-based superjunction power MOSFET of claim 1, wherein: the voltage-resistant layer is composed of a first semiconductor drift region with a certain conductivity type and a second semiconductor drift region with a conductivity type opposite to that of the first semiconductor drift region, wherein the upper surface of the first semiconductor drift region is contacted with the lower surface of the grid electrode and part of the semiconductor body region, and the upper surface of the second semiconductor drift region is contacted with the semiconductor body region.

3. The 4H-SiC-based superjunction power MOSFET of claim 2, wherein: the arrangement mode of the super junction structure formed by the first semiconductor drift region and the second semiconductor drift region includes, but is not limited to, any one of bar, hexagon, rectangle or circle.

4. A 4H-SiC-based superjunction power MOSFET according to claim 3, characterised in that: the left end of the semiconductor minority carrier block region is flush with the semiconductor buffer region and the first semiconductor drift region, and the other end of the semiconductor minority carrier block region extends into the lower portion of the second semiconductor drift region.

5. The 4H-SiC-based superjunction power MOSFET of claim 1, wherein: the grid electrode is composed of a grid insulating layer, a semiconductor polysilicon gate layer and a conducting layer, wherein the grid insulating layer covers part of the voltage-resistant layer, part of the semiconductor body region and part of the semiconductor source region, and the semiconductor polysilicon gate layer and the conducting layer cover the upper surface of the grid insulating layer in sequence.