CN219267652U

CN219267652U - DDR2 micro-assembly

Info

Publication number: CN219267652U
Application number: CN202320318105.6U
Authority: CN
Inventors: 张�诚; 毛臻; 余国良; 周军
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2023-02-27
Filing date: 2023-02-27
Publication date: 2023-06-27
Anticipated expiration: 2033-02-27

Abstract

The utility model discloses a DDR2 micro-assembly, which belongs to the field of memories and comprises an intermediate solder ball, a plastic package body, a first DDR2 chip, a TSV bridge piece, a second DDR2 chip and a bottom solder ball; the first DDR2 chip fans out the bonding pads to two sides through a rewiring design, and the middle solder balls are positioned on the back surface of the first DDR2 chip; the TSV bridge pieces are arranged on two sides of a rewiring second DDR2 chip, and the second DDR2 chip is interconnected with the first DDR2 chip through the TSV bridge pieces; the plastic package body is used for wrapping the first DDR2 chip, the TSV bridge piece and the second DDR2 chip, the bottom implanting ball is located at the bottom of the injection molded structure. The wiring point position of the original DDR3 bare chip is changed based on the rewiring technology, so that the wiring point position is adapted to a required packaging structure, and stacking of the DDR2 bare chips after the rewiring of 2 chips is achieved through the TSV technology.

Description

DDR2 micro-assembly

Technical Field

The utility model relates to the technical field of memories, in particular to a DDR2 micro-assembly.

Background

In computer systems, memory performance is one of the key factors for overall machine performance. With the rapid development of microelectronics, the operating main frequency and bus bandwidth of a processor are increased by times, so that a memory is required to provide a very high data transmission rate and storage capacity to adapt to the data transmission rate and the storage capacity. The data needed by the processor during operation are all needed to be obtained from the memory, if the memory can not provide the data for the processor in time, the processor can be in a waiting state, so that the hardware resource waste is caused, and the maximum performance can not be exerted.

DDR2 SDRAM is a new generation memory technology standard developed by JEDEC (joint electron device engineering Committee), and is the biggest difference from the previous generation DDR memory technology standard in that, although the same is the basic mode of simultaneously carrying out data transmission in rising/falling delay of a clock, DDR2 memory has twice the pre-reading capability of the previous generation DDR memory, which means that DDR2 memory can read/write data at the speed of 4 times of an external bus per clock cycle and can operate at the speed of 4 times of an internal control bus.

With the rapid development of electronic technology, integrated circuits and packaging processes have broken through greatly, and SiP (System in a Package, system in package) technology has become one of the important approaches for system-class integration. Based on the system-in-package technology, all components can be integrated into the same package body in a bare chip bonding mode, so that the purposes of high integration, microminiaturization, low power consumption, high reliability and high efficiency of the system are achieved.

In order to adapt to different packaging structures, a rewiring technology is evolved, and the wiring position of an original chip is changed through a wafer-level metal rewiring process and a bump process based on the rewiring technology, so that the advantages of changing the design of an original input/output end, increasing the distance between input/output ports and the size of the bump, reducing the stress of a substrate and a component and increasing the reliability of the component can be obtained. In addition, in order to meet the vertical intercommunication between chips, through-Silicon-Via (TSV) technology is being proposed. Unlike the previous integrated circuit package bonding and bump stacking techniques, the TSV can maximize the density of chips stacked in three dimensions, minimize the overall dimensions, and greatly improve chip speed and low power consumption performance.

Disclosure of Invention

The utility model aims to provide a DDR2 micro-component to solve the problems of large size and low integration of the existing design.

In order to solve the technical problems, the utility model provides a DDR2 micro-assembly, which comprises an intermediate solder ball, a plastic package body, a first DDR2 chip, a TSV bridge piece, a second DDR2 chip and a bottom solder ball; wherein,,

the first DDR2 chip fans out the bonding pads to two sides through a rewiring design, and the middle solder balls are positioned on the back surface of the first DDR2 chip;

the TSV bridge pieces are arranged on two sides of a rewiring second DDR2 chip, and the second DDR2 chip is interconnected with the first DDR2 chip through the TSV bridge pieces;

the plastic package body is used for wrapping the first DDR2 chip, the TSV bridge piece and the second DDR2 chip, the bottom implanting ball is located at the bottom of the injection molded structure.

In one embodiment, the signal pins of the rerouted first DDR2 chip are in the same plane as the signal pins of the rerouted second DDR2 chip.

In one embodiment, the function pins WE#, A0:13, BA2:0, CAS, RAS, VREF of the first DDR2 chip and the second DDR2 chip are used in parallel.

In one embodiment, the power supply pins VDD, VDDQ, and ground VSS of the first and second DDR2 chips are combined upon rewiring.

In one embodiment, the first DDR2 chip and the second DDR2 chip access function pins CS [1-2], ODT [0-1], LDQSN [1-2], UDQSP [1-2], UDQSN [1-2], LDQSP [1-2], CKE [1-2], CK_P/N [1-2], UDM [1-2], LDM [1-2], respectively.

In one embodiment, the 32bit wide data signals of the DDR2 micro-component are all tapped.

In the DDR2 micro assembly provided by the utility model, the wiring point position of the original DDR3 bare chip is changed based on the rewiring technology, so that the packaging structure is adapted to the required packaging structure, the stacking of the DDR2 bare chips after the rewiring of 2 chips is realized through the TSV technology, and the problems of large size, low integration level and the like existing in the existing design are solved.

Drawings

FIG. 1 is a schematic block diagram of a DDR2 micro-component provided by the present utility model;

fig. 2 is a schematic diagram of a packaging structure of a DDR2 micro-component provided by the present utility model.

Detailed Description

The DDR2 micro-assembly provided by the utility model is further described in detail below with reference to the drawings and the specific embodiments. The advantages and features of the present utility model will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the utility model.

The utility model provides a DDR2 micro-component, the functional block diagram of which is shown in figure 1. The internal bare chip of the DDR2 micro assembly is a bare chip (namely a bare chip Die1 and a bare chip Die 2) after RDL, and part of functional pins are used in parallel, wherein the functional pins comprise WE#, A0:13, BA2:0 and CAS, RAS, VREF. Power supply pins VDD, VDDQ and ground VSS are incorporated at RDL to improve overcurrent capability while reducing package complexity. The functional pins CS [1-2], ODT [0-1], LDQSN [1-2], UDQSP [1-2], UDQSN [1-2], LDQSP [1-2], CKE [1-2], CK_P/N [1-2], UDM [1-2], LDM [1-2] are respectively connected into the bare chip Die1 and the bare chip Die2. In order to improve compatibility in the design of the DDR2 micro-component, 32bit wide data signals are all led out.

The overall package of the DDR2 micro assembly is shown in fig. 2, and mainly comprises an intermediate solder ball 1, a plastic package body 2, a first DDR2 chip 3 after rewiring, a TSV bridge 4, a second DDR2 chip 5 after rewiring, and a bottom solder ball 6, wherein the first DDR2 chip 3 fans out a bonding pad to two sides through rewiring design, and the intermediate solder ball 1 is formed on the back surface of the first DDR2 chip 3. And placing TSV bridge pieces 4 on two sides of the re-wired second DDR2 chip 5, and interconnecting the re-wired first DDR2 chip 3 through the TSV bridge pieces 4, so that the signal pins of the re-wired first DDR2 chip 3 and the signal pins of the re-wired second DDR2 chip 5 are on the same plane. Finally, the bottom ball 6 is planted through injection molding of the plastic package body 2. The DDR2 micro-component final package is PBGA352 with package dimensions of 11.35mm by 8.96mm by 1mm.

The above description is only illustrative of the preferred embodiments of the present utility model and is not intended to limit the scope of the present utility model, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. The DDR2 micro-assembly is characterized by comprising an intermediate solder ball, a plastic package body, a first DDR2 chip, a TSV bridge piece, a second DDR2 chip and a bottom solder ball; wherein,,

2. The DDR2 micro-component of claim 1, wherein the signal pins of the rerouted first DDR2 chip are in a same plane as the signal pins of the rerouted second DDR2 chip.

3. The DDR2 micro-component of claim 1, wherein the functional pins we#, a0:13, BA2:0, CAS, RAS, VREF of the first DDR2 chip and the second DDR2 chip are used in parallel.

4. The DDR2 micro-component of claim 1, wherein power supply pins VDD, VDDQ, and ground VSS of the first DDR2 chip and the second DDR2 chip are merged upon rewiring.

5. The DDR2 micro-component of claim 1, wherein the first DDR2 chip and the second DDR2 chip access functional pins CS [1-2], ODT [0-1], LDQSN [1-2], UDQSP [1-2], LDQSP [1-2], CKE [1-2], CK_P/N [1-2], UDM [1-2], LDM [1-2], respectively.

6. The DDR2 micro-component of claim 1, wherein the 32bit wide data signal of the DDR2 micro-component is entirely out.