CN219247827U - Reference clock signal generating circuit and phase-locked loop circuit - Google Patents

Abstract

The utility model provides a reference clock signal generating circuit and a phase-locked loop circuit, wherein the reference clock signal generating circuit comprises a two-power divider, a direct digital frequency synthesizer, an adjustable frequency multiplier, a mixer and an acoustic surface filter; in the utility model, a reference clock signal generating circuit is designed by combining a two-power divider, a direct digital frequency synthesizer, an adjustable frequency multiplier, a mixer and an acoustic surface filter, when the frequency of a finally output clock signal needs to be increased, the frequency of the clock signal can be increased by increasing the frequency multiplication number of the adjustable frequency multiplier, the output frequency requirement of the digital direct frequency synthesizer can be effectively reduced, and the small stepping function required by a later-stage circuit such as a phase-locked loop circuit is provided; the digital direct frequency synthesizer has the advantages of simple structure principle, low output frequency requirement on the digital direct frequency synthesizer, low corresponding cost and unlimited productivity.

Description

Reference clock signal generating circuit and phase-locked loop circuit

Technical Field

The present utility model relates to the field of phase-locked loop technology, and in particular, to a reference clock signal generating circuit and a phase-locked loop circuit.

Background

The phase-locked loop (Phase Locked Loop, PLL) technology is widely applied to frequency locking synthesis, and with the rapid development of modern electronic technology, the requirement for the output frequency of the phase-locked loop is higher and higher, for example, in many high-frequency or ultrahigh-frequency radio frequency technical fields, the output frequency of the phase-locked loop is required to be higher and higher, and correspondingly, the frequency of the reference clock signal of the phase-locked loop is also required to be higher and higher.

However, the reference clock signal of the phase-locked loop is generally synthesized by a digital direct frequency synthesizer (Direct Digital Synthesis, DDS), and when the frequency of the reference clock signal required by the phase-locked loop is increased, the output frequency of the digital direct frequency synthesizer can be only increased, the output frequency range of the digital direct frequency synthesizer of the same model is limited, and the higher the output frequency, the higher the price of the digital direct frequency synthesizer is, the more likely the digital direct frequency synthesizer is forbidden, which is extremely unfavorable for the production cost control and the mass production requirement of the product.

Therefore, a simple, efficient and non-limited solution for generating the reference clock signal of the phase-locked loop is needed.

Disclosure of Invention

The utility model provides a technical scheme for generating reference clock signals of a phase-locked loop, which is based on an adjustable frequency multiplier to design the reference clock signal generating circuit, improves the frequency of the reference clock signals by increasing the frequency multiplication number of the frequency multiplier so as to reduce the output frequency requirement of a digital direct frequency synthesizer and provide a small stepping function required by the phase-locked loop circuit.

In order to achieve the above object and other related objects, the present utility model provides the following technical solutions.

A reference clock signal generation circuit, comprising:

the second power divider receives the first clock signal and divides the first clock signal into a second clock signal and a third clock signal;

the direct digital frequency synthesizer is connected with the third clock signal and performs frequency synthesis processing based on the third clock signal to obtain a fourth clock signal;

the adjustable frequency multiplier is connected with the second clock signal and performs frequency multiplication processing on the second clock signal to obtain a fifth clock signal;

the frequency mixer is in radio frequency connection with the fourth clock signal, the local oscillator is in local connection with the fifth clock signal, the fourth clock signal and the fifth clock signal are subjected to frequency mixing processing, and a sixth clock signal and a seventh clock signal are obtained and output at an intermediate frequency end;

the sound surface filter is connected with the sixth clock signal and the seventh clock signal, performs filtering selection on the sixth clock signal and the seventh clock signal, and selects one of the sixth clock signal and the seventh clock signal to be output outwards and serve as a reference clock signal of a rear-stage circuit;

and adjusting the frequency of the reference clock signal by adjusting the value of the frequency multiplication number of the adjustable frequency multiplier within a preset range.

Optionally, the preset range at least includes 2 to 20.

Optionally, the reference clock signal generating circuit further includes:

and the crystal oscillator is used for generating the first clock signal.

Optionally, the crystal oscillator at least comprises a temperature compensation crystal oscillator and a constant temperature crystal oscillator.

Optionally, the reference clock signal generating circuit further includes:

and the sound surface filter is connected with the sixth clock signal and the seventh clock signal, performs filtering selection on the sixth clock signal and the seventh clock signal, and selects one of the sixth clock signal and the seventh clock signal to be output outwards as a reference clock signal of a rear-stage circuit.

A phase locked loop circuit comprising:

the reference clock signal generation circuit;

and the phase-locked loop module is connected with the reference clock signal, performs phase-locked loop control according to the reference clock signal, and obtains and outputs a target clock signal.

Optionally, the phase-locked loop module includes:

the input end of the phase frequency detector is connected with the reference clock signal;

the input end of the loop filter is connected with the output end of the phase frequency detector;

the voltage-controlled input end of the voltage-controlled oscillator is connected with the output end of the loop filter, and the first output end of the voltage-controlled oscillator outputs the target clock signal;

and the input end of the frequency divider is connected with the second output end of the voltage-controlled oscillator, and the output end of the frequency divider is connected with the feedback end of the phase frequency detector.

The utility model has the beneficial effects that: the reference clock signal generating circuit is designed by combining the two power dividers, the direct digital frequency synthesizer, the adjustable frequency multiplier, the mixer and the sound surface filter, when the frequency of the finally output clock signal needs to be increased, the frequency of the clock signal can be increased by increasing the frequency multiplication number of the adjustable frequency multiplier, the output frequency requirement of the digital direct frequency synthesizer can be effectively reduced, and the small stepping function required by a later-stage circuit such as a phase-locked loop circuit is provided; the digital direct frequency synthesizer has the advantages of simple structure principle, low output frequency requirement on the digital direct frequency synthesizer, low corresponding cost and unlimited productivity.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the utility model and together with the description, serve to explain the principles of the utility model. It is evident that the drawings in the following description are only some embodiments of the present utility model and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art. In the drawings:

FIG. 1 is a block diagram of a reference clock signal generation circuit of the present utility model;

fig. 2 is a block diagram of a phase locked loop circuit of the present utility model;

fig. 3 is a schematic diagram showing the output of a mixer and the filtering flow of an acoustic surface filter according to an exemplary embodiment of the present utility model.

Detailed Description

Further advantages and effects of the present utility model will become readily apparent to those skilled in the art from the disclosure herein, by referring to the accompanying drawings and the preferred embodiments. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model. It should be understood that the preferred embodiments are presented by way of illustration only and not by way of limitation.

It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present utility model by way of illustration, and only the components related to the present utility model are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present utility model, it will be apparent, however, to one skilled in the art that embodiments of the present utility model may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present utility model.

As described in the foregoing background, the inventors have studied to find: the reference clock signal of the existing phase-locked loop is generally synthesized and generated by a digital direct frequency synthesizer, when the frequency of the reference clock signal required by the phase-locked loop is increased, the output frequency range of the digital direct frequency synthesizer of the same model is limited only by increasing the output frequency of the digital direct frequency synthesizer, and the price of the digital direct frequency synthesizer with higher output frequency is higher, and the digital direct frequency synthesizer is possibly forbidden to operate, which is extremely unfavorable for the control of the production cost and the mass production requirement of the product.

Based on this, the present utility model proposes a reference clock signal generating circuit, as shown in fig. 1, comprising:

two power divider for receiving first clock signal f _ref And apply the first clock signal f _ref Divided into a second clock signal f _ref1 And a third clock signal f _ref2 ；

A direct digital frequency synthesizer (DDS) connected with a third clock signal f _ref2 And based on a third clock signal f _ref2 Frequency synthesis processing is carried out to obtain a fourth clock signal f _DDS ；

The frequency multiplier is adjustable within a preset range, and is connected with a second clock signal f _ref1 And for the second clock signal f _ref1 Performing frequency multiplication to obtain a fifth clock signal f _LO ；

Mixer, RF terminal RF connected to fourth clock signal f _DDS Local oscillator LO is connected with fifth clock signal f _LO For the fourth clock signal f _DDS And a fifth clock signal f _LO Mixing to obtain and output a sixth clock signal f at the intermediate frequency end IF _F1 And a seventh clock signal f _F2 。

An acoustic surface filter connected to the sixth clock signal f _F1 And a seventh clock signal f _F2 For the sixth clock signal f _F1 And a seventh clock signal f _F2 Filtering and selecting the sixth clock signal f _F1 And a seventh clock signal f _F2 Is output externally as the reference clock signal f of the subsequent circuit _PFD ；

Wherein the reference clock signal f is adjusted by adjusting the value of the frequency multiplication number of the adjustable frequency multiplier within a preset range _PFD Is a frequency of (a) is a frequency of (b).

It should be noted that, the frequency multiplication number n of the adjustable frequency multiplier is an integer greater than or equal to 2, and the preset range of the frequency multiplication number n of the adjustable frequency multiplier may be a numerical range of 2-20, 4-100, etc., which is not limited herein; the frequency multiplication number n of the adjustable frequency multiplier can be adjusted by numerical control or manually.

In detail, as shown in fig. 1, the reference clock signal generating circuit further includes:

a crystal oscillator for generating a first clock signal f _ref 。

The crystal oscillator at least comprises a temperature compensation crystal oscillator and a constant temperature crystal oscillator; the constant-temperature crystal oscillator has higher and better precision than the temperature compensation crystal oscillator, for example, the temperature compensation crystal oscillator can reach 7 orders of magnitude, and the constant-temperature crystal oscillator can reach 9 orders of magnitude, so the constant-temperature crystal oscillator is generally used for high-end measuring instruments such as a frequency meter, a signal generator, a network analyzer and the like; the temperature compensation crystal oscillator has better starting characteristics, and even if the temperature compensation crystal oscillator uses the best heating element, the temperature compensation crystal oscillator still needs a heating process, and the time for reaching the level-7 is about 5 minutes, and the time for reaching the level-9 is even higher and even more than 1 hour.

Based on the reference clock signal generating circuit, the utility model also provides a phase-locked loop circuit, as shown in fig. 2, which comprises:

a reference clock signal generation circuit;

a phase-locked loop module connected with the reference clock signal f _PFD According to the reference clock signal f _PFD Performing phase-locked loop control to obtain and output a target clock signal f _O 。

In detail, as shown in fig. 2, the phase-locked loop module includes:

phase frequency detector PFD with input end connected to reference clock signal f _PFD ；

The input end of the loop filter is connected with the output end of the phase frequency detector PFD;

a VCO having a voltage-controlled input terminal connected to the output terminal of the loop filter and a first output terminal for outputting a target clock signal f _O ；

And the input end of the frequency divider is connected with the second output end of the voltage-controlled oscillator VCO, and the output end of the frequency divider is connected with the feedback end of the phase frequency detector PFD.

The details of the phase-locked loop module may be found in the prior art, and will not be described herein.

In detail, as shown in FIGS. 1-2, the reference clock signal generating circuit of the present utility model is designed in heterodyne loop mode, and is generated by crystal oscillatorFirst clock signal f _ref The two power dividers are used for dividing the signal into two paths, one path (b path) of the signal is used as a reference signal of the DDS, the other path (a path) of the signal is connected to a local oscillator end LO of the mixer after passing through the adjustable frequency multiplier, an output signal of the DDS is connected to a radio frequency end RF of the mixer, and a sixth clock signal f is generated at an intermediate frequency end IF of the mixer _F1 ＝f _ref ×n-f _DDS And a seventh clock signal f _F2 ＝f _ref ×n+f _DDS Two signals are generated, one of the signals can be selected as the reference clock signal f of the following phase-locked loop module according to the actual use requirement and the filtering characteristic of the acoustic surface filter _PFD . The circuit can increase the reference clock signal f by increasing the frequency multiplication number n of the adjustable frequency multiplier _PFD The output of DDS can be stabilized in a lower output frequency range and provide the small step function required by the phase-locked loop circuit.

In more detail, the working flow of the reference clock signal generating circuit as shown in fig. 1 and the phase-locked loop circuit as shown in fig. 2 is as follows:

1) First clock signal f output by crystal oscillator _ref After passing through the two power dividers, the signal is divided into two paths of signals, namely a second clock signal f _ref1 And a third clock signal f _ref2 ；

2) Second clock signal f _ref1 After the frequency multiplication treatment by the adjustable frequency multiplier, a fifth clock signal f is obtained _Lo Fifth clock signal f _Lo Accessing a local oscillation end LO of the mixer; third clock signal f _ref2 As reference signal for the direct digital frequency synthesizer, the direct digital frequency synthesizer is based on the third clock signal f _ref2 Frequency synthesis processing is carried out to obtain a fourth clock signal f _DDS Fourth clock signal f _DDS A radio frequency terminal RF connected to the mixer;

3) The two signals pass through a mixer to generate a signal |alpha x f _DDS ±β×n×f _ref I (alpha, beta are integers equal to or greater than 0), wherein f _DDS +n×f _ref (i.e. the seventh clock signal f _F2 ) And n x f _ref -f _DDS (i.e. the sixth clock signal f _F1 ) The maximum power of (2) is most suitable as the post-treatmentReference signal use of stage phase-locked loop modules, i.e. reference clock signal f _PFD Has the following relation

f _PFD ＝(n×f _ref ±f _DDS )；

4) The signal generated by the mixer is passed through an acoustic surface filter (SAW) to filter out unwanted signals and output a relatively pure reference clock signal f _PFD The schematic diagram of the filtering flow of the output and the acoustic surface filter of the corresponding mixer entering the post-stage phase-locked loop module is shown in fig. 3, and is not repeated here;

5) In the phase-locked loop module, when the feedback signal fo/M is equal to f _PFD When the loop keeps stable output, the relation is formed

f _O ＝M×f _PFD ；

At f _PFD And f _ref Is put into the above formula, can obtain:

f _O ＝M×(n×f _ref ±f _DDS )；

that is, the reference clock signal f _PFD Is set to the frequency of the target clock signal f _O The reference clock signal f can be adjusted by adjusting the frequency of the adjustable frequency multiplier n within a preset range _PFD Is set to the frequency of the target clock signal f _O When the frequency of the reference clock signal f needs to be increased _PFD Is set to the frequency of the target clock signal f _O Can be realized by increasing the frequency multiplication number n of the adjustable frequency multiplier without adjusting the output frequency of the digital direct frequency synthesizer, which can effectively reduce the output frequency requirement of the digital direct frequency synthesizer.

In summary, in the reference clock signal generating circuit and the pll circuit provided by the present utility model, the reference clock signal generating circuit is designed by combining the two power dividers, the direct digital frequency synthesizer, the adjustable frequency multiplier, the mixer and the sound surface filter, when the frequency of the finally output clock signal needs to be increased, the frequency of the clock signal can be increased by increasing the frequency multiplication number of the adjustable frequency multiplier, so that the output frequency requirement of the digital direct frequency synthesizer can be effectively reduced, and the small step function required by the post-stage circuit such as the pll circuit is provided; the digital direct frequency synthesizer has the advantages of simple structure principle, low output frequency requirement on the digital direct frequency synthesizer, low corresponding cost and unlimited productivity.

The above embodiments are merely illustrative of the principles of the present utility model and its effectiveness, and are not intended to limit the utility model. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the utility model. It is therefore intended that all equivalent modifications and changes made by those skilled in the art without departing from the spirit and technical spirit of the present utility model shall be covered by the appended claims.

Claims (6)

1. A reference clock signal generation circuit, comprising:

the second power divider receives the first clock signal and divides the first clock signal into a second clock signal and a third clock signal;

the direct digital frequency synthesizer is connected with the third clock signal and performs frequency synthesis processing based on the third clock signal to obtain a fourth clock signal;

the adjustable frequency multiplier is connected with the second clock signal and performs frequency multiplication processing on the second clock signal to obtain a fifth clock signal;

the frequency mixer is in radio frequency connection with the fourth clock signal, the local oscillator is in local connection with the fifth clock signal, the fourth clock signal and the fifth clock signal are subjected to frequency mixing processing, and a sixth clock signal and a seventh clock signal are obtained and output at an intermediate frequency end;

the sound surface filter is connected with the sixth clock signal and the seventh clock signal, performs filtering selection on the sixth clock signal and the seventh clock signal, and selects one of the sixth clock signal and the seventh clock signal to be output outwards and serve as a reference clock signal of a rear-stage circuit;

and adjusting the frequency of the reference clock signal by adjusting the value of the frequency multiplication number of the adjustable frequency multiplier within a preset range.

2. The reference clock signal generation circuit of claim 1, wherein the predetermined range comprises at least 2-20.

3. The reference clock signal generation circuit of claim 1, wherein the reference clock signal generation circuit further comprises:

and the crystal oscillator is used for generating the first clock signal.

4. A reference clock signal generation circuit according to claim 3, wherein the crystal oscillator comprises at least a temperature compensated crystal oscillator and a constant temperature crystal oscillator.

5. A phase locked loop circuit comprising:

the reference clock signal generation circuit of any one of claims 1-4;

and the phase-locked loop module is connected with the reference clock signal, performs phase-locked loop control according to the reference clock signal, and obtains and outputs a target clock signal.

6. The phase-locked loop circuit of claim 5, wherein the phase-locked loop module comprises:

the input end of the phase frequency detector is connected with the reference clock signal;

the input end of the loop filter is connected with the output end of the phase frequency detector;

the voltage-controlled input end of the voltage-controlled oscillator is connected with the output end of the loop filter, and the first output end of the voltage-controlled oscillator outputs the target clock signal;

and the input end of the frequency divider is connected with the second output end of the voltage-controlled oscillator, and the output end of the frequency divider is connected with the feedback end of the phase frequency detector.

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