CN219143444U - Analog direct addition circuit and corresponding electronic equipment - Google Patents
Analog direct addition circuit and corresponding electronic equipment Download PDFInfo
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- CN219143444U CN219143444U CN202320165409.3U CN202320165409U CN219143444U CN 219143444 U CN219143444 U CN 219143444U CN 202320165409 U CN202320165409 U CN 202320165409U CN 219143444 U CN219143444 U CN 219143444U
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Abstract
The utility model provides an analog direct addition circuit and corresponding electronic equipment. The first input module may provide a first analog signal and the second input module may provide a second analog signal. The switch module comprises a first switch unit and a second switch unit, and the output module is used for outputting a first analog signal and a second analog signal. When the circuit is in an energy storage state, the first switch unit is conducted, the first input module outputs a first analog signal to the first energy storage module, and the first energy storage module stores energy of the first analog signal. When the circuit is in a superposition state, the second switch unit is conducted, the second input module outputs a second analog signal to the second energy storage module, the first energy storage module releases energy of the first analog signal, and the second energy storage module stores the energy of the first analog signal and the energy of the second analog signal.
Description
Technical Field
The present utility model relates to the field of circuits, and in particular, to an analog direct addition circuit and a corresponding electronic device.
Background
In the prior art, the response function of the operational amplifier adder circuit is uo=k1×u1+k2×u2. Wherein, K1, K2 are characteristic parameters of the impedance element of the adder, U1 and U2 are two analog signals, and Uo is an output signal. In general, K1 and K2 are not equal to 1, and because of the limited precision of element parameters, K1 and K2 are all changed within a certain range and are not constant between different samples in the same batch. Therefore, the conventional operational amplifier adder circuit has a technical problem that it is difficult to perform the direct adding operation of two analog signals.
Therefore, it is desirable to provide an analog direct adding circuit and a corresponding electronic device to solve the above-mentioned problems.
Disclosure of Invention
The utility model provides an analog direct addition circuit and corresponding electronic equipment, which effectively solve the technical problem that the existing operational amplifier addition circuit is difficult to realize direct addition operation of two analog signals.
The utility model provides an analog direct addition circuit, comprising:
a first input module for providing a first analog signal;
a second input module for providing a second analog signal;
the switch module comprises a first switch unit and a second switch unit, wherein the first switch unit is used for controlling the first analog signal to be input into the first energy storage module, and the second switch unit is used for controlling the second analog signal to be input into the second energy storage module;
the first energy storage module is used for storing energy of the first analog signal;
the second energy storage module is used for storing the energy of the second analog signal and storing the energy of the first analog signal released by the first energy storage module;
the power supply is used for supplying power to the output module;
the output module is used for outputting the first analog signal and the second analog signal;
when the circuit is in an energy storage state, the first switch unit is turned on, the first input module outputs the first analog signal to the first energy storage module, and the first energy storage module stores energy of the first analog signal;
when the circuit is in a superposition state, the second switch unit is conducted, the second input module outputs the second analog signal to the second energy storage module, the first energy storage module releases the energy of the first analog signal, the second energy storage module stores the energy of the first analog signal and the energy of the second analog signal and is used for realizing direct-adding operation of which two analog signal coefficients are 1, and the steady-state response has no system error.
In the analog direct addition circuit, the first switch unit comprises a second electronic switch piece and a third electronic switch piece, the second switch unit comprises a first electronic switch piece and a fourth electronic switch piece, one end of the first electronic switch piece is connected with the second input module, the other end of the first electronic switch piece is connected with one end of the third electronic switch piece, and the other end of the third electronic switch piece is grounded; one end of the second electronic switch piece is connected with the first input module, and the other end of the second electronic switch piece is connected with the fourth electronic switch piece;
the first energy storage module comprises a first energy storage capacitor, the second energy storage module comprises a second energy storage capacitor, one end of the first energy storage capacitor is connected between the first electronic switch piece and the third electronic switch piece, the other end of the first energy storage capacitor is connected between the second electronic switch piece and the fourth electronic switch piece, one end of the second energy storage capacitor is connected with the fourth electronic switch piece, and the other end of the second energy storage capacitor is grounded.
In the analog direct addition circuit, when the circuit is in an energy storage state, the second electronic switch piece and the third electronic switch piece are conducted, and the first input module, the second electronic switch piece, the first energy storage capacitor and the third electronic switch piece are sequentially connected to form a conducted circuit structure;
when the circuit is in a superposition state, the first electronic switch piece and the fourth electronic switch piece are conducted, and the second input module, the first electronic switch piece, the first energy storage capacitor, the fourth electronic switch piece and the second energy storage capacitor are sequentially connected to form a conducted circuit structure.
In the analog direct addition circuit of the present utility model, the charging time of the first energy storage capacitor is determined by the impedance when the second electronic switch is turned on, the impedance when the third electronic switch is turned on, and the capacitance of the first energy storage capacitor.
In the analog direct addition circuit of the present utility model, the charging time of the second energy storage capacitor is determined by the impedance of the first electronic switch when the first electronic switch is turned on, the impedance of the fourth electronic switch when the fourth electronic switch is turned on, the capacitance of the first energy storage capacitor, and the capacitance of the second energy storage capacitor.
In the analog direct addition circuit, the output module comprises an amplifier, the amplifier comprises a forward input end, a reverse input end and an output end, the forward input end is connected with the second energy storage capacitor, the reverse input end is connected with the output end, the output end is used for outputting a first analog signal and a second analog signal, the discharge time of the second energy storage capacitor is delayed, and the resistance of the output circuit is reduced under the condition that the voltage value of the output signal of the second energy storage capacitor is unchanged, so that the output driving capability of the circuit is enhanced.
In the analog direct addition circuit, the first electronic switch piece, the second electronic switch piece, the third electronic switch piece and the fourth electronic switch piece are all MOS tubes.
In the analog direct addition circuit of the present utility model, the impedance of the first electronic switch when turned on, the impedance of the second electronic switch when turned on, the impedance of the third electronic switch when turned on, and the impedance of the fourth electronic switch when turned on are all less than 1.5kΩ.
In the analog direct addition circuit, the capacitive reactance of the first energy storage capacitor is 2pF-10pF, and the capacitive reactance of the second energy storage capacitor is 2pF-10pF.
An electronic device comprising an analog direct addition circuit as claimed in any one of the preceding claims.
Compared with the prior art, the utility model has the beneficial effects that: the utility model provides an analog direct addition circuit which comprises a first input module, a second input module, a switch module, a first energy storage module, a second energy storage module and an output module. When the circuit is in an energy storage state, the first switch unit is conducted, the first input module outputs a first analog signal to the first energy storage module, and the first energy storage module stores energy of the first analog signal. When the circuit is in the superposition state, the second switch unit is conducted, and the second input module outputs a second analog signal to the second energy storage module. And the first energy storage module releases the energy of the first analog signal. Thus, the second energy storage module stores the energy of the first analog signal and the energy of the second analog signal. After multiple high-frequency conduction operations, the voltages at two ends of the second energy storage capacitor will quickly and gradually approach the voltages of the first analog signal and the second analog signal. Also, the output module may output the first analog signal and the second analog signal. Thus, the voltage of the output signal of the output module also synchronously approaches the voltage of the first analog signal superimposed with the second analog signal, i.e. the steady state response is equal to the first analog signal superimposed with the second analog signal. Therefore, the analog direct addition circuit can realize direct addition operation with two analog signal coefficients of 1, and steady state response has no systematic error. The technical problem that the existing operational amplifier adding circuit is difficult to realize direct adding operation of two analog signals is effectively solved.
Drawings
FIG. 1 is a block diagram of an embodiment of an analog direct addition circuit of the present utility model.
FIG. 2 is a circuit diagram of an embodiment of an analog direct addition circuit of the present utility model.
FIG. 3 is an equivalent circuit diagram of an embodiment of an analog direct addition circuit in a tank state according to the present utility model.
Fig. 4 is an equivalent circuit diagram of an embodiment of an analog direct addition circuit in a superimposed state according to the present utility model.
FIG. 5 is a diagram of an iterative process of one embodiment of an analog direct addition circuit of the present utility model.
FIG. 6 is a second iteration process diagram of an embodiment of an analog direct addition circuit of the present utility model.
Fig. 7 is a circuit diagram of an embodiment of a prior art adder circuit.
In the figure, 10, an analog direct addition circuit; 11. a first input module; 12. a second input module; 13. a switch module; 131. a first switching unit; 132. a second switching unit; 14. a first energy storage module; 15. a second energy storage module; 16. and an output module.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
The terms of directions used in the present utility model, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", "top" and "bottom", are used for explaining and understanding the present utility model only with reference to the orientation of the drawings, and are not intended to limit the present utility model.
The words "first," "second," and the like in the terminology of the present utility model are used for descriptive purposes only and are not to be construed as indicating or implying relative importance and not as limiting the order of precedence.
In the drawings, like structural elements are denoted by like reference numerals.
Referring to fig. 1 and 2, the present utility model provides an analog direct adding circuit 10 and a corresponding electronic device. The analog direct addition circuit 10 is applied to an electronic device, and the analog direct addition circuit 10 comprises a first input module 11, a second input module 12, a switch module 13, a first energy storage module 14, a second energy storage module 15 and an output module 16. The first input module 11 is used for providing a first analog signal and the second input module 12 is used for providing a second analog signal. The switch module 13 includes a first switch unit 131 and a second switch unit 132, wherein the first switch unit 131 is used for controlling the first analog signal to be input into the first energy storage module 14, and the second switch unit 132 is used for controlling the second analog signal to be input into the second energy storage module 15. The first energy storage module 14 is used for storing energy of the first analog signal, the second energy storage module 15 is used for storing energy of the second analog signal and storing energy of the first analog signal released by the first energy storage module 14, and the output module 16 is used for outputting the first analog signal and the second analog signal.
Referring to fig. 2, the first switching unit 131 includes a second electronic switching element S2 and a third electronic switching element S3, and the second switching unit 132 includes a first electronic switching element S1 and a fourth electronic switching element S4. One end of the first electronic switch piece S1 is connected with the second input module 12, the other end of the first electronic switch piece S1 is connected with one end of the third electronic switch piece S3, and the other end of the third electronic switch piece S3 is grounded. One end of the second electronic switch piece S2 is connected with the first input module 11, and the other end of the second electronic switch piece S2 is connected with the fourth electronic switch piece S4.
Referring to fig. 2, the first energy storage module 14 includes a first energy storage capacitor C3, the second energy storage module 15 includes a second energy storage capacitor C4, one end of the first energy storage capacitor C3 is connected between the first electronic switch S1 and the third electronic switch S3, the other end of the first energy storage capacitor C3 is connected between the second electronic switch S2 and the fourth electronic switch S4, one end of the second energy storage capacitor C4 is connected with the fourth electronic switch S4, and the other end of the second energy storage capacitor C4 is grounded. The capacitive reactance of the first energy storage capacitor C3 is 2pF-10pF, and the capacitive reactance of the second energy storage capacitor C4 is 2pF-10pF.
Referring to fig. 2, the output module 16 includes an amplifier U4, and the amplifier U4 includes a forward input terminal, a reverse input terminal and an output terminal. The analog direct summing circuit 10 also includes a power supply VCC for powering an amplifier U4 of the output module 16, whose VEE is grounded or a negative power supply. The positive input end is connected with the second energy storage capacitor C4, the negative input end is connected with the output end, and the output end is used for outputting a first analog signal and a second analog signal. The amplifier U4 is configured to delay the discharging time of the second energy storage capacitor C4, and reduce the resistance of the output circuit while keeping the voltage value of the output signal of the second energy storage capacitor C4 unchanged, so as to enhance the output driving capability of the circuit. The first input module 11 further includes a first pre-stage output resistor R5 and a first pre-stage output capacitor C1, and the second input module 12 further includes a second pre-stage output resistor R6 and a second pre-stage output capacitor C2.
Referring to fig. 1 and 2, when the circuit is in the energy storage state, the first switch unit 131 is turned on. The first input module 11 outputs the first analog signal to the first energy storage module 14, and the first energy storage module 14 stores energy of the first analog signal. When the circuit is in the superimposed state, the second switching unit 132 is turned on. The second input module 12 outputs the second analog signal to the second energy storage module 15, and the first energy storage module 14 releases the energy of the first analog signal, and the second energy storage module 15 stores the energy of the first analog signal and the energy of the second analog signal.
Referring to fig. 7, in the prior art, the actual response function of the adder circuit is uo= (u1×r2+u2×r1) ×r3+r4)/(r1+r2)/R3. Therefore, uo=u1+u2 only when there is an ideal state of r1=r2=r3=r4. However, it is generally difficult to achieve in a real situation. Wherein U1 and U2 are two analog signals input by the adder circuit, and Uo is a signal output by the adder circuit. R1, R2, R3 and R4 are respectively four resistors in the summing circuit, and U3 is an amplifier of the summing circuit. In practical use, the signals need to be superimposed in original proportions, for example, two correlated single-ended stereo signals are synthesized into a single-channel signal. However, if the above-described method is used for the superimposing operation, the left and right channels are mismatched in a small proportion due to the systematic error.
Referring to fig. 3, when the circuit is in the energy storage state, the second electronic switch S2 and the third electronic switch S3 are turned on, and the first electronic switch S1 and the fourth electronic switch S4 are turned off. The first input module 11, the second electronic switch component S2, the first energy storage capacitor C3, and the third electronic switch component S3 are sequentially connected to form a conductive circuit structure. The first input module 11 inputs the first analog signal to charge the first storage capacitor C3, so that the first storage capacitor C3 stores energy of the first analog signal.
Referring to fig. 4, when the circuit is in the stacked state, the second electronic switch S2 and the third electronic switch S3 are turned off, and the first electronic switch S1 and the fourth electronic switch S4 are turned on. The second input module 12, the first electronic switch component S1, the first energy storage capacitor C3, the fourth electronic switch component S4, and the second energy storage capacitor C4 are sequentially connected to form a conductive circuit structure. The second input module 12 outputs a second analog signal to a second storage capacitor, and the first storage capacitor C3 discharges energy of the first analog signal. The second storage capacitor C4 thus stores the energy of the first analog signal and the energy of the second analog signal. Through multiple high-frequency switching operations, the voltage across the second storage capacitor C4 will quickly gradually approach the voltages of the first analog signal and the second analog signal. The signal output by the amplifier U4 is also synchronously approaching to the first analog signal and the second analog signal through the isolation amplification of the amplifier U4, namely, the steady state response is equal to the first analog signal and the second analog signal. Thus, the analog direct addition circuit 10 can realize direct addition operation in which both analog signal coefficients are 1, and the steady-state response is free from systematic errors.
Referring to fig. 2, the impedance of the first electronic switch S1, the impedance of the second electronic switch S2, the impedance of the third electronic switch S3, and the impedance of the fourth electronic switch S4 are all less than 1.5kΩ. The first electronic switch S1, the second electronic switch S2, the third electronic switch S3, and the fourth electronic switch S4 are all MOS transistors. The first electronic switching element S1, the second electronic switching element S2, the third electronic switching element S3, and the fourth electronic switching element S4 are used as switches for switching the circuit in the energy storage state or the stacked state.
Referring to fig. 3, when the circuit is in the energy storage state, the second electronic switch S2 and the third electronic switch S3 are turned on, and the first input module 11, the second electronic switch S2, the first energy storage capacitor C3, and the third electronic switch S3 are sequentially connected to form a conductive circuit structure. When the circuit is in the energy storage state, the second electronic switch piece S2 and the third electronic switch piece S3 are turned on, and the first electronic switch piece S1 and the fourth electronic switch piece S4 are turned off. At this time, the impedance of the second electronic switch S2 and the third electronic switch S3 is less than 1.5kΩ, and in order to increase the response speed, the process of the electronic switch needs to ensure a very small distributed capacitance, which is negligible. The impedance formed in the circuit when the first electronic switch S1 and the fourth electronic switch S4 are turned off is about 10mΩ or more, and the first pre-stage circuit output resistance R5 is generally less than 100 Ω. The first pre-stage output capacitance C1 is typically required to be less than 10pF. Therefore, when the circuit is at the working frequency smaller than 1MHz, the impedance of the output resistor R5 of the first pre-stage circuit, the capacitance of the output capacitor C1 of the first pre-stage circuit, the impedance of the first electronic switch piece S1 and the impedance of the fourth electronic switch piece S4 are all negligible, and the circuit is simplified into the form of FIG. 3. The analog direct adding circuit 10 further includes a parasitic capacitance Cp, which is a parasitic capacitance Cp inside the chip and at two ends of the first storage capacitor C3 on the PCB board, and the parasitic capacitance Cp is generally about 2 to 3 pF. The charging time of the first energy storage capacitor C3 is determined by the impedance of the second electronic switch S2 when it is turned on, the impedance of the third electronic switch S3 when it is turned on, and the capacitive reactance of the first energy storage capacitor C3. τ1≡2rc×cf, taking rc=1.5k, cf=10pf, so τ1=3×10 (-8) seconds. Wherein τ1 is the charging time of the first energy storage capacitor C3, cf is the capacitance of the first energy storage capacitor, and Rc is the impedance of the second electronic switch S2 or the third electronic switch S3.
Referring to fig. 4, when the circuit is in the stacked state, the first electronic switch S1 and the fourth electronic switch S4 are turned on, and the second input module 12, the first electronic switch S1, the first energy storage capacitor C3, the fourth electronic switch S4, and the second energy storage capacitor C2 are sequentially connected to form a turned-on circuit structure. Neglecting the effects of the impedance R6 of the output resistor of the second pre-stage circuit, the capacitive reactance of the output capacitor C2 of the second pre-stage circuit, the impedance of the second electronic switch S2 and the third electronic switch S3, a simplified circuit of the superposition phase is shown in fig. 4 below. The analog direct addition circuit 10 further includes a first distributed capacitor and a second distributed capacitor, wherein the first distributed capacitor is a distributed capacitor at two ends of the first energy storage capacitor C3, and the second distributed capacitor is a distributed capacitor at two ends of the second energy storage capacitor C4. The charging time of the second energy storage capacitor C4 is determined by the impedance of the first electronic switch S1 when it is turned on, the impedance of the fourth electronic switch S4 when it is turned on, the capacitive reactance of the first energy storage capacitor C3, and the capacitive reactance of the second energy storage capacitor C4. τ2≡2rc×cf×co/(cf+co), it is apparent that τ2 is smaller than τ1. I.e. the discharge rate is greater than the charge rate, taking cf=co=10pf, τ2=1.5 x 10 (-8) seconds. Wherein τ2 is the charging time of the second energy storage capacitor C4, rc is the impedance of the first electronic switch S4 or the fourth electronic switch S4, cf is the capacitance of the first energy storage capacitor C3, and Co is the capacitance of the second energy storage capacitor C4. The energy storage period duration is taken to be T1, wherein T1=τ1. The overlapping period duration is taken to be T2, where t2=τ2. And τ1=2×τ2, neglecting the time of the switching process, and completing the period of once energy storage and superposition to obtain t=t1+t2=τ1+τ2=4.5×10 (-8) seconds, the switching frequency fs=1/t=22.2 MHz, and the duty cycle is 66.7%.
Referring to fig. 5, the initial condition u1=0v, u2=1v, and the voltage stored in the first energy storage capacitor and the voltage stored in the second energy storage capacitor are equal to 0V. Through theoretical calculation, 4 steps of iteration are carried out, and the error of the storage voltage of the second energy storage capacitor C4 is smaller than 36.8%. And performing 12 steps of iteration, wherein the error of the storage voltage of the second energy storage capacitor C4 is less than 5%. After 26 steps of iteration, the error of the stored voltage of the second energy storage capacitor C4 is less than 1 per mill, and the iteration process is shown in fig. 5. In fig. 5, the abscissa is a single beat count, each step iterates 2 beats, the circuit is in the energy storage state, and the circuit is in the superposition state, and each single beat is executed. Wherein U1 is a first analog signal, U2 is a second analog signal, VCf y is a storage voltage of the first storage capacitor C3, and VCout is a storage voltage of the second storage capacitor C4.
Referring to fig. 6, the initial condition u1=1v, u2=0v, and the voltage stored in the first energy storage capacitor and the voltage stored in the second energy storage capacitor C4 are equal to 0V. Through theoretical calculation, 4 steps of iteration are carried out, and the error of the storage voltage of the second energy storage capacitor C4 is smaller than 36.8%. After 12 steps of iteration, the error of the storage voltage of the second energy storage capacitor C4 is smaller than 5%. After 25 steps of iteration, the error of the stored voltage of the second energy storage capacitor C4 is less than 1 per mill, and the iteration process is shown in fig. 6. In fig. 6, the abscissa is a single beat count, each step iterates 2 beats, the circuit is in the energy storage state, and the circuit is in the superposition state, and each single beat is executed. Wherein U1 is a first analog signal, U2 is a second analog signal, VCf y is a storage voltage of the first storage capacitor C3, and VCout is a storage voltage of the second storage capacitor C4.
If the switching period T is prolonged by 2 beats per continuous under the above conditions, the overall response speed is reduced as compared with calculation, and when T is far greater than 3×τ2, the response speed depends on the switching period T. The overall response speed is almost unchanged by decreasing the switching period, and the relationship between the specific switching period and the overall response speed is shown in the following table. And the switching period is reduced, and the amplitude of the stepped wave output by the second energy storage capacitor is reduced. However, after the switching speed is increased, the influence of the switching process is gradually revealed, and the actual response speed is reduced. It is generally recommended that the switching period be no greater than τ1+τ2, and that the switching period be related to the error as shown in the following table. The switching period is T, VCf l y is the storage voltage of the first storage capacitor C3 in the initial state, VCout is the storage voltage of the second storage capacitor C4 in the initial state, and τ1=2×τ2.
VCf y is the storage voltage of the first storage capacitor C3 in the initial state, and VCout is the storage voltage of the second storage capacitor C4 in the initial state. Therefore, when the first analog signal and the second analog signal are not input, the voltages of the first tank capacitor C3 and the second tank capacitor C4 are both 0V, as shown in the above table. After the first analog signal and the second analog signal are input, u1=0v and u2=1v, that is, the voltage of the first analog signal input is 0V, and the voltage of the second analog signal input is 1V. Based on the above table, in conjunction with fig. 5, after multiple iterations, the final voltages of the first energy storage capacitor C3 and the second energy storage capacitor C4 are 1V.
As shown in the above table, t3=3×τ2, u1=0v, u2=1v. I.e. the switching period is 3 x tau 2, the voltage of the first analog signal input is 0V and the voltage of the second analog signal input is 1V. The error of the stored voltage of the second storage capacitor C4 is less than 36.8%, 4 iterations are required, and the response time is 12 x tau 2. The error of the stored voltage of the second storage capacitor C4 is less than 5%, 12 iterations are required, and the response time is 36 x tau 2. The error of the stored voltage of the second energy storage capacitor C4 is less than 1%o, 25 iterations are required, and the response time is 75 ×.
As shown in the above table, t3=9×τ2, u1=0v, u2=1v. I.e. the switching period is 9 x τ2, which is extended by a factor of 3 compared to t3=3 x τ2. The voltage of the first analog signal input is 0V, and the voltage of the second analog signal input is 1V. The error of the stored voltage of the second storage capacitor C4 is less than 36.8%, 2 iterations are required, and the response time is 18 x tau 2. The error of the stored voltage of the second storage capacitor C4 is less than 5%, 5 iterations are required, and the response time is 45 x tau 2. The error of the stored voltage of the second energy storage capacitor C4 is less than 1%o, 12 iterations are needed, and the response time is 108 ×. Thus, the response time for a switching period of 9 τ2 is greater than the response time for a switching period of 3 τ2. Thereby verifying the conclusion above: the switching period is prolonged, and the overall response speed is reduced.
As shown in the above table, t3=τ2, u1=0v, u2=1v. I.e. the switching period is τ2, which is reduced to 1/3 compared to t3=3×τ2. The voltage of the first analog signal input is 0V, and the voltage of the second analog signal input is 1V. The error of the stored voltage of the second storage capacitor C4 is less than 36.8%, 12 iterations are required, and the response time is 12 x tau 2. The error of the stored voltage of the second storage capacitor C4 is less than 5%, 33 iterations are required, and the response time is 33 x tau 2. The error of the stored voltage of the second energy storage capacitor C4 is less than 1%o, 73 iterations are needed, and the response time is 73 ×. Thus, the response time for a switching period τ2 is approximately equal to the response time for a switching period of 3 τ2. Thereby verifying the conclusion above: the switching period is reduced, and the overall response speed is almost unchanged.
In summary, in theory, the 3dB bandwidth estimation of the response speed of the first analog signal and the second analog signal is about 1/(2×pi (τ1+τ2) ×4) ×884kHz, so that the capacitive reactance of the second storage capacitor is properly reduced, the duty cycle is increased, the duration of τ2 can be shortened, and the bandwidth can be slightly increased.
If the bandwidth needs to be further improved, the optimization circuit parameters can be continuously adjusted. Since τ1≡2rc×cf, decreasing the impedance when the second electronic switching element S2 or the third electronic switching element S3 is turned on, or decreasing the capacitance of the first storage capacitor C3, the charging time of the first storage capacitor C3 can be reduced. Because the process of the switching tube needs to ensure extremely small distributed capacitance, the capacitance reactance of the energy storage capacitor can be reduced by reducing the distributed capacitance. Further, reducing the capacitive reactance of the first distributed capacitance may also reduce the charging time of the first storage capacitance C3.
Since τ2≡2rc×cf×co/(cf+co), decreasing the impedance of the first electronic switch S1 or the fourth electronic switch S4 when turned on, or decreasing the capacitance of the first storage capacitor C3 or the capacitance of the second storage capacitor C4, may result in a decrease in τ2, i.e. a decrease in the charging time of the second storage capacitor C4. And the capacitive reactance of the energy storage capacitor can be reduced by reducing the distributed capacitance, so that the charging time of the second energy storage capacitor C4 can be reduced by reducing the capacitive reactance of the first distributed capacitance or the capacitive reactance of the second distributed capacitance. Since the calculation formula of the bandwidth is 1/(2×pi×1+τ2) ×4, decreasing τ1 and τ2 can reduce the charging time of the first energy storage capacitor C3 or the charging time of the second energy storage capacitor C4, and thus the bandwidth is increased. From the above conclusion τ1=2τ2, the bandwidth is 1/24×pi×τ2. If τ2 is shortened to 1/2, the bandwidth increases by a factor of 2. The switching frequency is correspondingly increased, which is the inverse of the switching period. And ensure that the output resistance and output capacitance of the preceding stage input circuit are still small enough, so that the influence on the input of the adding circuit can be reduced.
The working principle of the utility model is as follows: when the analog direct addition circuit 10 works, the circuit is in an energy storage state, the second electronic switch piece S2 and the third electronic switch piece S3 are turned on, and the first electronic switch piece S1 and the fourth electronic switch piece S4 are turned off. The first input module 11, the second electronic switch component S2, the third electronic switch component S3 and the first energy storage capacitor C3 are sequentially connected to form a conductive circuit structure. The first input module 11 inputs the first analog signal to charge the first storage capacitor C3, so that the first storage capacitor C4 stores energy of the first analog signal.
The circuit is in an energy storage state, the second electronic switch piece S2 and the third electronic switch piece S3 are opened, and the first electronic switch piece S1 and the fourth electronic switch piece S4 are closed. The second input module 12, the first electronic switch component S1, the first energy storage capacitor C3, the fourth electronic switch component S4, and the second energy storage capacitor C4 are sequentially connected to form a conductive circuit structure. The second input module 12 outputs the second analog signal to the second storage capacitor C4, and the first storage capacitor C3 discharges the energy of the first analog signal. Thus, the second storage capacitor C4 stores the energy of the first analog signal and the energy of the second analog signal. Through multiple high-frequency switching operations, the voltage across the second storage capacitor C4 will quickly gradually approach the voltages of the first analog signal and the second analog signal. The second tank capacitor C4 then transmits the first analog signal and the second analog signal to the amplifier U4 of the output module 16. Then, the amplifier outputs the first analog signal and the second analog signal. The amplifier U4 performs isolation amplification on the first analog signal and the second analog signal, and the signal output by the amplifier U4 also synchronously approaches to the first analog signal and overlaps the second analog signal, i.e. the steady state response is equal to the first analog signal and overlaps the second analog signal. Thus, the analog direct addition circuit 10 can realize direct addition operation in which both analog signal coefficients are 1, and the steady-state response is free from systematic errors.
The utility model provides an analog direct addition circuit which comprises a first input module, a second input module, a switch module, a first energy storage module, a second energy storage module and an output module. When the circuit is in an energy storage state, the first switch unit is conducted, the first input module outputs a first analog signal to the first energy storage module, and the first energy storage module stores energy of the first analog signal. When the circuit is in the superposition state, the second switch unit is conducted, and the second input module outputs a second analog signal to the second energy storage module. And the first energy storage module releases the energy of the first analog signal. Thus, the second energy storage module stores the energy of the first analog signal and the energy of the second analog signal. After multiple high-frequency conduction operations, the voltages at two ends of the second energy storage capacitor will quickly and gradually approach the voltages of the first analog signal and the second analog signal. Also, the output module may output the first analog signal and the second analog signal. Thus, the voltage of the output signal of the output module also synchronously approaches the voltage of the first analog signal superimposed with the second analog signal, i.e. the steady state response is equal to the first analog signal superimposed with the second analog signal. Therefore, the analog direct addition circuit can realize direct addition operation with two analog signal coefficients of 1, and steady state response has no systematic error. The technical problem that the existing operational amplifier adding circuit is difficult to realize direct adding operation of two analog signals is effectively solved.
In summary, although the present utility model has been described in terms of the preferred embodiments, the preferred embodiments are not limited to the above embodiments, and various modifications and changes can be made by one skilled in the art without departing from the spirit and scope of the utility model, and the scope of the utility model is defined by the appended claims.
Claims (10)
1. An analog direct addition circuit, comprising:
a first input module for providing a first analog signal;
a second input module for providing a second analog signal;
the switch module comprises a first switch unit and a second switch unit, wherein the first switch unit is used for controlling the first analog signal to be input into the first energy storage module, and the second switch unit is used for controlling the second analog signal to be input into the second energy storage module;
the first energy storage module is used for storing energy of the first analog signal;
the second energy storage module is used for storing the energy of the second analog signal and storing the energy of the first analog signal released by the first energy storage module;
the power supply is used for supplying power to the output module;
the output module is used for outputting the first analog signal and the second analog signal;
when the circuit is in an energy storage state, the first switch unit is turned on, the first input module outputs the first analog signal to the first energy storage module, and the first energy storage module stores energy of the first analog signal;
when the circuit is in a superposition state, the second switch unit is conducted, the second input module outputs the second analog signal to the second energy storage module, the first energy storage module releases the energy of the first analog signal, and the second energy storage module stores the energy of the first analog signal and the energy of the second analog signal.
2. An analog direct addition circuit according to claim 1, wherein said first switch unit comprises a second electronic switch element and a third electronic switch element, said second switch unit comprises a first electronic switch element and a fourth electronic switch element, one end of said first electronic switch element is connected to said second input module, the other end of said first electronic switch element is connected to one end of said third electronic switch element, and the other end of said third electronic switch element is grounded; one end of the second electronic switch piece is connected with the first input module, and the other end of the second electronic switch piece is connected with the fourth electronic switch piece;
the first energy storage module comprises a first energy storage capacitor, the second energy storage module comprises a second energy storage capacitor, one end of the first energy storage capacitor is connected between the first electronic switch piece and the third electronic switch piece, the other end of the first energy storage capacitor is connected between the second electronic switch piece and the fourth electronic switch piece, one end of the second energy storage capacitor is connected with the fourth electronic switch piece, and the other end of the second energy storage capacitor is grounded.
3. An analog direct addition circuit according to claim 2, wherein when the circuit is in an energy storage state, said second electronic switch and said third electronic switch are turned on, and said first input module, said second electronic switch, said first energy storage capacitor, and said third electronic switch are connected in sequence to form a conductive circuit structure;
when the circuit is in a superposition state, the first electronic switch piece and the fourth electronic switch piece are conducted, and the second input module, the first electronic switch piece, the first energy storage capacitor, the fourth electronic switch piece and the second energy storage capacitor are sequentially connected to form a conducted circuit structure.
4. An analog direct addition circuit according to claim 2, wherein the charge time of said first storage capacitor is determined by the impedance of said second electronic switch when said second electronic switch is on, the impedance of said third electronic switch when said third electronic switch is on, and the capacitive reactance of said first storage capacitor.
5. An analog direct addition circuit according to claim 2, wherein the charging time of said second storage capacitor is determined by the impedance of said first electronic switch when on, the impedance of said fourth electronic switch when on, the capacitive reactance of said first storage capacitor and the capacitive reactance of said second storage capacitor.
6. An analog direct addition circuit according to claim 2, wherein said output module comprises an amplifier, said amplifier comprising a forward input, a reverse input and an output, said forward input being connected to said second storage capacitor, said reverse input being connected to said output, said output being adapted to output a first analog signal and a second analog signal.
7. An analog direct addition circuit according to claim 2, wherein said first electronic switch, said second electronic switch, said third electronic switch, and said fourth electronic switch are MOS transistors.
8. An analog direct addition circuit according to claim 2, wherein the impedance of said first electronic switch when on, the impedance of said second electronic switch when on, the impedance of said third electronic switch when on, and the impedance of said fourth electronic switch when on are all less than 1.5kΩ.
9. An analog direct addition circuit according to claim 2, wherein the capacitive reactance of said first storage capacitor is in the range of 2pF to 10pF and the capacitive reactance of said second storage capacitor is in the range of 2pF to 10pF.
10. An electronic device comprising an analog direct addition circuit as claimed in any one of claims 1 to 9.
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| CN202320165409.3U CN219143444U (en) | 2023-02-01 | 2023-02-01 | Analog direct addition circuit and corresponding electronic equipment |
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| CN202320165409.3U CN219143444U (en) | 2023-02-01 | 2023-02-01 | Analog direct addition circuit and corresponding electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116094512A (en) * | 2023-02-01 | 2023-05-09 | 无锡宇宁智能科技有限公司 | Analog direct addition circuit and corresponding electronic equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116094512A (en) * | 2023-02-01 | 2023-05-09 | 无锡宇宁智能科技有限公司 | Analog direct addition circuit and corresponding electronic equipment |
| CN116094512B (en) * | 2023-02-01 | 2023-12-12 | 无锡宇宁智能科技有限公司 | Analog direct addition circuit and corresponding electronic equipment |
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