CN219124193U

CN219124193U - TTL (time to live) conversion compatible RS232 level conversion circuit

Info

Publication number: CN219124193U
Application number: CN202223492460.XU
Authority: CN
Inventors: 李振勇
Original assignee: Guangzhou Xingyi Electronic Technology Co ltd
Current assignee: Guangzhou Xingyi Electronic Technology Co ltd
Priority date: 2022-12-27
Filing date: 2022-12-27
Publication date: 2023-06-02
Anticipated expiration: 2032-12-27

Abstract

The utility model provides a TTL-to-compatible RS232 level conversion circuit, which is low in cost and simple and reliable. The circuit comprises an exclusive or gate logic chip (U1); the first pins (1A and 1B) of the exclusive OR gate logic chip (U1) are grounded; a fourth pin (2A) of the exclusive-OR gate logic chip (U1) is connected to the signal U0_TX; the fifth pin (2B) of the exclusive-OR gate logic chip (U1) is connected to the tenth pin (3B) of the exclusive-OR gate logic chip (U1); a sixth pin (2Y) of the exclusive-OR gate logic chip (U1) is connected with a second resistor (R2) in series and is connected to an output signal DOUT; a fifth pin (2B) of the exclusive-OR gate logic chip (U1) is connected to the input signal U0_RX; an eighth pin (3Y) of the exclusive-OR gate logic chip (U1) is connected with a sixth resistor (R6) in series and is connected to a signal U0_RX; twelfth and thirteenth pins (4A and 4B) of the exclusive OR gate logic chip (U1) are connected to ground.

Description

TTL (time to live) conversion compatible RS232 level conversion circuit

Technical Field

The utility model relates to the technical field of electronic circuits, in particular to a TTL-to-compatible RS232 level conversion circuit.

Background

At present, most of TTL-to-RS 232 level conversion circuits adopt special chips, such as MAX232 chips, and the special chips can convert standard RS232 level, but the cost of the chips is higher than that of the exclusive OR gate logic chips used in the utility model. In addition, the user singlechip sometimes needs to convert TTL into RS232 to communicate with a computer end, and sometimes needs to convert TTL into TTL to communicate with another section of singlechip. If the MAX232 chip circuit is used, it is necessary to disconnect the two signal lines for transmission and reception before the MAX232 chip and switch to the TTL port, which is troublesome.

Disclosure of Invention

The application provides a TTL-to-compatible RS232 level conversion circuit which is low in cost and simple and reliable.

The TTL conversion compatible RS232 level conversion circuit comprises:

the 1A/1B pin of the exclusive-OR gate logic chip U1 is connected to the ground;

the 1Y pin of the exclusive OR gate logic chip U1 is suspended and is not used;

the 2A of the exclusive-OR gate logic chip U1 is connected to a signal U0_TX, wherein U0_TX is generally connected to a TX pin of a serial port of the singlechip;

the 2B of the exclusive-OR gate logic chip U1 is connected to the 3B pin of the U1;

the 2Y serial 100R resistor R2 of the exclusive OR gate logic chip U1 is connected to an output signal DOUT, wherein DOUT is generally connected to an RX pin of the RS232 level device;

the 2B of the exclusive-OR gate logic chip U1 is connected to an input signal U0_RX, wherein U0_RX is generally connected to an RX pin of a serial port of the singlechip;

the 3Y serial 100R resistor R6 of the exclusive OR gate logic chip U1 is connected to a signal U0_RX, wherein the U0_RX is generally connected to an RX pin of a serial port of the singlechip;

the 3A of the exclusive-OR gate logic chip U1 is connected with a signal DIN in series with R4/R3 in succession and is connected with R5/D1 in parallel in succession, wherein DIN is generally connected with a TX pin of RS232 level equipment;

the 3B of the exclusive-OR gate logic chip U1 is connected to the 2B of the exclusive-OR gate logic chip U1, and is connected to a 5V power supply through R1 and is connected to the ground through JP 1;

the 4Y pin of the exclusive-OR gate logic chip U1 is suspended;

4A/4B of the exclusive OR gate logic chip U1 is connected to the ground;

3B of the exclusive-OR gate logic chip U1 is connected to a 5V power supply through R1 and connected to ground through JP 1; JP1 is a shorting pad for providing on-off state of the bond.

The beneficial effects of the utility model are mainly as follows:

compared with the prior art, the TTL conversion compatible RS232 level conversion circuit is low in cost and simple and reliable in circuit. Shorting and disconnection of the pads are supported to select TTL to RS232 or TTL to TTL.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present utility model, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an embodiment of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the utility model are shown.

All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

In the description of the present utility model, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.

In order to achieve the above objective, the present utility model provides the following technical solution, including an exclusive or gate logic chip U1, see fig. 1 in detail.

Term interpretation: TX is typically single-chip serial port communication, and signal transmission and RX is receiving.

The 1A/1B pin of the exclusive OR gate logic chip U1 is connected to the ground.

The 1Y pin of the exclusive OR gate logic chip U1 is suspended and is not used.

The 2A of the exclusive-OR gate logic chip U1 is connected to a signal U0_TX, wherein U0_TX is generally connected to a TX pin of a serial port of the singlechip.

And the 2B of the exclusive or gate logic chip U1 is connected to the 3B pin of the U1.

The 2Y serial 100R resistor R2 of the exclusive or gate logic chip U1 is connected to the output signal DOUT, where DOUT is typically connected to the RX pin of the RS232 level device.

The 2B of the exclusive-or gate logic chip U1 is connected to the input signal u0_rx, where u0_rx is generally connected to an RX pin of the serial port of the single chip microcomputer.

The 3Y serial 100R resistor R6 of the exclusive OR gate logic chip U1 is connected to the signal U0_RX, wherein the U0_RX is generally connected to an RX pin of a serial port of the singlechip.

The 3A of the exclusive OR gate logic chip U1 is connected in series with R4/R3 in succession to signal DIN, which is connected in parallel with R5/D1 in succession, wherein DIN is generally connected to the TX pin of the RS232 level device.

The 3B of the exclusive or gate logic chip U1 is connected to its own 2B and through R1 to a 5V power supply and through JP1 to ground.

And the 4Y pin of the exclusive OR gate logic chip U1 is suspended.

4A/4B of the exclusive OR gate logic chip U1 is connected to ground.

Description of specific model of chip:

the model of the exclusive or gate logic chip U1 is SN74AHC86PWR, which is a 4-way two-input exclusive or gate logic chip, and the actual circuit can only use 2 ways.

The D1 is a voltage stabilizing diode, the model is BZT52C5V1S, and the external input signal DIN is limited to be less than 5V so as not to burn U1 under high voltage.

So JP1 is a shorting pad, which selects TTL to RS232 mode when the soldering is disconnected and TTL to TTL mode when the soldering is connected.

TTL level: greater than 2.4V represents a logic 1 and less than 0.8V represents a logic 0.

RS232 level: +3 to +15V represent logic 0, and-3V to-15V represent logic 1.

It is understood that the TLL and RS232 levels are inverted, representing the same logic.

An RS232 chip, the inside of which is provided with a transmitter and a receiver; the transmitter transmits the normal RS232 level, but the receiver supports the incoming RS232 level as well as the response TTL level. This means that on the circuit, the singlechip only needs to do level logic inversion when transmitting, and voltage limitation and logic inversion when receiving.

According to the principles of the utility model we look at the circuit. When JP1 is off, 2B/3B is high, and input 2A/3A implements a logical inversion, i.e., is compatible with RS232 mode, as can be seen from the truth table of the exclusive OR gate of the following table. When JP1 is short-circuited, 2B/3B is low level, and input and output logic is consistent, namely TTL mode.

A	B	Output Y
			0	0	0
0	1	1
			1	0	1
1	1	0

Exclusive OR gate truth table

When the RS232 mode is compatible:

u0TX is connected to 2A, output 2Y is connected in series with R2 resistor to DOUT, and the transmission completes the logic reversal. Wherein the R2 resistor acts as a current limiter.

The PC end RS232 level DIN is connected in series with R3/R4 to 3A, D1 is connected in parallel in the middle, and the output 3Y is connected in series with R6 to U0RX. Parallel D1 is a 5.1V zener diode, R3 and D1 limit the voltage of 3A to 5.1V when DIN input is 15V, so as not to burn out the chip U1 at high voltage. When DIN input is 15V, D1 will be on, limiting the voltage of 3A to 0.3V. Wherein, R4 plays the effect of current limiting, and R5 acts as the load of D1, makes D1 work more stable.

Thus, the description of the compatible RS232 mode is finished. And the JP1 switch is supported to switch between a compatible 232 level mode and a TTL level mode, which is very convenient.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.

Claims

1. A TTL-to-compatible RS232 level shifter circuit comprising:

an exclusive-OR gate logic chip (U1);

the first pins (1A and 1B) of the exclusive OR gate logic chip (U1) are grounded;

a third pin (1Y) of the exclusive-OR gate logic chip (U1) is suspended;

a fourth pin (2A) of the exclusive-OR gate logic chip (U1) is connected to the signal U0_TX; wherein U0TX is connected to a TX pin of a serial port of the singlechip;

the fifth pin (2B) of the exclusive-OR gate logic chip (U1) is connected to the tenth pin (3B) of the exclusive-OR gate logic chip (U1);

a sixth pin (2Y) of the exclusive-OR gate logic chip (U1) is connected with a second resistor (R2) in series and is connected to an output signal DOUT; wherein DOUT is connected to an RX pin of the RS232 level device;

a fifth pin (2B) of the exclusive-OR gate logic chip (U1) is connected to the input signal U0_RX; wherein U0_RX is generally connected to an RX pin of a serial port of the singlechip;

an eighth pin (3Y) of the exclusive-OR gate logic chip (U1) is connected with a sixth resistor (R6) in series and is connected to a signal U0_RX; wherein U0_RX is generally connected to an RX pin of the serial port of the singlechip;

a ninth pin (3A) of the exclusive-OR gate logic chip (U1) is sequentially connected with a third resistor (R3) and a fourth resistor (R4) in series and is connected to a signal DIN, and a fifth resistor (R5) and a first diode (D1) are sequentially connected in parallel; wherein DIN is connected to the TX pin of the RS232 level device

A tenth pin (3B) of the exclusive-OR gate logic chip (U1) is connected to a 5V power supply through a first resistor (R1) and connected to ground through JP 1; so JP1 is a shorting pad for providing on-off state of the weld;

twelfth and thirteenth pins (4A and 4B) of the exclusive OR gate logic chip (U1) are connected to ground.

2. The TTL-to-compatible RS232 level shifter circuit of claim 1, comprising:

the exclusive-OR gate logic chip (U1) is a 4-way two-input exclusive-OR gate logic chip.

3. The TTL-to-compatible RS232 level shifter circuit of claim 1, comprising:

the type of the exclusive-OR gate logic chip (U1) is SN74AHC86PWR.

4. The TTL-to-compatible RS232 level shifter circuit of claim 1, comprising:

and D1 is a voltage-stabilizing diode, and the model is BZT52C5V1S.

5. The TTL-to-compatible RS232 level shifter circuit of claim 1, comprising:

the first resistor (R1) is 47K.

6. The TTL-to-compatible RS232 level shifter circuit of claim 1, comprising:

the second resistance (R2) is 100R.

7. The TTL-to-compatible RS232 level shifter circuit of claim 1, comprising:

the third resistor (R3) is 1K.

8. The TTL-to-compatible RS232 level shifter circuit of claim 1, comprising:

the fourth resistor (R4) is 1K.

9. The TTL-to-compatible RS232 level shifter circuit of claim 1, comprising:

the fifth resistor (R5) is 47K.

10. The TTL-to-compatible RS232 level shifter circuit of claim 1, comprising:

the sixth resistance (R6) is 100R.