CN219123219U

CN219123219U - Semiconductor packaging structure

Info

Publication number: CN219123219U
Application number: CN202223599497.2U
Authority: CN
Inventors: 李伟聪; 文雨; 姜春亮
Original assignee: Shenzhen Vergiga Semiconductor Co Ltd
Current assignee: Shenzhen Vergiga Semiconductor Co Ltd
Priority date: 2022-12-29
Filing date: 2022-12-29
Publication date: 2023-06-02
Anticipated expiration: 2032-12-29

Abstract

The application discloses semiconductor packaging structure, this semiconductor packaging structure include slide glass platform and chip module, and the chip module sets up on the slide glass platform, and the chip module includes first chip and second chip, and partial second chip is located between first chip and the slide glass platform, and the second chip includes negative pole face and the positive pole face of relative setting, and the negative pole face is carried away from the slide glass platform. The packaging area of the chip module can be reduced by the scheme.

Description

Semiconductor packaging structure

Technical Field

The application relates to the technical field of semiconductors, in particular to a semiconductor packaging structure.

Background

An insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is a novel power electronic device in which a MOS field effect transistor and a bipolar transistor are combined. The power transistor has the advantages of easiness in driving and controlling, low on-state voltage, high on-state current and low loss, is one of core electronic components in a modern power electronic circuit, and is widely applied to various fields of national economy such as communication, energy, traffic, industry, medicine, household appliances, aerospace and the like. The application of the IGBT plays an extremely important role in improving the performance of a power electronic system.

Since IGBTs have no reverse turn-on capability, IGBTs currently on the market are packaged together in parallel with fast recovery diodes (Fast Recovery Diode, FRD) to achieve freewheeling capability. However, for chips with currents exceeding 75A, the IGBT and FRD may not be packaged into a package frame with a limited area due to the large chip area.

Disclosure of Invention

The application provides a semiconductor packaging structure which can reduce the packaging area of a chip module.

The application provides a semiconductor packaging structure, including:

a slide holder;

the chip module is arranged on the carrying platform, the chip module comprises a first chip and a second chip, part of the second chip is positioned between the first chip and the carrying platform, the second chip comprises a cathode surface and an anode surface which are oppositely arranged, and the cathode surface faces away from the carrying platform.

In the semiconductor packaging structure provided by the application, the semiconductor packaging structure further comprises a bonding pad module and a pin module, wherein the chip module and the pin module are respectively connected with the bonding pad module.

In the semiconductor packaging structure provided by the application, the pad module comprises a gate pad, a driver source pad, a source pad and a drain pad, wherein the gate pad, the driver source pad and the source pad are all spaced from the carrier, and the drain pad is connected with the carrier.

In the semiconductor packaging structure provided by the application, the first chip is provided with a gate pressure welding point and a source pressure welding point, the gate pressure welding point is connected with the gate welding point through a gate lead, the source pressure welding point is connected with the source welding point through a driver source lead, and the source pressure welding point is connected with the source welding point through a source lead.

In the semiconductor packaging structure provided by the application, the cathode surface of the second chip is connected with the drain electrode bonding pad through the drain electrode lead.

In the semiconductor package structure provided by the application, the pin module comprises a gate pin, a driver source pin, a source pin and a drain pin, wherein the gate pin is connected with the gate pad, the driver source pin is connected with the driver source pad, the source pin is connected with the source pad, and the drain pin is connected with the drain pad.

In the semiconductor packaging structure provided by the application, a first magnetic connection region is arranged on the first chip, a second magnetic connection region is arranged on the second chip, and the first magnetic connection region is magnetically connected with the second magnetic connection region.

In the semiconductor packaging structure provided by the application, the lengths of the first magnetic connection region and the second magnetic connection region are 1000 um-2000 um.

In the semiconductor packaging structure provided by the application, the widths of the first magnetic connection region and the second magnetic connection region are 1000 um-2000 um.

In the semiconductor packaging structure provided by the application, the thicknesses of the first magnetic connection region and the second magnetic connection region are 1000 um-3000 um.

In summary, the semiconductor packaging structure provided by the application comprises a carrying platform and a chip module, wherein the chip module is arranged on the carrying platform, the chip module comprises a first chip and a second chip, a part of the second chip is positioned between the first chip and the carrying platform, the second chip comprises a cathode surface and an anode surface which are oppositely arranged, and the cathode surface is opposite to the carrying platform. According to the scheme, the second chip is inverted, and the second chip and part of the first chip are overlapped, so that the packaging area of the chip module is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present application.

Fig. 2 is a schematic structural diagram of an IGBT chip according to an embodiment of the present application.

Fig. 3 is a schematic structural diagram of an FRD chip according to an embodiment of the present application.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the present application may have the same meaning or may have different meanings, a particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

In the following description, suffixes such as "module", "component", or "unit" for representing elements are used only for facilitating the description of the present application, and are not of specific significance per se. Thus, "module," "component," or "unit" may be used in combination.

In the description of the present application, it should be noted that the positional or positional relationship indicated by the terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are based on the positional or positional relationship shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Since IGBTs have no reverse turn-on capability, IGBTs currently on the market are packaged together in parallel with fast recovery diodes (Fast Recovery Diode, FRD) to achieve freewheeling capability. However, for chips with currents exceeding 75A, the IGBT and FRD may not be packaged into a package module with a limited area due to the large chip area.

Based on this, the embodiment of the application provides a semiconductor packaging structure, and the technical scheme shown in the application will be described in detail through specific embodiments. The following description of the embodiments is not intended to limit the priority of the embodiments.

Referring to fig. 1-3, the semiconductor package may include a package frame 1000. The package frame 1000 has a stage 100, and the stage 100 is provided with a chip module 10.

The chip module 10 includes a first chip 11 and a second chip 12, a portion of the second chip 12 is located between the first chip 11 and the stage 100, the second chip 12 includes a cathode surface and an anode surface that are oppositely disposed, and the cathode surface faces away from the stage 100.

It should be noted that, the first chip 11 is provided with a first magnetic connection region 111, the second chip 12 is provided with a second magnetic connection region 121, and the first magnetic connection region 111 is magnetically connected to the second magnetic connection region 121.

In some embodiments, the first magnetic connection region 111 and the second magnetic connection region 121 may be composed of ferroferric oxide, or may be composed of a magnetic alloy material composed of iron/aluminum/boron and/or other rare earth metals. It will be appreciated that the first magnetic connection region 111 and the second magnetic connection region 121 are of opposite polarity such that the first magnetic connection region 111 and the second magnetic connection region 121 attract each other to form a good electrical connection.

In another embodiment, one of the first magnetic connection region 111 and the second magnetic connection region 121 may be made of ferroferric oxide or a magnetic alloy material made of iron/aluminum/boron/or other rare earth metals, and the other may be made of metallic aluminum or not treated, forming only the contact window. It will be appreciated that the first magnetic connection region 111 and the second magnetic connection region 121 may also attract each other to form a good electrical connection.

In the embodiment of the present application, the lengths of the first magnetic connection region 111 and the second magnetic connection region 121 are 1000um to 2000um. The widths of the first magnetic connection region 111 and the second magnetic connection region 121 are 1000um to 2000um. The thickness of the first magnetic connection region 111 and the second magnetic connection region 121 is 1000um to 3000um.

In some embodiments, the semiconductor package structure may further include a pad module 20 and a pin module 30, and the chip module 10 and the pin module 30 are connected to the pad module 20, respectively.

The pad module 20 includes a gate pad 21, a driver source pad 22, a source pad 23 and a drain pad 24, where the gate pad 21, the driver source pad 22 and the source pad 23 are spaced from the stage 100, and the drain pad 24 is connected to the stage 100.

The lead module 30 includes a gate lead 31, a driver source lead 3332, a source lead 33, and a drain lead 34. The gate lead 31 is connected to the gate pad 21 for connecting an external gate signal; the driver source pin 3332 is connected to the driver source pad 22 for connecting external driver source signals; source lead 33 is connected to source pad 23 for connecting an external source signal; drain lead 34 is connected to drain pad 24 for connection to an external drain signal.

In some embodiments, the first chip 11 has a gate pad 112 and a source pad 113 thereon. The gate pad 112 is connected to the gate pad 21 through a gate lead, the source pad 113 is connected to the driver source pad 22 through a driver source lead, and the source pad 113 is connected to the source pad 23 through a source lead. The cathode side of the second chip 12 is connected to the drain pad 24 by a drain lead. The first chip 11 may form a good electrical connection with the stage 100 by means of solder, i.e. the drain of the first chip 11 is connected to the drain pin 34.

The number of the gate leads, the driver source leads, the source leads and the drain leads may be adjusted according to practical situations. For example, 1, 2, 3, 4, 5, or the like.

In the embodiment of the present application, the first chip 11 is an IGBT chip, and the second chip 12 is an FRD chip.

In summary, the semiconductor packaging structure provided in the embodiment of the application includes a carrier 100 and a chip module 10, the chip module 10 is disposed on the carrier 100, the chip module 10 includes a first chip 11 and a second chip 12, a part of the second chip 12 is located between the first chip 11 and the carrier 100, the second chip 12 includes a cathode surface and an anode surface which are oppositely disposed, and the cathode surface faces away from the carrier 100. The second chip 12 is flipped, and the second chip 12 and part of the first chip 11 are overlapped, so that the packaging area of the chip module 10 is reduced, and a larger area of chip can be accommodated on the stage 100 with the same size.

The foregoing has described in detail the semiconductor package structure provided herein with specific examples for the purpose of illustrating the principles and embodiments of the present application, the foregoing examples being provided solely to assist in understanding the core concept of the present application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.

Claims

1. A semiconductor package structure, comprising:

a slide holder;

2. The semiconductor package according to claim 1, further comprising a pad module and a pin module, wherein the chip module and the pin module are connected to the pad module, respectively.

3. The semiconductor package according to claim 2, wherein the pad module comprises a gate pad, a driver source pad, a source pad, and a drain pad, each of the gate pad, the driver source pad, and the source pad having a space therebetween with the stage, the drain pad being connected with the stage.

4. The semiconductor package according to claim 3, wherein the first chip has a gate pad and a source pad, the gate pad being connected to the gate pad by a gate lead, the source pad being connected to the driver source pad by a driver source lead, the source pad being connected to the source pad by a source lead.

5. The semiconductor package according to claim 3, wherein the cathode surface of the second chip is connected to the drain pad through a drain lead.

6. The semiconductor package according to claim 3, wherein the lead module comprises a gate lead, a driver source lead, a source lead, and a drain lead, the gate lead being connected to the gate pad, the driver source lead being connected to the driver source pad, the source lead being connected to the source pad, the drain lead being connected to the drain pad.

7. The semiconductor package according to claim 1, wherein a first magnetic connection region is disposed on the first chip, a second magnetic connection region is disposed on the second chip, and the first magnetic connection region is magnetically connected to the second magnetic connection region.

8. The semiconductor package according to claim 7, wherein the first and second magnetic connection regions each have a length of 1000um to 2000um.

9. The semiconductor package according to claim 7 or 8, wherein the first magnetic connection region and the second magnetic connection region each have a width of 1000um to 2000um.

10. The semiconductor package according to claim 7 or 8, wherein the first magnetic connection region and the second magnetic connection region each have a thickness of 1000um to 3000um.